diff --git a/Documentation/devicetree/bindings/riscv/physical-memory.yaml b/Documentation/devicetree/bindings/riscv/physical-memory.yaml
new file mode 100644
index 000000000000..deb49b34672f
--- /dev/null
+++ b/Documentation/devicetree/bindings/riscv/physical-memory.yaml
@@ -0,0 +1,101 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/riscv/physical-memory.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: RISC-V Physical Memory Regions
+
+maintainers:
+  - Samuel Holland <samuel.holland@sifive.com>
+
+description:
+  The RISC-V Privileged Architecture defines a number of Physical Memory
+  Attributes (PMAs) which apply to a given region of memory. These include the
+  types of accesses (read, write, execute, LR/SC, and/or AMO) allowed within
+  a region, the supported access widths and alignments, the cacheability and
+  coherence of the region, and whether or not accesses to the region may have
+  side effects.
+
+  Some RISC-V platforms provide multiple physical address mappings for main
+  memory or certain peripherals. Each alias of a region generally has different
+  PMAs (e.g. cacheable vs non-cacheable), which allows software to dynamically
+  select the PMAs for an access by referencing the corresponding alias.
+
+  The RISC-V Supervisor Domains specification defines a platform-specific
+  Physical Address Width (PAW), which describes the largest physical address
+  supported by a platform. Any access to an address >= 2^PAW is guaranteed to
+  raise an access fault, and therefore metadata (e.g. Memory Protection Tables)
+  need not be maintained for those addresses.
+
+  On DT-based RISC-V platforms, all of this information is provided by the
+  riscv,physical-memory-regions property of the root node.
+
+properties:
+  $nodename:
+    const: '/'
+
+  riscv,physical-memory-regions:
+    $ref: /schemas/types.yaml#/definitions/uint32-matrix
+    description:
+      A table of physical memory regions. The first entry in the table must
+      cover the entire range of physical addresses supported by the platform
+      (i.e. 0 to 2^PAW-1) and provides the default PMAs for all addresses not
+      covered by another table entry. Remaining table entries provide PMAs for
+      more specific physical memory regions, which must be contained within the
+      range of entry 0, but which must not overlap with each other.
+    minItems: 1
+    maxItems: 256
+    items:
+      minItems: 4
+      maxItems: 6
+      additionalItems: true
+      items:
+        - description: CPU physical address (#address-cells)
+        - description: >
+            Size (#size-cells). For entry 0, if the size is zero, the size is
+            assumed to be 2^(32 * #size-cells).
+        - description: >
+            Flags describing the most restrictive PMAs for any address within
+            the region.
+
+            The least significant byte indicates the types of accesses allowed
+            for this region. Note that a memory region may support a type of
+            access (e.g. AMOs) even if the CPU does not.
+
+            The next byte describes the cacheability, coherence, idempotency,
+            and ordering PMAs for this region. It also includes a flag to
+            indicate that accesses to a region are unsafe and must be
+            prohibited by software (for example using PMPs or Smmpt).
+
+            The third byte is reserved for future PMAs.
+
+            The most significant byte is the index of the lowest-numbered entry
+            which this entry is an alias of, if any. Aliases need not be the
+            same size, for example if a smaller memory region repeats within a
+            larger alias.
+        - description: Reserved for describing future PMAs
+
+additionalProperties: true
+
+examples:
+  - |
+    #include <dt-bindings/riscv/physical-memory.h>
+
+    / {
+      compatible = "starfive,jh7100";
+      #address-cells = <2>;
+      #size-cells = <2>;
+      riscv,physical-memory-regions =
+          <0x00 0x00000000 0x40 0x00000000 (PMA_RW | PMA_IO) 0x0>,
+          <0x00 0x18000000 0x00 0x00020000 (PMA_RWX | PMA_NONCACHEABLE_MEMORY) 0x0>,
+          <0x00 0x18080000 0x00 0x00020000 (PMA_RWX | PMA_NONCACHEABLE_MEMORY) 0x0>,
+          <0x00 0x41000000 0x00 0x1f000000 (PMA_RWX | PMA_NONCACHEABLE_MEMORY) 0x0>,
+          <0x00 0x61000000 0x00 0x1f000000 (PMA_RWXA | PMA_NONCOHERENT_MEMORY | PMR_ALIAS(3)) 0x0>,
+          <0x00 0x80000000 0x08 0x00000000 (PMA_RWXA | PMA_NONCOHERENT_MEMORY) 0x0>,
+          <0x10 0x00000000 0x08 0x00000000 (PMA_RWX | PMA_NONCACHEABLE_MEMORY | PMR_ALIAS(5)) 0x0>,
+          <0x20 0x00000000 0x10 0x00000000 (PMA_RWX | PMA_NONCACHEABLE_MEMORY) 0x0>,
+          <0x30 0x00000000 0x10 0x00000000 (PMA_RWXA | PMA_NONCOHERENT_MEMORY | PMR_ALIAS(7)) 0x0>;
+    };
+
+...
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index 1c5544401530..2d2c2fd886b1 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -624,6 +624,9 @@ config RISCV_ISA_SVPBMT
 
 	   The Svpbmt extension is only available on 64-bit cpus.
 
+	   This option also controls selection of memory type based on
+	   physical memory aliases.
+
 	   If you don't know what to do here, say Y.
 
 config TOOLCHAIN_HAS_V
diff --git a/arch/riscv/Kconfig.errata b/arch/riscv/Kconfig.errata
index e318119d570d..5b1fe6a8d728 100644
--- a/arch/riscv/Kconfig.errata
+++ b/arch/riscv/Kconfig.errata
@@ -86,6 +86,7 @@ config ERRATA_THEAD_MAE
 	bool "Apply T-Head's memory attribute extension (XTheadMae) errata"
 	depends on ERRATA_THEAD && 64BIT && MMU
 	select RISCV_ALTERNATIVE_EARLY
+	select RISCV_ISA_SVPBMT
 	default y
 	help
 	  This will apply the memory attribute extension errata to handle the
diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs
index a9c3d2f6debc..3383b2140bcd 100644
--- a/arch/riscv/Kconfig.socs
+++ b/arch/riscv/Kconfig.socs
@@ -85,4 +85,9 @@ config SOC_CANAAN_K210
 	help
 	  This enables support for Canaan Kendryte K210 SoC platform hardware.
 
+config SOC_SIFIVE_EIC7700
+	bool "ESWIN EIC7700x SoCs"
+	help
+	  This enables support for ESWIN EIC7700X SoC platform hardware.
+
 endmenu # "SoC selection"
diff --git a/arch/riscv/boot/dts/Makefile b/arch/riscv/boot/dts/Makefile
index 64a898da9aee..29a97a663ea2 100644
--- a/arch/riscv/boot/dts/Makefile
+++ b/arch/riscv/boot/dts/Makefile
@@ -1,6 +1,7 @@
 # SPDX-License-Identifier: GPL-2.0
 subdir-y += allwinner
 subdir-y += canaan
+subdir-y += eswin
 subdir-y += microchip
 subdir-y += renesas
 subdir-y += sifive
diff --git a/arch/riscv/boot/dts/eswin/Makefile b/arch/riscv/boot/dts/eswin/Makefile
new file mode 100644
index 000000000000..49dccee69b5a
--- /dev/null
+++ b/arch/riscv/boot/dts/eswin/Makefile
@@ -0,0 +1,2 @@
+# SPDX-License-Identifier: GPL-2.0
+dtb-$(CONFIG_SOC_SIFIVE_EIC7700) += eic7700-hifive-premier-p550.dtb eic7700-milkv-megrez.dtb eic7700-pine64-starpro64.dtb
diff --git a/arch/riscv/boot/dts/eswin/eic7700-arch.dtsi b/arch/riscv/boot/dts/eswin/eic7700-arch.dtsi
new file mode 100644
index 000000000000..c0d9f396a50c
--- /dev/null
+++ b/arch/riscv/boot/dts/eswin/eic7700-arch.dtsi
@@ -0,0 +1,543 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Include file for Eswin EIC7700 SoC's cpu.
+ *
+ * Copyright 2024, Beijing ESWIN Computing Technology Co., Ltd.. All rights reserved.
+ * SPDX-License-Identifier: GPL-2.0
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, version 2.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <https://www.gnu.org/licenses/>.
+ */
+
+#include <dt-bindings/clock/eic7700-clock.h>
+
+#define UART0_INT	100
+#define UART1_INT	101
+#define UART2_INT	102
+#define UART3_INT	103
+#define UART4_INT	104
+
+/ {
+	#address-cells = <2>;
+	#size-cells = <2>;
+	compatible = "eic7700-dev";
+
+	L64: cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		timebase-frequency = <RTCCLK_FREQ>;
+		L17: cpu@0 {
+			clock-frequency = <0>;
+			compatible = "eswin,eic770x", "riscv";
+			d-cache-block-size = <64>;
+			d-cache-sets = <128>;
+			d-cache-size = <32768>;
+			d-tlb-sets = <1>;
+			d-tlb-size = <32>;
+			device_type = "cpu";
+			hardware-exec-breakpoint-count = <4>;
+			hwpf-distanceBits = <6>;
+			hwpf-hitCacheThrdBits = <5>;
+			hwpf-hitMSHRThrdBits = <4>;
+			hwpf-l2pfPoolSize = <10>;
+			hwpf-nIssQEnt = <6>;
+			hwpf-nPrefetchQueueEntries = <8>;
+			hwpf-nStreams = <16>;
+			hwpf-qFullnessThrdBits = <4>;
+			hwpf-windowBits = <6>;
+			i-cache-block-size = <64>;
+			i-cache-sets = <128>;
+			i-cache-size = <32768>;
+			i-tlb-sets = <1>;
+			i-tlb-size = <32>;
+			mmu-type = "riscv,sv48";
+			next-level-cache = <&L15>;
+			reg = <0x0>;
+			riscv,isa-base = "rv64i";
+			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "h", "zicsr", "zifencei", "zba", "zbb", "sscofpmf";
+			riscv,pmpgranularity = <4096>;
+			riscv,pmpregions = <8>;
+			sifive,buserror = <&L16>;
+			status = "okay";
+			timebase-frequency = <RTCCLK_FREQ>;
+			tlb-split;
+			clocks = <&d0_clock EIC7700_CLK_CPU_EXT_SRC_CORE_CLK_0>;
+			operating-points-v2 = <&d0_cpu_opp_table>;
+			L14: interrupt-controller {
+				#interrupt-cells = <1>;
+				compatible = "riscv,cpu-intc";
+				interrupt-controller;
+			};
+			L13: pmu {
+				riscv,raw-event-to-mhpmcounters = <0x0 0x0 0xffffffff 0xff 0x78
+					0x0 0x1 0xffffffff 0xfffe07ff 0x78
+					0x0 0x2 0xffffffff 0xfffe00ff 0x78
+					0x0 0x3 0xfffffffc 0xff 0x78
+					0x0 0x4 0xffffffc0 0xff 0x78
+					0x0 0x5 0xffffffff 0xfffffdff 0x78
+					0x0 0x6 0xfffffe00 0x110204ff 0x78
+					0x0 0x7 0xffffffff 0xf00000ff 0x78
+					0x0 0x8 0xfffffe04 0xff 0x78
+					0x0 0x9 0xffffffff 0xffffc0ff 0x78
+					0x0 0xa 0xffffffff 0xf00000ff 0x78
+					0x0 0xb 0xffffffff 0xfffffcff 0x78
+					0x0 0xc 0xfffffff0 0xff 0x78
+					0x0 0xd 0xffffffff 0x800000ff 0x78
+					0x0 0xe 0xffffffff 0xf80000ff 0x78
+					0x0 0xf 0xfffffffc 0xff 0x78>;
+				riscv,event-to-mhpmcounters = <0x01 0x01 0x01 0x02 0x02 0x02 0x4 0x6 0x78 0x10009 0x10009 0x78 0x10019 0x10019 0x78 0x10021 0x10021 0x78>;
+				riscv,event-to-mhpmevent = <0x4 0x0 0x202 0x5 0x0 0x4000 0x6 0x0 0x2001 0x10009 0x0 0x102 0x10019 0x0 0x1002 0x10021 0x0 0x802>;
+				compatible = "riscv,pmu0", "riscv,pmu";
+				interrupts-extended = <&L14 13>;
+			};
+		};
+		L22: cpu@1 {
+			clock-frequency = <0>;
+			compatible = "eswin,eic770x", "riscv";
+			d-cache-block-size = <64>;
+			d-cache-sets = <128>;
+			d-cache-size = <32768>;
+			d-tlb-sets = <1>;
+			d-tlb-size = <32>;
+			device_type = "cpu";
+			hardware-exec-breakpoint-count = <4>;
+			hwpf-distanceBits = <6>;
+			hwpf-hitCacheThrdBits = <5>;
+			hwpf-hitMSHRThrdBits = <4>;
+			hwpf-l2pfPoolSize = <10>;
+			hwpf-nIssQEnt = <6>;
+			hwpf-nPrefetchQueueEntries = <8>;
+			hwpf-nStreams = <16>;
+			hwpf-qFullnessThrdBits = <4>;
+			hwpf-windowBits = <6>;
+			i-cache-block-size = <64>;
+			i-cache-sets = <128>;
+			i-cache-size = <32768>;
+			i-tlb-sets = <1>;
+			i-tlb-size = <32>;
+			mmu-type = "riscv,sv48";
+			next-level-cache = <&L20>;
+			reg = <0x1>;
+			riscv,isa-base = "rv64i";
+			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "h", "zicsr", "zifencei", "zba", "zbb", "sscofpmf";
+			riscv,pmpgranularity = <4096>;
+			riscv,pmpregions = <8>;
+			sifive,buserror = <&L21>;
+			status = "okay";
+			timebase-frequency = <RTCCLK_FREQ>;
+			tlb-split;
+			clocks = <&d0_clock EIC7700_CLK_CPU_EXT_SRC_CORE_CLK_1>;
+			operating-points-v2 = <&d0_cpu_opp_table>;
+			L19: interrupt-controller {
+				#interrupt-cells = <1>;
+				compatible = "riscv,cpu-intc";
+				interrupt-controller;
+			};
+			L18: pmu {
+				riscv,raw-event-to-mhpmcounters = <0x0 0x0 0xffffffff 0xff 0x78
+					0x0 0x1 0xffffffff 0xfffe07ff 0x78
+					0x0 0x2 0xffffffff 0xfffe00ff 0x78
+					0x0 0x3 0xfffffffc 0xff 0x78
+					0x0 0x4 0xffffffc0 0xff 0x78
+					0x0 0x5 0xffffffff 0xfffffdff 0x78
+					0x0 0x6 0xfffffe00 0x110204ff 0x78
+					0x0 0x7 0xffffffff 0xf00000ff 0x78
+					0x0 0x8 0xfffffe04 0xff 0x78
+					0x0 0x9 0xffffffff 0xffffc0ff 0x78
+					0x0 0xa 0xffffffff 0xf00000ff 0x78
+					0x0 0xb 0xffffffff 0xfffffcff 0x78
+					0x0 0xc 0xfffffff0 0xff 0x78
+					0x0 0xd 0xffffffff 0x800000ff 0x78
+					0x0 0xe 0xffffffff 0xf80000ff 0x78
+					0x0 0xf 0xfffffffc 0xff 0x78>;
+				riscv,event-to-mhpmcounters = <0x01 0x01 0x01 0x02 0x02 0x02 0x4 0x6 0x78 0x10009 0x10009 0x78 0x10019 0x10019 0x78 0x10021 0x10021 0x78>;
+				riscv,event-to-mhpmevent = <0x4 0x0 0x202 0x5 0x0 0x4000 0x6 0x0 0x2001 0x10009 0x0 0x102 0x10019 0x0 0x1002 0x10021 0x0 0x802>;
+				compatible = "riscv,pmu0", "riscv,pmu";
+				interrupts-extended = <&L19 13>;
+			};
+		};
+		L27: cpu@2 {
+			clock-frequency = <0>;
+			compatible = "eswin,eic770x", "riscv";
+			d-cache-block-size = <64>;
+			d-cache-sets = <128>;
+			d-cache-size = <32768>;
+			d-tlb-sets = <1>;
+			d-tlb-size = <32>;
+			device_type = "cpu";
+			hardware-exec-breakpoint-count = <4>;
+			hwpf-distanceBits = <6>;
+			hwpf-hitCacheThrdBits = <5>;
+			hwpf-hitMSHRThrdBits = <4>;
+			hwpf-l2pfPoolSize = <10>;
+			hwpf-nIssQEnt = <6>;
+			hwpf-nPrefetchQueueEntries = <8>;
+			hwpf-nStreams = <16>;
+			hwpf-qFullnessThrdBits = <4>;
+			hwpf-windowBits = <6>;
+			i-cache-block-size = <64>;
+			i-cache-sets = <128>;
+			i-cache-size = <32768>;
+			i-tlb-sets = <1>;
+			i-tlb-size = <32>;
+			mmu-type = "riscv,sv48";
+			next-level-cache = <&L25>;
+			reg = <0x2>;
+			riscv,isa-base = "rv64i";
+			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "h", "zicsr", "zifencei", "zba", "zbb", "sscofpmf";
+			riscv,pmpgranularity = <4096>;
+			riscv,pmpregions = <8>;
+			sifive,buserror = <&L26>;
+			status = "okay";
+			timebase-frequency = <RTCCLK_FREQ>;
+			tlb-split;
+			clocks = <&d0_clock EIC7700_CLK_CPU_EXT_SRC_CORE_CLK_2>;
+			operating-points-v2 = <&d0_cpu_opp_table>;
+			L24: interrupt-controller {
+				#interrupt-cells = <1>;
+				compatible = "riscv,cpu-intc";
+				interrupt-controller;
+			};
+			L23: pmu {
+				riscv,raw-event-to-mhpmcounters = <0x0 0x0 0xffffffff 0xff 0x78
+					0x0 0x1 0xffffffff 0xfffe07ff 0x78
+					0x0 0x2 0xffffffff 0xfffe00ff 0x78
+					0x0 0x3 0xfffffffc 0xff 0x78
+					0x0 0x4 0xffffffc0 0xff 0x78
+					0x0 0x5 0xffffffff 0xfffffdff 0x78
+					0x0 0x6 0xfffffe00 0x110204ff 0x78
+					0x0 0x7 0xffffffff 0xf00000ff 0x78
+					0x0 0x8 0xfffffe04 0xff 0x78
+					0x0 0x9 0xffffffff 0xffffc0ff 0x78
+					0x0 0xa 0xffffffff 0xf00000ff 0x78
+					0x0 0xb 0xffffffff 0xfffffcff 0x78
+					0x0 0xc 0xfffffff0 0xff 0x78
+					0x0 0xd 0xffffffff 0x800000ff 0x78
+					0x0 0xe 0xffffffff 0xf80000ff 0x78
+					0x0 0xf 0xfffffffc 0xff 0x78>;
+				riscv,event-to-mhpmcounters = <0x01 0x01 0x01 0x02 0x02 0x02 0x4 0x6 0x78 0x10009 0x10009 0x78 0x10019 0x10019 0x78 0x10021 0x10021 0x78>;
+				riscv,event-to-mhpmevent = <0x4 0x0 0x202 0x5 0x0 0x4000 0x6 0x0 0x2001 0x10009 0x0 0x102 0x10019 0x0 0x1002 0x10021 0x0 0x802>;
+				compatible = "riscv,pmu0", "riscv,pmu";
+				interrupts-extended = <&L24 13>;
+			};
+		};
+		L32: cpu@3 {
+			clock-frequency = <0>;
+			compatible = "eswin,eic770x", "riscv";
+			d-cache-block-size = <64>;
+			d-cache-sets = <128>;
+			d-cache-size = <32768>;
+			d-tlb-sets = <1>;
+			d-tlb-size = <32>;
+			device_type = "cpu";
+			hardware-exec-breakpoint-count = <4>;
+			hwpf-distanceBits = <6>;
+			hwpf-hitCacheThrdBits = <5>;
+			hwpf-hitMSHRThrdBits = <4>;
+			hwpf-l2pfPoolSize = <10>;
+			hwpf-nIssQEnt = <6>;
+			hwpf-nPrefetchQueueEntries = <8>;
+			hwpf-nStreams = <16>;
+			hwpf-qFullnessThrdBits = <4>;
+			hwpf-windowBits = <6>;
+			i-cache-block-size = <64>;
+			i-cache-sets = <128>;
+			i-cache-size = <32768>;
+			i-tlb-sets = <1>;
+			i-tlb-size = <32>;
+			mmu-type = "riscv,sv48";
+			next-level-cache = <&L30>;
+			reg = <0x3>;
+			riscv,isa-base = "rv64i";
+			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "h", "zicsr", "zifencei", "zba", "zbb", "sscofpmf";
+			riscv,pmpgranularity = <4096>;
+			riscv,pmpregions = <8>;
+			sifive,buserror = <&L31>;
+			status = "okay";
+			timebase-frequency = <RTCCLK_FREQ>;
+			tlb-split;
+			clocks = <&d0_clock EIC7700_CLK_CPU_EXT_SRC_CORE_CLK_3>;
+			operating-points-v2 = <&d0_cpu_opp_table>;
+			L29: interrupt-controller {
+				#interrupt-cells = <1>;
+				compatible = "riscv,cpu-intc";
+				interrupt-controller;
+			};
+			L28: pmu {
+				riscv,raw-event-to-mhpmcounters = <0x0 0x0 0xffffffff 0xff 0x78
+					0x0 0x1 0xffffffff 0xfffe07ff 0x78
+					0x0 0x2 0xffffffff 0xfffe00ff 0x78
+					0x0 0x3 0xfffffffc 0xff 0x78
+					0x0 0x4 0xffffffc0 0xff 0x78
+					0x0 0x5 0xffffffff 0xfffffdff 0x78
+					0x0 0x6 0xfffffe00 0x110204ff 0x78
+					0x0 0x7 0xffffffff 0xf00000ff 0x78
+					0x0 0x8 0xfffffe04 0xff 0x78
+					0x0 0x9 0xffffffff 0xffffc0ff 0x78
+					0x0 0xa 0xffffffff 0xf00000ff 0x78
+					0x0 0xb 0xffffffff 0xfffffcff 0x78
+					0x0 0xc 0xfffffff0 0xff 0x78
+					0x0 0xd 0xffffffff 0x800000ff 0x78
+					0x0 0xe 0xffffffff 0xf80000ff 0x78
+					0x0 0xf 0xfffffffc 0xff 0x78>;
+				riscv,event-to-mhpmcounters = <0x01 0x01 0x01 0x02 0x02 0x02 0x4 0x6 0x78 0x10009 0x10009 0x78 0x10019 0x10019 0x78 0x10021 0x10021 0x78>;
+				riscv,event-to-mhpmevent = <0x4 0x0 0x202 0x5 0x0 0x4000 0x6 0x0 0x2001 0x10009 0x0 0x102 0x10019 0x0 0x1002 0x10021 0x0 0x802>;
+				compatible = "riscv,pmu0", "riscv,pmu";
+				interrupts-extended = <&L29 13>;
+			};
+		};
+	};
+	L50: memory@80000000 {
+		compatible = "sifive,axi4-mem-port", "sifive,axi4-port", "sifive,mem-port";
+		device_type = "memory";
+		reg = <0x0 0x80000000 0x7f 0x80000000>;
+		sifive,port-width-bytes = <32>;
+	};
+	SOC: soc {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		compatible = "SiFive,FU800-soc", "fu800-soc", "sifive-soc", "simple-bus";
+		ranges;
+		L40: authentication-controller {
+			compatible = "sifive,authentication0";
+			sifive,auth-types = "fuse";
+		};
+		L51: axi4-sys-port@40000000 {
+			#address-cells = <1>;
+			#size-cells = <1>;
+			compatible = "sifive,axi4-sys-port", "sifive,axi4-port", "sifive,sys-port", "simple-external-bus", "simple-bus";
+			ranges = <0x40000000 0x0 0x40000000 0x40000000>;
+			sifive,port-width-bytes = <16>;
+		};
+		L52: axi4-sys-port@8000000000 {
+			#address-cells = <2>;
+			#size-cells = <2>;
+			compatible = "sifive,axi4-sys-port", "sifive,axi4-port", "sifive,sys-port", "simple-external-bus", "simple-bus";
+			ranges = <0x80 0x0 0x80 0x0 0x180 0x0>;
+			sifive,port-width-bytes = <16>;
+		};
+		L46: basic-bus-blocker@200000 {
+			compatible = "sifive,basic-bus-blocker1";
+			reg = <0x0 0x200000 0x0 0x1000>;
+			reg-names = "control";
+		};
+		L43: basic-bus-blocker@202000 {
+			compatible = "sifive,basic-bus-blocker1";
+			reg = <0x0 0x202000 0x0 0x1000>;
+			reg-names = "control";
+		};
+		L48: basic-bus-blocker@204000 {
+			compatible = "sifive,basic-bus-blocker1";
+			reg = <0x0 0x204000 0x0 0x1000>;
+			reg-names = "control";
+		};
+		L54: burst-bundler@10010000 {
+			compatible = "sifive,burst-bundler0";
+			reg = <0x0 0x10010000 0x0 0x1000>;
+			reg-names = "control";
+		};
+		L16: bus-error-unit@hart0 {
+			compatible = "sifive,buserror";
+			interrupt-parent = <&plic0>;
+			interrupts = <517>;
+			reg = <0x0 0x1700000 0x0 0x1000>;
+			reg-names = "control";
+		};
+		L21: bus-error-unit@hart1 {
+			compatible = "sifive,buserror";
+			interrupt-parent = <&plic0>;
+			interrupts = <518>;
+			reg = <0x0 0x1701000 0x0 0x1000>;
+			reg-names = "control";
+		};
+		L26: bus-error-unit@hart2 {
+			compatible = "sifive,buserror";
+			interrupt-parent = <&plic0>;
+			interrupts = <519>;
+			reg = <0x0 0x1702000 0x0 0x1000>;
+			reg-names = "control";
+		};
+		L31: bus-error-unit@hart3 {
+			compatible = "sifive,buserror";
+			interrupt-parent = <&plic0>;
+			interrupts = <520>;
+			reg = <0x0 0x1703000 0x0 0x1000>;
+			reg-names = "control";
+		};
+		L7: cache-controller@2010000 {
+			cache-block-size = <64>;
+			cache-level = <3>;
+			cache-sets = <4096>;
+			cache-size = <4194304>;
+			cache-unified;
+			compatible = "sifive,eic7700";
+			interrupt-parent = <&plic0>;
+			interrupts = <1>, <3>, <4>, <2>;
+			next-level-cache = <&L9 &L10 &L11 &L50>;
+			reg = <0x0 0x2010000 0x0 0x4000 0x0 0x8000000 0x0 0x400000>;
+			reg-names = "control", "sideband";
+			sifive,a-mshr-count = <60>;
+			sifive,bank-count = <4>;
+			sifive,ecc-granularity = <8>;
+			sifive,max-master-id = <13>;
+			sifive,perfmon-counters = <6>;
+			numa-node-id = <0>;
+		};
+
+		L34: debug-controller@0 {
+			compatible = "sifive,debug-100", "riscv,debug-100";
+			debug-attach = "jtag";
+			reg = <0x0 0x0 0x0 0x1000>;
+			reg-names = "control";
+		};
+		L8: error-device@1000 {
+			compatible = "sifive,error0";
+			reg = <0x0 0x1000 0x0 0x3000 0x0 0x5000 0x0 0x13000 0x0 0x19000 0x0 0xe7000 0x0 0x114000 0x0 0xec000 0x0 0x201000 0x0 0x1000 0x0 0x203000 0x0 0x1000 0x0 0x205000 0x0 0x14fb000 0x0 0x1704000 0x0 0x8fc000 0x0 0x2014000 0x0 0x5fec000 0x0 0x8400000 0x0 0x3c00000 0x0 0x10000000 0x0 0x3000 0x0 0x10004000 0x0 0xc000 0x0 0x10011000 0x0 0x1f000 0x0 0x10034000 0x0 0x9fcc000 0x0 0x1a400000 0x0 0x5c00000>;
+		};
+		L9: error-device@10003000 {
+			compatible = "sifive,error0";
+			reg = <0x0 0x10003000 0x0 0x1000>;
+		};
+
+		plic0: interrupt-controller@c000000 {
+			#interrupt-cells = <1>;
+			compatible = "sifive,plic-1.0.0";
+			interrupt-controller;
+			interrupts-extended = <
+				&L14 0xffffffff &L14 9
+				&L19 0xffffffff &L19 9
+				&L24 0xffffffff &L24 9
+				&L29 0xffffffff &L29 9>;
+			reg = <0x0 0xc000000 0x0 0x4000000>;
+			reg-names = "control";
+			riscv,max-priority = <7>;
+			riscv,ndev = <520>;
+		};
+		L53: order-obliterator@10030000 {
+			compatible = "sifive,order-obliterator0";
+			interrupt-parent = <&plic0>;
+			interrupts = <516>;
+			reg = <0x0 0x10030000 0x0 0x4000>;
+			reg-names = "control";
+		};
+		L15: pl2@104000 {
+			cache-block-size = <64>;
+			cache-level = <2>;
+			cache-sets = <512>;
+			cache-size = <262144>;
+			cache-unified;
+			compatible = "sifive,pL2Cache0", "cache";
+			next-level-cache = <&L7>;
+			reg = <0x0 0x104000 0x0 0x4000>;
+			reg-names = "control";
+			sifive,ecc-granularity = <16>;
+			sifive,perfmon-counters = <6>;
+		};
+		L20: pl2@108000 {
+			cache-block-size = <64>;
+			cache-level = <2>;
+			cache-sets = <512>;
+			cache-size = <262144>;
+			cache-unified;
+			compatible = "sifive,pL2Cache0", "cache";
+			next-level-cache = <&L7>;
+			reg = <0x0 0x108000 0x0 0x4000>;
+			reg-names = "control";
+			sifive,ecc-granularity = <16>;
+			sifive,perfmon-counters = <6>;
+		};
+		L25: pl2@10c000 {
+			cache-block-size = <64>;
+			cache-level = <2>;
+			cache-sets = <512>;
+			cache-size = <262144>;
+			cache-unified;
+			compatible = "sifive,pL2Cache0", "cache";
+			next-level-cache = <&L7>;
+			reg = <0x0 0x10c000 0x0 0x4000>;
+			reg-names = "control";
+			sifive,ecc-granularity = <16>;
+			sifive,perfmon-counters = <6>;
+		};
+		L30: pl2@110000 {
+			cache-block-size = <64>;
+			cache-level = <2>;
+			cache-sets = <512>;
+			cache-size = <262144>;
+			cache-unified;
+			compatible = "sifive,pL2Cache0", "cache";
+			next-level-cache = <&L7>;
+			reg = <0x0 0x110000 0x0 0x4000>;
+			reg-names = "control";
+			sifive,ecc-granularity = <16>;
+			sifive,perfmon-counters = <6>;
+		};
+		L10: rom@1a000000 {
+			compatible = "ucbbar,cacheable-zero0";
+			reg = <0x0 0x1a000000 0x0 0x400000>;
+		};
+		L11: rom@3a000000 {
+			compatible = "ucbbar,cacheable-zero0";
+			reg = <0x0 0x3a000000 0x0 0x400000>;
+		};
+		L6: subsystem_pbus_clock {
+			#clock-cells = <0>;
+			clock-frequency = <10000000>;
+			clock-output-names = "subsystem_pbus_clock";
+			compatible = "fixed-clock";
+		};
+		L61: teststatus@4000 {
+			compatible = "sifive,test0";
+			reg = <0x0 0x4000 0x0 0x1000>;
+			reg-names = "control";
+		};
+		L45: tl-address-adjuster@20000000 {
+			#address-cells = <1>;
+			#size-cells = <1>;
+			compatible = "sifive,tl-inter-sys-port", "sifive,tl-port", "simple-external-bus", "simple-bus";
+			ranges = <0x20000000 0x0 0x20000000 0x1a000000 0x3a400000 0x0 0x3a400000 0x5c00000>;
+			sifive,port-width-bytes = <8>;
+		};
+		L42: tl-inter-mem-master-port@80000000 {
+			#address-cells = <2>;
+			#size-cells = <2>;
+			compatible = "sifive,tl-inter-mem-master-port", "sifive,tl-port", "sifive,inter-mem-master-port", "simple-external-bus", "simple-bus";
+			ranges = <0x0 0x80000000 0x0 0x80000000 0x7f 0x80000000>;
+			sifive,port-width-bytes = <32>;
+		};
+		L55: trace-encoder-0@100000 {
+			compatible = "sifive,trace0";
+			reg = <0x0 0x100000 0x0 0x1000>;
+			reg-names = "control";
+		};
+		L56: trace-encoder-1@101000 {
+			compatible = "sifive,trace0";
+			reg = <0x0 0x101000 0x0 0x1000>;
+			reg-names = "control";
+		};
+		L57: trace-encoder-2@102000 {
+			compatible = "sifive,trace0";
+			reg = <0x0 0x102000 0x0 0x1000>;
+			reg-names = "control";
+		};
+		L58: trace-encoder-3@103000 {
+			compatible = "sifive,trace0";
+			reg = <0x0 0x103000 0x0 0x1000>;
+			reg-names = "control";
+		};
+		L59: trace-funnel-0@18000 {
+			compatible = "sifive,trace0";
+			reg = <0x0 0x18000 0x0 0x1000>;
+			reg-names = "control";
+		};
+	};
+};
diff --git a/arch/riscv/boot/dts/eswin/eic7700-hifive-premier-p550.dts b/arch/riscv/boot/dts/eswin/eic7700-hifive-premier-p550.dts
new file mode 100644
index 000000000000..a9ed79f25530
--- /dev/null
+++ b/arch/riscv/boot/dts/eswin/eic7700-hifive-premier-p550.dts
@@ -0,0 +1,726 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree file for Eswin EIC7700 SoC.
+ *
+ * Copyright 2024, Beijing ESWIN Computing Technology Co., Ltd.. All rights reserved.
+ * SPDX-License-Identifier: GPL-2.0
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, version 2.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <https://www.gnu.org/licenses/>.
+ */
+
+/dts-v1/;
+
+#define RTCCLK_FREQ		1000000
+#define LSPCLK_FREQ		200000000
+#define CMA_SIZE		0x20000000
+
+#include "eic7700.dtsi"
+#include "eic7700-pinctrl-common.dtsi"
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/gpio/gpio.h>
+
+/* Clock frequency (in Hz) of the PCB crystal for rtcclk */
+
+/ {
+	#address-cells = <2>;
+	#size-cells = <2>;
+	model = "SiFive HiFive Premier P550";
+	compatible = "sifive,hifive-premier-p550", "eswin,eic7700";
+
+	aliases {
+		serial0 = &d0_uart0;
+		ethernet0 = &d0_gmac0;
+		ethernet1 = &d0_gmac1;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+
+	cpus {
+		timebase-frequency = <RTCCLK_FREQ>;
+	};
+
+	reserved-memory {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		linux,cma {
+			compatible = "shared-dma-pool";
+			reusable;
+			size = <0x0 CMA_SIZE>;
+			alignment = <0x0 0x1000>;
+			linux,cma-default;
+		};
+
+		npu0_reserved: sprammemory@59000000 {
+			no-map;
+			reg = <0x0 0x59000000 0x0 0x400000>;
+		};
+
+		lpcpu0_reserved: lpcpu@a0000000 {
+			no-map;
+			reg = <0x0 0xa0000000 0x0 0x100000>;
+		};
+
+		g2d_4GB_boundary_reserved_4k {
+			no-map;
+			reg = <0x0 0xfffff000 0x0 0x1000>;
+		};
+	};
+};
+
+&d0_clock {
+	status = "okay";
+};
+
+&d0_reset {
+	status = "okay";
+};
+
+&d0_pmu {
+	status = "okay";
+};
+
+&ddr0 {
+	status = "okay";
+};
+
+&ddr1 {
+	status = "okay";
+};
+
+&d0_cfg_noc {
+	status = "okay";
+};
+
+&d0_llc_noc {
+	status = "okay";
+	stat,0 = "TracePort:ddr0_p0_req";
+	stat,1 = "TracePort:ddr1_p0_req";
+};
+
+&d0_sys_noc {
+	status = "okay";
+
+	stat,0 = "TracePort:ddr0_p1_req",
+		 "InitFlow:mcput_snoc_mp/I/0";
+
+	stat,1 = "TracePort:ddr0_p2_req",
+		 "InitFlow:dspt_snoc/I/0",
+		 "AddrBase:0x81000000", "AddrSize:0x30",
+		 "Opcode:RdWrLockUrg", "Status:ReqRsp", "Length:0x8000", "Urgency:0x0";
+
+	stat,2 = "TracePort:ddr1_p1_req",
+		 "Status:Req", "AddrSize:0x28";
+
+	stat,3 = "TracePort:ddr1_p2_req";
+
+	latency,0 = "TracePort:sysnoc_trans_probe_0", "AddrSize:0x0";
+	latency,1 = "TracePort:sysnoc_trans_probe_1","Mode:latency","AddrBase:0x82000000","AddrSize:0x28","Opcode:RdWr";
+
+	pending,0 = "TracePort:sysnoc_trans_probe_2", "AddrSize:0x3";
+};
+
+&d0_media_noc {
+	status = "okay";
+
+	stat,0 = "TracePort:ddr0_p3_req";
+	stat,1 = "TracePort:ddr1_p3_req";
+};
+
+&d0_realtime_noc {
+	status = "okay";
+
+	stat,0 = "TracePort:ddr0_p4_req";
+	stat,1 = "TracePort:ddr1_p4_req";
+};
+
+&d0_noc_wdt {
+	status = "okay";
+};
+
+&d0_ipc_scpu {
+	status = "okay";
+};
+
+&d0_lpcpu {
+	status = "disabled";
+};
+
+&pcie {
+	/* GPIO12 PCIE PRSNT input */
+	status = "okay";
+};
+
+&d0_npu{
+	status = "okay";
+};
+
+&d0_dsp_subsys {
+	status = "okay";
+};
+
+&d0_dsp0 {
+	status = "okay";
+};
+
+&d0_dsp1 {
+	status = "okay";
+};
+
+&d0_dsp2 {
+	status = "okay";
+};
+
+&d0_dsp3 {
+	status = "okay";
+};
+
+&gpu0 {
+	status = "okay";
+};
+
+&gc820 {
+	status = "okay";
+};
+
+&vdec0 {
+	status = "okay";
+};
+
+&venc0 {
+	status = "okay";
+};
+
+&video_output {
+	status = "okay";
+};
+
+&dc {
+	status = "okay";
+};
+
+&dc_test {
+    status = "disabled";
+};
+
+&virtual_display {
+    status = "disabled";
+};
+
+&dsi_output {
+    status = "okay";
+};
+
+&dsi_controller {
+    status = "okay";
+};
+
+&dsi_panel {
+	status = "okay";
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_gpio82_default &pinctrl_gpio85_default>;
+	backlight0-gpios = <&portc 18 GPIO_ACTIVE_HIGH>;
+	rst-gpios = <&portc 21 GPIO_ACTIVE_HIGH>;
+};
+
+&dw_hdmi {
+	status = "okay";
+	ports {
+		port@2 {
+			reg = <2>;
+			hdmi_in_i2s: endpoint@1 {
+				system-clock-frequency = <12288000>;
+				remote-endpoint = <&d0_i2s0_endpoint>;
+			};
+		};
+	};
+};
+
+&dw_hdmi_hdcp2 {
+    status = "okay";
+};
+
+&d0_i2s0 {
+	status = "okay";
+	d0_i2s0_port: port {
+		d0_i2s0_endpoint: endpoint {
+			remote-endpoint = <&hdmi_in_i2s>;
+			dai-format = "i2s";
+		};
+	};
+};
+
+&d0_i2s1 {
+	status = "okay";
+	d0_i2s1_port: port {
+		d0_i2s1_endpoint: endpoint {
+			remote-endpoint = <&d0_codec0_endpoint>;
+			dai-format = "i2s";
+		};
+	};
+};
+
+&d0_i2s2 {
+	/* connect WIFI module */
+	status = "disabled";
+};
+
+&d0_graphcard0 {
+	status = "okay";
+	dais = <&d0_i2s1_port>;
+};
+
+&d0_graphcard1 {
+	status = "okay";
+	dais = <&d0_i2s0_port>;
+};
+
+&d0_graphcard2 {
+	status = "disabled";
+};
+
+&isp_0 {
+	status = "disabled";
+};
+
+&isp_1 {
+	status = "disabled";
+};
+
+&dewarp {
+	status = "okay";
+};
+
+&mipi_dphy_rx {
+	status = "disabled";
+};
+
+&csi_dma0 {
+	status = "disabled";
+};
+
+&csi_dma1 {
+	status = "disabled";
+};
+
+&csi2_0 {
+	status = "disabled";
+};
+
+&csi2_1 {
+	status = "disabled";
+};
+
+&sdhci_emmc {
+	/* emmc */
+	status = "okay";
+	delay_code = <0x17>;
+	drive-impedance-ohm = <50>;
+	enable-cmd-pullup;
+	enable-data-pullup;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_emmc_led_control_default>;
+};
+
+&sdio0 {
+	/* sd card */
+	status = "okay";
+	delay_code = <0x29>;
+	drive-impedance-ohm = <33>;
+	enable-cmd-pullup;
+	enable-data-pullup;
+	no-sdio;
+	no-mmc;
+};
+
+&sdio1 {
+	/* wifi module */
+	status = "okay";
+	delay_code = <0x29>;
+	drive-impedance-ohm = <33>;
+	enable-cmd-pullup;
+	enable-data-pullup;
+	non-removable;
+	no-sd;
+	no-mmc;
+};
+
+&d0_gmac0 {
+	status = "okay";
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_gpio106_default>;
+	rst-gpios = <&portd 10 GPIO_ACTIVE_LOW>;
+	eswin,rgmiisel = <&pinctrl 0x290 0x3>;
+	eswin,led-cfgs = <0x6100 0xa40 0x420>;
+};
+
+&d0_gmac1 {
+	status = "okay";
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_gpio111_default>;
+	rst-gpios = <&portd 15 GPIO_ACTIVE_LOW>;
+	eswin,rgmiisel = <&pinctrl 0x294 0x3>;
+	eswin,led-cfgs = <0x6100 0xa40 0x420>;
+};
+
+&d0_sata {
+	status = "okay";
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_sata_act_led_default>;
+};
+
+&d0_usbdrd3_0 {
+	status = "okay";
+};
+
+&d0_usbdrd_dwc3_0 {
+	status = "okay";
+	dr_mode = "host";
+	maximum-speed = "super-speed";
+};
+
+&d0_usbdrd3_1 {
+	status = "okay";
+};
+
+&d0_usbdrd_dwc3_1 {
+	status = "okay";
+	dr_mode = "host";
+	maximum-speed = "super-speed";
+	usb-hub {
+		gpio-hog;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_gpio43_default>;
+		gpios = <&portb 11 GPIO_ACTIVE_HIGH>;
+		output-low;
+		line-name = "usb-hub-reset";
+	};
+};
+
+&d0_dmac0 {
+	status = "okay";
+};
+
+&d0_aon_dmac {
+	status = "okay";
+};
+
+&d0_uart0 {
+	/* debug */
+	status = "okay";
+};
+
+&d0_uart1 {
+	/* M.2 KEY E */
+	status = "okay";
+};
+
+&d0_uart2 {
+	/* connect MCU */
+	status = "okay";
+};
+
+&d0_uart3 {
+	/* pin header mux with GPIO 92,93 */
+	status = "disabled";
+};
+
+&d0_uart4 {
+	/* unused */
+	status = "disabled";
+};
+
+&ssi0 {
+	/* pin header mux with GPIO 35,36,37,38,39,40 */
+	status = "disabled";
+};
+
+&ssi1 {
+	/* unused */
+	status = "disabled";
+};
+
+&bootspi {
+	/* spi flash */
+	status = "okay";
+	num-cs = <1>;
+	cs-gpios = <&portd 0 GPIO_ACTIVE_LOW>;
+	spi-flash@0 {
+		compatible = "winbond,w25q128jw",
+					"jedec,spi-nor";
+		reg = <0>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		spi-max-frequency = <4800000>;
+		rx-sample-delay-ns = <10>;
+	};
+};
+
+&d0_mbox0 {
+	status = "okay";
+};
+
+&d0_mbox1 {
+	status = "okay";
+};
+
+&d0_mbox2 {
+	status = "okay";
+};
+
+&d0_mbox3 {
+	status = "okay";
+};
+
+&d0_mbox4 {
+	status = "okay";
+};
+
+&d0_mbox5 {
+	status = "okay";
+};
+
+&d0_mbox6 {
+	status = "okay";
+};
+
+&d0_mbox7 {
+	status = "okay";
+};
+
+&fan_control {
+	status = "okay";
+};
+
+&d0_i2c0 {
+	/* codec es8388 */
+	status = "okay";
+	d0_es8388_0: es8388-0@11 {
+		compatible = "eswin,es8388";
+		reg = <0x11>;
+		#sound-dai-cells = <0>;
+		eswin-plat = <2>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_gpio0_default &pinctrl_gpio28_default>;
+		front-jack-gpios = <&porta 0 GPIO_ACTIVE_HIGH>;
+		back-jack-gpios = <&porta 28 GPIO_ACTIVE_HIGH>;
+		port {
+			d0_codec0_endpoint: endpoint {
+				system-clock-frequency = <12288000>;
+				remote-endpoint = <&d0_i2s1_endpoint>;
+			};
+		};
+	};
+};
+
+&d0_i2c1 {
+	/* pin header mux with GPIO 46,47 */
+	status = "disabled";
+};
+
+&d0_i2c2 {
+	/* mipi dsi touch ctrl con */
+	status = "disabled";
+};
+
+&d0_i2c3 {
+	/* FUSB303B cc logic */
+	status = "okay";
+	fusb303b@21 {
+		compatible = "fcs,fusb303b";
+		status = "okay";
+		reg = <0x21>;
+		eswin,syscfg = <&d0_sys_con 0x3C0 12>;
+
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_gpio5_default>;
+		int-gpios = <&porta 5 GPIO_ACTIVE_HIGH>;
+		connector {
+			compatible = "usb-c-connector";
+			label = "USB-C";
+			data-role = "host";
+		};
+	};
+};
+
+&d0_i2c4 {
+	/* unused */
+	status = "disabled";
+};
+
+&d0_i2c5 {
+	/* PCA9548 */
+	status = "okay";
+};
+
+&d0_i2c6 {
+	/* unused */
+	status = "disabled";
+};
+
+&d0_i2c7 {
+	/* unused */
+	status = "disabled";
+};
+
+&d0_i2c8 {
+	/* unused */
+	status = "disabled";
+};
+
+&d0_i2c9 {
+	/* unused */
+	status = "disabled";
+};
+
+&d0_aon_i2c0 {
+	/* AT24C02C EEPROM */
+	status = "okay";
+	eswin,syscfg = <&d0_sys_con 0x3C0 16>;
+	aon_eeprom@50 {
+		compatible = "atmel,24c02";
+		reg = <0x50>;
+	};
+};
+
+&d0_aon_i2c1 {
+	/* PCA9450 & SiC451 & INA226 & PAC1934 */
+	status = "okay";
+	eswin,syscfg = <&d0_sys_con 0x3C0 15>;
+	iic_hold_time = <0x40>;
+	pac1934:pac1934@10 {
+		compatible = "microchip,pac1934";
+		/*update all register data*/
+		update_time_ms = <1000>;
+		eswin,chan_label = "som vdd", "soc vdd", "cpu vdd", "ddr lpvdd";
+		label = "som_info";
+		/*The update number of times the energy accumulates*/
+		energy_acc_count = <0>;
+		shunt_resistors=<1 1 1 1>;
+		reg = <0x10>;
+	};
+
+	sys_power:ina226@44 {
+		compatible = "ti,ina226";
+		#io-channel-cells = <1>;
+		label = "sys_power";
+		reg = <0x44>;
+		shunt-resistor = <1000>;
+	};
+};
+
+&pwm0 {
+	/* fan */
+	status = "okay";
+};
+
+&pvt0 {
+	status = "okay";
+};
+
+&pvt1 {
+	status = "okay";
+};
+
+&wdt0 {
+	status = "okay";
+};
+
+&wdt1 {
+	status = "okay";
+};
+
+&wdt2 {
+	status = "okay";
+};
+
+&wdt3 {
+	status = "okay";
+};
+
+&die0_rtc {
+	status = "okay";
+};
+
+&timer0 {
+	status = "okay";
+};
+
+&timer1 {
+	status = "okay";
+};
+
+&timer2 {
+	status = "okay";
+};
+
+&timer3 {
+	status = "okay";
+};
+
+&pinctrl {
+	status = "okay";
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_gpio6_default &pinctrl_gpio7_default &pinctrl_gpio8_default &pinctrl_gpio9_default
+			&pinctrl_gpio10_default &pinctrl_gpio17_default &pinctrl_gpio35_default &pinctrl_gpio36_default
+			&pinctrl_gpio37_default &pinctrl_gpio38_default &pinctrl_gpio39_default &pinctrl_gpio40_default
+			&pinctrl_gpio41_default &pinctrl_gpio46_default &pinctrl_gpio52_default
+			&pinctrl_gpio53_default &pinctrl_gpio64_default &pinctrl_gpio65_default &pinctrl_gpio66_default
+			&pinctrl_gpio67_default &pinctrl_gpio70_default &pinctrl_gpio73_default &pinctrl_gpio83_default
+			&pinctrl_gpio86_default &pinctrl_gpio87_default &pinctrl_gpio92_default &pinctrl_gpio93_default>;
+
+    /* pin header default function for GPIO
+       SPI1 (CS0,SCLK,MOSI,MISO,D2,D3): GPIO 35,36,37,38,39,40
+       I2C1 (SCL,SDA): GPIO 46,47
+       UART3(TX,RX): GPIO 92,93
+    */
+};
+
+/*
+GPIO USED ON CarrierBoard:
+	gpio0   : FP Audio Jack Sense(I), active low
+	gpio5   : TYPE C cc logic interrupt(I), active low
+	gpio11  : BT WAKE HOST(I), active low
+	gpio12  : PCIE present(I), active low
+	gpio14  : DSI FPC CON CTRL(J10&J11)
+	gpio15  : Wlan wake host(I), active low
+	gpio28  : RP audio jack sense(I), active low
+	gpio29  : EMMC active led ctrl(O)
+
+	gpio43  : USB3.2 Gen1 hub Resetn(O), active low
+	gpio71  : CSI fpc con ctrl(O)
+	gpio74  : CSI fpc con ctrl(O)
+	gpio77  : CSI fpc con ctrl(O)
+	gpio76  : HOST WAKE BT(O), active low
+	gpio79  : WLAN POWER ON(O), active high
+	gpio80  : CSI fpc con ctrl(O)
+	gpio82  : DSI FPC CON CTRL(J10)
+	gpio85  : DSI FPC CON CTRL(J11)
+	gpio84  : GPIO LED CTRL(O), active high
+
+ GPIO USED ON SOM:
+	gpio18  : HOST WAKE WLAN(O), active low
+	gpio19  : HOST WAKE BT(O), active low
+	gpio20  : WLAN WAKE HOST(I), active low
+	gpio21  : BT WAKE HOST(I), active low
+	gpio106 : gphy0 resern(O), active low
+	gpio111 : gphy1 resern(O), active low
+
+*/
+
+&gpio0 {
+	status = "okay";
+};
diff --git a/arch/riscv/boot/dts/eswin/eic7700-milkv-megrez.dts b/arch/riscv/boot/dts/eswin/eic7700-milkv-megrez.dts
new file mode 100644
index 000000000000..f2a1bf624d0d
--- /dev/null
+++ b/arch/riscv/boot/dts/eswin/eic7700-milkv-megrez.dts
@@ -0,0 +1,987 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree file for Eswin EIC7700 SoC.
+ *
+ * Copyright 2024, Beijing ESWIN Computing Technology Co., Ltd.. All rights reserved.
+ * SPDX-License-Identifier: GPL-2.0
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, version 2.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <https://www.gnu.org/licenses/>.
+ */
+
+/dts-v1/;
+
+#define RTCCLK_FREQ		1000000
+#define LSPCLK_FREQ		200000000
+
+/* If wanna enable ECC capability of DDR, should reserve highest zone of 1/8 all space for it */
+#define MEMORY_SIZE_H		0x4
+#define MEMORY_SIZE_L		0x0
+#define CMA_SIZE		0x20000000
+
+#include "eic7700.dtsi"
+#include "eic7700-pinctrl-common.dtsi"
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/gpio/gpio.h>
+
+/* Clock frequency (in Hz) of the PCB crystal for rtcclk */
+
+/ {
+	#address-cells = <2>;
+	#size-cells = <2>;
+	model = "Milk-V Megrez";
+	compatible = "sifive,hifive-unmatched-a00", "sifive,fu740-c000",
+		     "sifive,fu740", "eswin,eic7700";
+
+	aliases {
+		serial0 = &d0_uart0;
+		ethernet0 = &d0_gmac0;
+		ethernet1 = &d0_gmac1;
+		rtc0 = &die0_rtc;
+		rtc1 = &pcf_rtc;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+		opensbi_domain_config: domain-config {
+			compatible = "opensbi,domain,config";
+			system-suspend-test;
+		};
+	};
+
+	cpus {
+		timebase-frequency = <RTCCLK_FREQ>;
+	};
+
+	memory@80000000 {
+		device_type = "memory";
+		reg = <0x0 0x80000000 MEMORY_SIZE_H MEMORY_SIZE_L>;
+		numa-node-id = <0>;
+	};
+
+	memory@59000000 {
+		device_type = "memory";
+		reg = <0x0 0x59000000 0x0 0x400000>;
+		numa-node-id = <0>;
+	};
+
+	reserved-memory {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		linux,cma {
+			compatible = "shared-dma-pool";
+			reusable;
+			size = <0x0 CMA_SIZE>;
+			alignment = <0x0 0x1000>;
+			alloc-ranges = <0x0 0x80000000 MEMORY_SIZE_H MEMORY_SIZE_L>;
+			linux,cma-default;
+		};
+
+		npu0_reserved: sprammemory@59000000 {
+			no-map;
+			reg = <0x0 0x59000000 0x0 0x400000>;
+		};
+
+		lpcpu0_reserved: lpcpu@a0000000 {
+			no-map;
+			reg = <0x0 0xa0000000 0x0 0x100000>;
+		};
+
+		g2d_4GB_boundary_reserved_4k {
+			no-map;
+			reg = <0x0 0xfffff000 0x0 0x1000>;
+		};
+
+		g2d_8GB_boundary_reserved_4k {
+			no-map;
+			reg = <0x1 0xfffff000 0x0 0x1000>;
+		};
+
+		g2d_12GB_boundary_reserved_4k {
+			no-map;
+			reg = <0x2 0xfffff000 0x0 0x1000>;
+		};
+
+		mmz_nid_0_part_0 {
+			compatible = "eswin-reserve-memory";
+			reg = <0x3 0x0 0x1 0x80000000>;
+			no-map;
+		};
+	};
+
+	leds {
+		compatible = "gpio-leds";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_gpio107_default &pinctrl_gpio108_default &pinctrl_gpio109_default>;
+
+		gpio-107 {
+			gpios = <&portd 11 GPIO_ACTIVE_HIGH>;
+			label = "power";
+			linux,default-trigger = "default-on";
+		};
+
+		gpio-108 {
+			gpios = <&portd 12 GPIO_ACTIVE_LOW>;
+			label = "heartbeat";
+			linux,default-trigger = "heartbeat";
+		};
+
+		gpio-109 {
+			gpios = <&portd 13 GPIO_ACTIVE_HIGH>;
+			label = "gpio-109";
+			linux,default-trigger = "default-off";
+		};
+
+		gpio-110 {
+			gpios = <&portd 14 GPIO_ACTIVE_HIGH>;
+			label = "gpio-109";
+			linux,default-trigger = "default-off";
+		};
+	};
+
+	gpio-keys {
+		compatible = "gpio-keys";
+
+		ok_key {
+			label = "OK";
+			pinctrl-names = "default";
+			pinctrl-0 = <&pinctrl_gpio6_default>;
+			gpios = <&porta 6 GPIO_ACTIVE_LOW>;
+		};
+	};
+};
+
+&d0_clock {
+	status = "okay";
+};
+
+&d0_reset {
+	status = "okay";
+};
+
+&d0_pmu {
+	status = "okay";
+};
+
+&ddr0 {
+	status = "okay";
+};
+
+&ddr1 {
+	status = "okay";
+};
+
+&d0_cfg_noc {
+	status = "okay";
+};
+
+&d0_llc_noc {
+	status = "okay";
+	stat,0 = "TracePort:ddr0_p0_req";
+	stat,1 = "TracePort:ddr1_p0_req";
+	//latency,0 = "TracePort:llcnoc_trans_probe";
+	//pending,0 = "TracePort:llcnoc_trans_probe";
+};
+
+&d0_sys_noc {
+	status = "okay";
+
+	//eswin,DSPT-qos-owner;
+	//eswin,NPU-qos-owner;
+	//eswin,SPISLV_TBU3-qos-owner;
+
+	stat,0 = "TracePort:ddr0_p1_req",
+		 "InitFlow:mcput_snoc_mp/I/0";
+
+	stat,1 = "TracePort:ddr0_p2_req",
+		 "InitFlow:dspt_snoc/I/0",
+		 "AddrBase:0x81000000", "AddrSize:0x30",
+		 "Opcode:RdWrLockUrg", "Status:ReqRsp", "Length:0x8000", "Urgency:0x0";
+
+	stat,2 = "TracePort:ddr1_p1_req",
+		 "Status:Req", "AddrSize:0x28";
+
+	stat,3 = "TracePort:ddr1_p2_req";
+
+	latency,0 = "TracePort:sysnoc_trans_probe_0", "AddrSize:0x0";
+	latency,1 = "TracePort:sysnoc_trans_probe_1","Mode:latency","AddrBase:0x82000000","AddrSize:0x28","Opcode:RdWr";
+	//latency,2 = "TracePort:sysnoc_trans_probe_2";
+
+	//pending,0 = "TracePort:sysnoc_trans_probe_0";
+	//pending,1 = "TracePort:sysnoc_trans_probe_1","Mode:latency","AddrBase:0x82000000","AddrSize:0x0","Opcode:RdWr";
+	pending,0 = "TracePort:sysnoc_trans_probe_2", "AddrSize:0x3";
+};
+
+&d0_media_noc {
+	status = "okay";
+
+	//eswin,GPU-qos-owner;
+	//eswin,TBU2-qos-owner;
+	//eswin,VC-qos-owner;
+
+	stat,0 = "TracePort:ddr0_p3_req";
+	stat,1 = "TracePort:ddr1_p3_req";
+	//latency,0 = "TracePort:mnoc_trans_probe";
+	//pending,0 = "TracePort:mnoc_trans_probe";
+};
+
+&d0_realtime_noc {
+	status = "okay";
+
+	//eswin,TBU0-qos-owner;
+	//eswin,VO-qos-owner;
+
+	stat,0 = "TracePort:ddr0_p4_req";
+	stat,1 = "TracePort:ddr1_p4_req";
+	//latency,0 = "TracePort:rnoc_trans_probe";
+	//pending,0 = "TracePort:rnoc_trans_probe";
+};
+
+&d0_noc_wdt {
+	status = "okay";
+};
+
+&d0_ipc_scpu {
+	status = "okay";
+};
+
+&pcie {
+	status = "okay";
+};
+
+&d0_npu{
+	status = "okay";
+	npu-supply=<&npu_vcc1>;
+	apply_npu_1G_freq;
+};
+
+&d0_dsp_subsys {
+	status = "okay";
+};
+
+&d0_dsp0 {
+	status = "okay";
+};
+
+&d0_dsp1 {
+	status = "okay";
+};
+
+&d0_dsp2 {
+	status = "okay";
+};
+
+&d0_dsp3 {
+	status = "okay";
+};
+
+&gpu0 {
+	status = "okay";
+};
+
+&gc820 {
+	status = "okay";
+};
+
+&vdec0 {
+	status = "okay";
+};
+
+&venc0 {
+	status = "okay";
+};
+
+&video_output {
+	status = "okay";
+};
+
+&dc {
+	status = "okay";
+	dc_out: port {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		dc_out_dsi: endpoint@0 {
+			reg = <0>;
+			remote-endpoint = <&dsi_input>;
+		};
+		dc_out_dpi1: endpoint@1 {
+			reg = <1>;
+			remote-endpoint = <&vd_input>;
+		};
+		dc_out_hdmi: endpoint@2 {
+			reg = <2>;
+			remote-endpoint = <&hdmi_in_dc>;
+		};
+	};
+};
+
+&dc_test {
+	status = "disabled";
+};
+
+&virtual_display {
+	status = "okay";
+	port {
+		vd_input: endpoint {
+			remote-endpoint = <&dc_out_dpi1>;
+		};
+	};
+};
+
+&dsi_output {
+	status = "okay";
+};
+
+&dsi_controller {
+	status = "okay";
+	ports {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		port@0 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0>;
+			dsi_input: endpoint {
+				remote-endpoint = <&dc_out_dsi>;
+			};
+		};
+		port@1 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <1>;
+			mipi_dsi_out: endpoint {
+				remote-endpoint = <&panel_in>;
+			};
+		};
+	};
+	dsi_panel:dsi_panel@0 {
+		compatible = "eswin,generic-panel";
+		reg = <0>;
+		dsi,format = <0>; //RGB888:0, RGB666:1, RGB565:3
+		dsi,lanes = <4>;
+		port {
+			panel_in: endpoint {
+				remote-endpoint = <&mipi_dsi_out>;
+			};
+		};
+	};
+};
+
+&dsi_panel {
+	status = "okay";
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_gpio5_default &pinctrl_gpio111_default>;
+	backlight0-gpios = <&porta 5 GPIO_ACTIVE_HIGH>;
+	rst-gpios = <&portd 15 GPIO_ACTIVE_HIGH>;
+};
+
+&dw_hdmi {
+	status = "okay";
+	ports {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		port@0 {
+			reg = <0>;
+			hdmi_in_dc: endpoint@0 {
+				remote-endpoint = <&dc_out_hdmi>;
+			};
+		};
+		port@2 {
+			reg = <2>;
+			hdmi_in_i2s: endpoint@1 {
+				system-clock-frequency = <12288000>;
+				remote-endpoint = <&d0_i2s0_endpoint>;
+			};
+		};
+	};
+};
+
+&dw_hdmi_hdcp2 {
+    status = "okay";
+};
+
+&d0_i2s0 {
+	status = "okay";
+	d0_i2s0_port: port {
+		d0_i2s0_endpoint: endpoint {
+			remote-endpoint = <&hdmi_in_i2s>;
+			dai-format = "i2s";
+		};
+	};
+};
+
+&d0_i2s1 {
+	status = "okay";
+	d0_i2s1_port: port {
+		d0_i2s1_endpoint: endpoint {
+			remote-endpoint = <&d0_codec0_endpoint>;
+			dai-format = "i2s";
+		};
+	};
+};
+
+&d0_i2s2 {
+	status = "disabled";
+};
+
+&d0_graphcard0 {
+	status = "okay";
+	label = "Analog Audio-0";
+	dais = <&d0_i2s1_port>;
+};
+
+&d0_graphcard1 {
+	status = "okay";
+	label = "HDMI Audio";
+	dais = <&d0_i2s0_port>;
+};
+
+&d0_graphcard2 {
+        status = "disabled";
+};
+
+&isp_0 {
+	status = "okay";
+};
+
+&isp_1 {
+	status = "okay";
+};
+
+&dewarp {
+	status = "okay";
+};
+
+&mipi_dphy_rx {
+	status = "okay";
+};
+
+&csi_dma0 {
+	status = "okay";
+};
+
+&csi_dma1 {
+	status = "disabled";
+};
+
+&csi2_0 {
+	status = "okay";
+};
+
+&csi2_1 {
+	status = "disabled";
+};
+
+&sdhci_emmc {
+	/* emmc */
+	status = "okay";
+	delay_code = <0x17>;
+	drive-impedance-ohm = <50>;
+	enable-cmd-pullup;
+	enable-data-pullup;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_emmc_led_control_default>;
+	no-sdio;
+	no-sd;
+};
+
+&sdio0 {
+	/* sd card */
+	status = "okay";
+	delay_code = <0x3b>;
+	drive-impedance-ohm = <33>;
+	enable-cmd-pullup;
+	enable-data-pullup;
+	no-sdio;
+	no-mmc;
+	disable-wp;
+	broken-cd;
+};
+
+&sdio1 {
+	/* wifi module */
+	status = "okay";
+	delay_code = <0x29>;
+	drive-impedance-ohm = <33>;
+	enable-cmd-pullup;
+	enable-data-pullup;
+	keep-power-in-suspend;
+	non-removable;
+	no-sd;
+	no-mmc;
+};
+
+&d0_gmac0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_gpio94_default>;
+	rst-gpios = <&portc 30 GPIO_ACTIVE_LOW>;
+	eswin,rgmiisel = <&pinctrl 0x290 0x3>;
+	eswin,led-cfgs = <0x6100 0xa40 0x420>;
+	dly-param-1000m = <0x23232323 0x800c8023 0x0c0c0c0c>;
+	dly-param-100m = <0x50505050 0x803f8050 0x3f3f3f3f>;
+	dly-param-10m = <0 0 0>;
+	status = "okay";
+};
+
+&d0_gmac1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_gpio16_default>;
+	rst-gpios = <&porta 16 GPIO_ACTIVE_LOW>;
+	eswin,rgmiisel = <&pinctrl 0x294 0x3>;
+	eswin,led-cfgs = <0x6100 0xa40 0x420>;
+	dly-param-1000m = <0x25252525 0x80268025 0x26262626>;
+	dly-param-100m = <0x48484848 0x80588048 0x58585858>;
+	dly-param-10m = <0 0 0>;
+	status = "okay";
+};
+
+&d0_sata {
+	status = "okay";
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_sata_act_led_default>;
+};
+
+&d0_usbdrd3_0 {
+	status = "okay";
+};
+
+&d0_usbdrd_dwc3_0 {
+	status = "okay";
+	dr_mode = "host";
+	maximum-speed = "super-speed";
+};
+
+&d0_usbdrd3_1 {
+	status = "okay";
+};
+
+&d0_usbdrd_dwc3_1 {
+	status = "okay";
+	dr_mode = "host";
+	maximum-speed = "super-speed";
+};
+
+&d0_dmac0 {
+	status = "okay";
+};
+
+&d0_aon_dmac {
+	status = "okay";
+};
+
+&d0_uart0 {
+	/* debug */
+	status = "okay";
+};
+
+&d0_uart1 {
+	/* BT M.2 KEY-E */
+	status = "okay";
+};
+
+&d0_uart2 {
+	/* RS232 DB9 */
+	status = "okay";
+};
+
+&d0_uart3 {
+	/* unused */
+	status = "disabled";
+};
+
+&d0_uart4 {
+	/* unused */
+	status = "disabled";
+};
+
+&ssi0 {
+	/* spi flash */
+	status = "okay";
+	num-cs = <2>;
+	spi-flash@0 {
+		compatible = "winbond,w25q128fw",
+					"jedec,spi-nor";
+		reg = <0>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		spi-max-frequency = <4800000>;
+		rx-sample-delay-ns = <10>;
+	};
+	spi-flash@1 {
+		compatible = "winbond,w25q128fw",
+					"jedec,spi-nor";
+		reg = <1>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		spi-max-frequency = <4800000>;
+		rx-sample-delay-ns = <10>;
+	};
+};
+
+&ssi1 {
+	/* spi flash */
+	status = "disabled";
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_spi2_default>;
+	num-cs = <2>;
+	spi-flash@0 {
+		compatible = "winbond,w25q128fw",
+					"jedec,spi-nor";
+		reg = <0>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		spi-max-frequency = <4800000>;
+		rx-sample-delay-ns = <10>;
+	};
+	spi-flash@1 {
+		compatible = "winbond,w25q128fw",
+					"jedec,spi-nor";
+		reg = <1>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		spi-max-frequency = <4800000>;
+		rx-sample-delay-ns = <10>;
+	};
+};
+
+&bootspi {
+	/* spi flash */
+	status = "okay";
+	num-cs = <1>;
+	cs-gpios = <&portd 0 GPIO_ACTIVE_LOW>;
+	wp-gpios = <&portd 4 GPIO_ACTIVE_LOW>;
+	spi-flash@0 {
+		compatible = "winbond,w25q128jw",
+					"jedec,spi-nor";
+		reg = <0>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		spi-max-frequency = <4800000>;
+		rx-sample-delay-ns = <10>;
+	};
+};
+
+&d0_mbox0 {
+	status = "okay";
+};
+
+&d0_mbox1 {
+	status = "okay";
+};
+
+&d0_mbox2 {
+	status = "okay";
+};
+
+&d0_mbox3 {
+	status = "okay";
+};
+
+&d0_mbox4 {
+	status = "okay";
+};
+
+&d0_mbox5 {
+	status = "okay";
+};
+
+&d0_mbox6 {
+	status = "okay";
+};
+
+&d0_mbox7 {
+	status = "okay";
+};
+
+&fan_control {
+	status = "okay";
+	eswin,pwm_inverted;
+};
+
+&d0_i2c0 {
+	/* codec es8388 */
+	status = "okay";
+	d0_es8388_0: es8388-0@10 {
+		compatible = "eswin,es8388";
+		reg = <0x10>;
+		#sound-dai-cells = <0>;
+		port {
+			d0_codec0_endpoint: endpoint {
+				system-clock-frequency = <12288000>;
+				remote-endpoint = <&d0_i2s1_endpoint>;
+			};
+		};
+	};
+};
+
+&d0_i2c1 {
+	status = "okay";
+	es5430@f {
+		compatible = "einno,es5340";
+		reg = <0xf>;
+		eswin,regulator_default-microvolt=<1000000>;
+		eswin,regulator_label = "supply vdd1", "npu vdd1", "npu current1", "npu temperature1";
+		label = "npu_vdd";
+		regulators{
+			npu_vcc1:npu_svcc{
+				regulator-name="NPU_SVCC";
+				regulator-min-microvolt=<700000>;
+				regulator-max-microvolt=<1100000>;
+				regulator-min-microamp=<20000000>;
+				regulator-max-microamp=<40000000>;
+				regulator-ov-protection-microvolt=<1100000>;
+				regulator-always-on;
+			};
+		};
+	};
+};
+
+&d0_i2c2 {
+	/* mipi dsi */
+	status = "disabled";
+};
+
+&d0_i2c3 {
+	/* mipi csi0/csi1 */
+	status = "okay";
+};
+
+&d0_i2c4 {
+	/* mipi csi2/csi3 */
+	status = "disabled";
+};
+
+&d0_i2c5 {
+	/* mipi csi4/csi5 */
+	status = "disabled";
+};
+
+&d0_i2c6 {
+	/* unused */
+	status = "disabled";
+};
+
+&d0_i2c7 {
+	/* unused */
+	status = "disabled";
+};
+
+&d0_i2c8 {
+	/* io extended for mipi csi */
+	status = "okay";
+	tca6416_0: gpio@20 {
+		compatible = "ti,tca6416";
+		reg = <0x20>;
+		gpio-controller; /* IRQ not connected */
+		#gpio-cells = <2>;
+		gpio-line-names = "MIPI_CSI0_PWDN", "MIPI_CSI0_RESET", "MIPI_CSI1_FBC", "MIPI_CSI1_ENB",
+				"MIPI_CSI1_RESET", "MIPI_CSI1_PWDN", "FREX_GP0", "",
+				"MIPI_CSI0_ENB", "MIPI_CSI0_FBC", "FREX_GP2", "MIPI_CSI2_FBC",
+				"MIPI_CSI2_ENB", "FREX_GP1", "MIPI_CSI2_RESET", "MIPI_CSI2_PWDN";
+	};
+	tca6416_1: gpio@21 {
+		compatible = "ti,tca6416";
+		reg = <0x21>;
+		gpio-controller;
+		#gpio-cells = <2>;
+		/* IRQ not connected */
+		gpio-line-names = "MIPI_CSI3_PWDN", "MIPI_CSI3_RESET", "MIPI_CSI3_ENB", "MIPI_CSI3_FBC",
+				"MIPI_CSI4_PWDN", "MIPI_CSI4_RESET", "MIPI_CSI4_ENB", "MIPI_CSI4_FBC",
+				"MIPI_CSI5_FBC", "MIPI_CSI5_ENB", "MIPI_CSI5_RESET", "MIPI_CSI5_PWDN",
+				"", "", "", "";
+	};
+};
+
+&d0_i2c9 {
+	/* unused */
+	status = "disabled";
+};
+
+&d0_aon_i2c0 {
+	/* temp sensor & rtc */
+	status = "okay";
+	eswin,syscfg = <&d0_sys_con 0x3C0 16>;
+	pcf_rtc:rtc@51 {
+		compatible = "nxp,pcf8563";
+		reg = <0x51>;
+	};
+
+	rtc_m41t11: m41t11@68 {
+		compatible = "st,m41t11";
+		reg = <0x68>;
+	};
+};
+
+&d0_aon_i2c1 {
+	/* ina226x4 */
+	status = "okay";
+	i2c-sda-hold-time-ns = <0x40>;
+	ina226@45 {
+		compatible = "ti,ina226";
+		#io-channel-cells = <1>;
+		label = "cpu_vdd";
+		reg = <0x45>;
+		shunt-resistor = <1000>;
+	};
+	ina226@44 {
+			compatible = "ti,ina226";
+			#io-channel-cells = <1>;
+			label = "soc_vdd";
+			reg = <0x44>;
+			shunt-resistor = <1000>;
+		};
+	ina226@41 {
+			compatible = "ti,ina226";
+			#io-channel-cells = <1>;
+			label = "lpddr_vdd";
+			reg = <0x41>;
+			shunt-resistor = <1000>;
+		};
+	ina226@48 {
+			compatible = "ti,ina226";
+			#io-channel-cells = <1>;
+			label = "dc_vdd";
+			reg = <0x48>;
+			shunt-resistor = <1000>;
+		};
+};
+
+&pwm0 {
+	/* fan */
+	status = "okay";
+};
+
+&pvt0 {
+	status = "okay";
+};
+
+&pvt1 {
+	status = "okay";
+};
+
+&wdt0 {
+	status = "disabled";
+};
+
+&wdt1 {
+	status = "disabled";
+};
+
+&wdt2 {
+	status = "disabled";
+};
+
+&wdt3 {
+	status = "disabled";
+};
+
+&die0_rtc {
+	status = "okay";
+};
+
+&timer0 {
+	status = "okay";
+};
+
+&timer1 {
+	status = "okay";
+};
+
+&timer2 {
+	status = "okay";
+};
+
+&timer3 {
+	status = "okay";
+};
+
+&pinctrl {
+	status = "okay";
+};
+
+&pinctrl_gpio23_default {
+	conf {
+		groups = "gpio23_group";
+		input-enable = <1>;
+		bias-pull-down = <1>;
+	};
+};
+
+&pinctrl_gpio55_default {
+	conf {
+		groups = "gpio55_group";
+		input-enable = <1>;
+		bias-pull-down = <1>;
+	};
+};
+
+
+/* GPIO Function Description
+
+	gpio0   : pcie prstn(I)
+	gpio5   : led back light power on/off(O)
+	gpio6   : system key(I)
+	gpio10  : dsi touch interrupt(I)
+	gpio11  : head phone plug/unplug detection2(I)
+	gpio12  : tf card power on/off(O)
+	gpio14  : bt wake host(I)
+	gpio15  : wlan wake host(I)
+	gpio16  : gphy1 resetn(O)
+	gpio28  : head phone plug/unplug detection1(I)
+	gpio34  : m.2 power on/off(O)
+	gpio94  : gphy0 resetn(O)
+	gpio106 : touch reset(O)
+	gpio107 : system led0(O)
+	gpio108 : system led1(O)
+	gpio109 : system led2(O)
+	gpio110 : system led3(O)
+	gpio111 : mipi dsi resetn(O)
+*/
+
+&gpio0 {
+	status = "okay";
+};
+&dev_llc_d0{
+	/* apply_npu_1G_freq; */
+	npu-supply=<&npu_vcc1>;
+	apply_npu_high_freq;
+};
+
+&d0_clock {
+	status = "okay";
+	force-1_8ghz;
+};
+
+&d0_cpu_opp_table {
+        opp-1500000000 {
+                opp-hz = /bits/ 64 <CLK_FREQ_1500M>;
+                opp-microvolt = <900000>;
+                clock-latency-ns = <70000>;
+        };
+        opp-1600000000 {
+                opp-hz = /bits/ 64 <CLK_FREQ_1600M>;
+                opp-microvolt = <900000>;
+                clock-latency-ns = <70000>;
+        };
+        opp-1700000000 {
+                opp-hz = /bits/ 64 <CLK_FREQ_1700M>;
+                opp-microvolt = <900000>;
+                clock-latency-ns = <70000>;
+        };
+        opp-1800000000 {
+                opp-hz = /bits/ 64 <CLK_FREQ_1800M>;
+                opp-microvolt = <900000>;
+                clock-latency-ns = <70000>;
+        };
+};
diff --git a/arch/riscv/boot/dts/eswin/eic7700-noc.dtsi b/arch/riscv/boot/dts/eswin/eic7700-noc.dtsi
new file mode 100644
index 000000000000..a4e143548832
--- /dev/null
+++ b/arch/riscv/boot/dts/eswin/eic7700-noc.dtsi
@@ -0,0 +1,2620 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Include file for Die0 NOC monitor of Eswin EIC770x family SoC.
+ *
+ * Copyright 2024, Beijing ESWIN Computing Technology Co., Ltd.. All rights reserved.
+ * SPDX-License-Identifier: GPL-2.0
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, version 2.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <https://www.gnu.org/licenses/>.
+ */
+
+d0_cfg_noc:d0_cfg_noc{
+	compatible = "eswin,eic7700-noc";
+	#address-cells = <2>;
+	#size-cells = <2>;
+	ranges;
+	reg = <0 0x52060000 0 0x4000>;
+
+	interrupts = <446>;
+	interrupt-names = "error";
+	interrupt-parent = <&plic0>;
+	errlogger,idx = <0 1 3 5>;
+
+	sideband_manager@52061000{
+		compatible = "eswin,win2xxx-noc-sideband-manager";
+		reg = <0 0x52061000 0 0x10>;
+		SenseIn0 =
+			<SBM_CLMM 	OFFSET0>,
+			<SBM_CNOC_AON 	OFFSET1>,
+			<SBM_CNOC_DDRT0_CTRL 	OFFSET2>,
+			<SBM_CNOC_DDRT0_PHY 	OFFSET3>,
+			<SBM_CNOC_DDRT1_CTRL 	OFFSET4>,
+			<SBM_CNOC_DDRT1_PHY 	OFFSET5>,
+			<SBM_CNOC_DSPT 	OFFSET6>,
+			<SBM_CNOC_GPU 	OFFSET7>,
+			<SBM_CNOC_HSP 	OFFSET8>,
+			<SBM_CNOC_LSP_APB2 	OFFSET9>,
+			<SBM_CNOC_LSP_APB3	OFFSET10>,
+			<SBM_CNOC_LSP_APB4 	OFFSET11>,
+			<SBM_CNOC_LSP_APB6 	OFFSET12>,
+			<SBM_CNOC_MCPUT_D2D 	OFFSET13>,
+			<SBM_CNOC_NPU 	OFFSET14>,
+			<SBM_CNOC_PCIET_P 	OFFSET15>,
+			<SBM_CNOC_PCIET_X 	OFFSET16>,
+			<SBM_CNOC_TCU 	OFFSET17>,
+			<SBM_CNOC_VC 	OFFSET18>,
+			<SBM_CNOC_VI 	OFFSET19>,
+			<SBM_CNOC_VO 	OFFSET20>;
+		bf-name =
+			"SBM_CLMM",
+			"SBM_CNOC_AON",
+			"SBM_CNOC_DDRT0_CTRL",
+			"SBM_CNOC_DDRT0_PHY ",
+			"SBM_CNOC_DDRT1_CTRL",
+			"SBM_CNOC_DDRT1_PHY",
+			"SBM_CNOC_DSPT",
+			"SBM_CNOC_GPU",
+			"SBM_CNOC_HSP",
+			"SBM_CNOC_LSP_APB2",
+			"SBM_CNOC_LSP_APB3",
+			"SBM_CNOC_LSP_APB4",
+			"SBM_CNOC_LSP_APB6",
+			"SBM_CNOC_MCPUT_D2D",
+			"SBM_CNOC_NPU",
+			"SBM_CNOC_PCIET_P",
+			"SBM_CNOC_PCIET_X",
+			"SBM_CNOC_TCU",
+			"SBM_CNOC_VC",
+			"SBM_CNOC_VI",
+			"SBM_CNOC_VO";
+	};
+	ErrorLogger0 {
+		compatible = "eswin,eic7700,register";
+		offset,length = < 0x14 32 >;
+		description = "Register 0 to log errors";
+		lock {
+			compatible = "eswin,eic7700,bitfield";
+			offset,length = < 0 1>;
+			lut = "Not Locked", "Locked";
+		};
+		OpCode {
+			compatible = "eswin,eic7700,bitfield";
+			offset,length = < 1 4>;
+			lut = "RD: data read with incrementing address",
+				"RDW: data read with wrapping address",
+				"RDL: allocates monitor in the Target with incrementing address",
+				"RDX: exclusive read with incrementing address",
+				"WR: data write with incrementing address",
+				"WRW: data write with wrapping address",
+				"WRC: conditional write if matching monitor in Target is found",
+				"RSV: reserved",
+				"PRE: preamble packet of linked sequence (locked sequence)",
+				"URG: urgency packet used for QoS (status must be REQ)";
+		};
+		ErrCode {
+			compatible = "eswin,eic7700,bitfield";
+			offset,length = < 8 3 >;
+			lut = "SLV (error source: Target): error detected by the Slave without any information or no Error",
+				"DEC (error source: Initiator NIU): decode error",
+				"UNS (error source: Target NIU): unsupported access type",
+				"DISC (error source: Power Disconnect): disconnected Target or NoC domain",
+				"SEC (error source: Initiator NIU or Firewall): security error",
+				"HIDE (error source: Firewall): hidden security error. Will be reported as OK to the initiator",
+				"TMO (error source: Target NIU): time-out",
+				"RSV: reserved";
+
+		};
+		Len1 {
+			compatible = "eswin,eic7700,bitfield";
+			offset,length = < 16 12 >;
+		};
+		Format {
+			compatible = "eswin,eic7700,bitfield";
+			offset,length = < 31 1 >;
+			lut = "NTTP v3.0 (Invalid)", "NTTP v3.5 (Ok)";
+		};
+	};
+
+	ErrorLogger1 {
+		compatible = "eswin,eic7700,register", "eswin,eic7700,noc,filter,routeid";
+		offset,length = < 0x18 32>;
+		description = "Register 1 to log errors";
+		InitFlow {
+			compatible = "eswin,eic7700,bitfield";
+			offset,length = < 15 1 >;  /*bit 15 will aloways be 0, then we will always get "snoc_cnoc/I/0"*/
+			lut =
+				"snoc_cnoc/I/0";
+		};
+
+		TargetFlow {
+			compatible = "eswin,eic7700,bitfield";
+			offset,length = < 10 5 >;
+			lut =
+				"clmm/T/0",
+				"cnoc_aon/T/0",
+				"cnoc_ddrt0_ctrl/T/0",
+				"cnoc_ddrt0_phy/T/0",
+				"cnoc_ddrt1_ctrl/T/0",
+				"cnoc_ddrt1_phy/T/0",
+				"cnoc_dspt/T/0",
+				"cnoc_gpu/T/0",
+				"cnoc_hsp/T/0",
+				"cnoc_lsp_apb2/T/0",
+				"cnoc_lsp_apb3/T/0",
+				"cnoc_lsp_apb4/T/0",
+				"cnoc_lsp_apb6/T/0",
+				"cnoc_mcput_d2d/T/0",
+				"cnoc_npu/T/0",
+				"cnoc_pciet_p/T/0",
+				"cnoc_pciet_x/T/0",
+				"cnoc_service/T/0",
+				"cnoc_tcu/T/0",
+				"cnoc_vc/T/0",
+				"cnoc_vi/T/0",
+				"cnoc_vo/T/0",
+				"RESERVED",
+				"RESERVED",
+				"RESERVED",
+				"RESERVED",
+				"RESERVED",
+				"RESERVED",
+				"RESERVED",
+				"RESERVED",
+				"RESERVED",
+				"RESERVED";
+		};
+
+		TargetSubRange {
+			compatible = "eswin,eic7700,bitfield";
+			offset,length = < 8 2 >;
+		};
+
+		SeqId {
+			compatible = "eswin,eic7700,bitfield";
+			offset,length = < 0 8 >;
+		};
+	};
+
+	ErrorLogger3 {
+		/* This register does not really include a bitfield or its bitfield is 32 bits and it provides an offset address */
+		/* To calculate the absolute address, you must use the initflow:targetflow:subrange from ErrorLogger1 register */
+		/* And use it as an index in the aperture table. Then you must add the value of this register to the value given */
+		/* by the table to get the absolute address. */
+		compatible = "eswin,eic7700,register";
+		offset,length = <0x20 32>;
+		description = "Register 3 to log errors";
+		aperture-link = <1>; /* link to ErrorLogger1 whose information are required to calculate real absolute address */
+		AbsoluteAddress {
+			compatible = "eswin,eic7700,bitfield";
+			offset,length = < 8 8 >;	/* bitfield initflow:targeflow:subrange from aperture-link register */
+			aperture-size= < 46 >;		/* Number of line in the aperture table below */
+			aperture-idx,aperture-base =	/* Aperture_idx is concatenation of initflow:targetflow:subrange bitfield from ErrorLogger1 */
+				/bits/ 64  <0x0 0x0    0x0  0x51600000>,
+				/bits/ 64  <0x0 0x0    0x1  0x71600000>,
+				/bits/ 64  <0x0 0x1    0x0  0x51800000>,
+				/bits/ 64  <0x0 0x1    0x1  0x71800000>,
+				/bits/ 64  <0x0 0x1    0x2  0x0       >,
+				/bits/ 64  <0x0 0x1    0x3  0x0       >,
+				/bits/ 64  <0x0 0x2    0x0  0x52300000>,
+				/bits/ 64  <0x0 0x2    0x1  0x72300000>,
+				/bits/ 64  <0x0 0x3    0x0  0x53000000>,
+				/bits/ 64  <0x0 0x3    0x1  0x73000000>,
+				/bits/ 64  <0x0 0x4    0x0  0x52380000>,
+				/bits/ 64  <0x0 0x4    0x1  0x72380000>,
+				/bits/ 64  <0x0 0x5    0x0  0x53800000>,
+				/bits/ 64  <0x0 0x5    0x1  0x73800000>,
+				/bits/ 64  <0x0 0x6    0x0  0x52200000>,
+				/bits/ 64  <0x0 0x6    0x1  0x72200000>,
+				/bits/ 64  <0x0 0x7    0x0  0x51400000>,
+				/bits/ 64  <0x0 0x7    0x1  0x71400000>,
+				/bits/ 64  <0x0 0x8    0x0  0x50400000>,
+				/bits/ 64  <0x0 0x8    0x1  0x70400000>,
+				/bits/ 64  <0x0 0x9    0x0  0x50800000>,
+				/bits/ 64  <0x0 0x9    0x1  0x70800000>,
+				/bits/ 64  <0x0 0xa    0x0  0x50900000>,
+				/bits/ 64  <0x0 0xa    0x1  0x70900000>,
+				/bits/ 64  <0x0 0xb    0x0  0x50a00000>,
+				/bits/ 64  <0x0 0xb    0x1  0x70a00000>,
+				/bits/ 64  <0x0 0xc    0x0  0x50b00000>,
+				/bits/ 64  <0x0 0xc    0x1  0x70b00000>,
+				/bits/ 64  <0x0 0xd    0x0  0x52100000>,
+				/bits/ 64  <0x0 0xd    0x1  0x72100000>,
+				/bits/ 64  <0x0 0xe    0x0  0x51c00000>,
+				/bits/ 64  <0x0 0xe    0x1  0x71c00000>,
+				/bits/ 64  <0x0 0xf    0x0  0x50000000>,
+				/bits/ 64  <0x0 0xf    0x1  0x70000000>,
+				/bits/ 64  <0x0 0x10   0x0  0x54000000>,
+				/bits/ 64  <0x0 0x10   0x1  0x74000000>,
+				/bits/ 64  <0x0 0x11   0x0  0x52060000>,
+				/bits/ 64  <0x0 0x11   0x1  0x72060000>,
+				/bits/ 64  <0x0 0x12   0x0  0x50c00000>,
+				/bits/ 64  <0x0 0x12   0x1  0x70c00000>,
+				/bits/ 64  <0x0 0x13   0x0  0x50100000>,
+				/bits/ 64  <0x0 0x13   0x1  0x70100000>,
+				/bits/ 64  <0x0 0x14   0x0  0x51000000>,
+				/bits/ 64  <0x0 0x14   0x1  0x71000000>,
+				/bits/ 64  <0x0 0x15   0x0  0x50200000>,
+				/bits/ 64  <0x0 0x15   0x1  0x70200000>;
+		};
+	};
+
+	ErrorLogger5 {
+		compatible = "eswin,eic7700,register";
+		offset,length = < 0x28 32>;
+		description = "Register 5 to log errors";
+
+		User_flag {
+			compatible = "eswin,eic7700,bitfield";
+			offset,length = < 0x0 7 >;
+			lut =
+				"Cache_0",
+				"Cache_1",
+				"Cache_2",
+				"Cache_3",
+				"Prot_0",
+				"Prot_1",
+				"Prot_2";
+		};
+	};
+};
+
+d0_llc_noc:d0_llc_noc@52081400 {
+	compatible = "eswin,eic7700-noc";
+	#address-cells = <2>;
+	#size-cells = <2>;
+	ranges;
+	reg = <0 0x52081400 0 0x4000>;
+	interrupts = <441>;
+	interrupt-names = "error";
+	interrupt-parent = <&plic0>;
+	errlogger,idx = <0 1 3 4 5>;
+	sideband_manager@52082000 {
+		compatible = "eswin,win2xxx-noc-sideband-manager";
+		reg = <0 0x52082000 0 0x10>;
+		SenseIn0 =
+			<SBM_LNOC_NPU_LLC0 	OFFSET0>,
+			<SBM_LNOC_NPU_LLC1 	OFFSET1>,
+			<SBM_LNOC_DDRT0_P0 	OFFSET2>,
+			<SBM_LNOC_DDRT1_P0 	OFFSET3>;
+		bf-name =
+			"SBM_LNOC_NPU_LLC0",
+			"SBM_LNOC_NPU_LLC1",
+			"SBM_LNOC_DDRT0_P0",
+			"SBM_LNOC_DDRT1_P0";
+	};
+
+	llcnoc_packet_ddr0_p0_req_probe@52080000 {
+		compatible = "eswin,win2xxx-noc-packet-probe";
+		reg = <0 0x52080000 0 0x4000>;
+		clocks = <&d0_clock EIC7700_CLK_DDRT0_P0_ACLK>;
+		clock-names = "clk";
+		interrupts = <445>;
+		interrupt-names = "stat";
+		interrupt-parent = <&plic0>;
+		filter,nr = <1>;
+		counter,nr = <2>;
+		portsel = "ddr0_p0_req";
+	};
+	llcnoc_packet_ddr1_p0_req_probe@52080800 {
+		compatible = "eswin,win2xxx-noc-packet-probe";
+		reg = <0 0x52080800 0 0x4000>;
+		clocks =<&d0_clock EIC7700_CLK_DDRT1_P0_ACLK>;
+		clock-names = "clk";
+		interrupts = <443>;
+		interrupt-names = "stat";
+		interrupt-parent = <&plic0>;
+		filter,nr = <1>;
+		counter,nr = <2>;
+		portsel = "ddr1_p0_req";
+	};
+	llcnoc_trans_probe@52081000 {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+		compatible = "eswin,win2xxx-noc-trans-probe";
+		reg = <0 0x52081000 0 0x4000>;
+		clocks =<&d0_clock EIC7700_CLK_NOC_NSP_CLK>;
+		clock-names = "clk";
+		interrupts = <441>;
+		interrupt-names = "stat";
+		interrupt-parent = <&plic0>;
+		filter,nr = <2>;
+		counter,nr = <8>;
+		profiler,nr = <1>;
+		portsel = "npu_llc0", "npu_llc1";
+		llcnoc_trans_npu_llc0_filter@52081480 {
+			status = "disabled";
+			compatible = "eswin,win2xxx-noc-trans-filter";
+			reg = <0 0x52081480 0 0x80>;
+		};
+		llcnoc_trans_npu_llc1_filter@52081500 {
+			status = "disabled";
+			compatible = "eswin,win2xxx-noc-trans-filter";
+			reg = <0 0x52081500 0 0x80>;
+		};
+		llcnoc_trans_profiler@52081580 {
+			compatible = "eswin,win2xxx-noc-trans-profiler";
+			reg = <0 0x52081580 0 0x80>;
+		};
+	};
+	ErrorLogger0 {
+		compatible = "eswin,eic7700,register";
+		offset,length = < 0x14 32 >;
+		description = "Register 0 to log errors";
+		lock {
+			compatible = "eswin,eic7700,bitfield";
+			offset,length = < 0 1 >;
+			lut = "Not Locked", "Locked";
+		};
+		OpCode {
+			compatible = "eswin,eic7700,bitfield";
+			offset,length = < 1 4 >;
+			lut = "RD: data read with incrementing address",
+				"RDW: data read with wrapping address",
+				"RDL: allocates monitor in the Target with incrementing address",
+				"RDX: exclusive read with incrementing address",
+				"WR: data write with incrementing address",
+				"WRW: data write with wrapping address",
+				"WRC: conditional write if matching monitor in Target is found",
+				"RSV: reserved",
+				"PRE: preamble packet of linked sequence (locked sequence)",
+				"URG: urgency packet used for QoS (status must be REQ)";
+		};
+		ErrCode {
+			compatible = "eswin,eic7700,bitfield";
+			offset,length = < 8 3 >;
+			lut = "SLV (error source: Target): error detected by the Slave without any information or no Error",
+				"DEC (error source: Initiator NIU): decode error",
+				"UNS (error source: Target NIU): unsupported access type",
+				"DISC (error source: Power Disconnect): disconnected Target or NoC domain",
+				"SEC (error source: Initiator NIU or Firewall): security error",
+				"HIDE (error source: Firewall): hidden security error. Will be reported as OK to the initiator",
+				"TMO (error source: Target NIU): time-out",
+				"RSV: reserved";
+
+		};
+		Len1 {
+			compatible = "eswin,eic7700,bitfield";
+			offset,length = < 16 12 >;
+		};
+		Format {
+			compatible = "eswin,eic7700,bitfield";
+			offset,length = < 31 1 >;
+			lut = "NTTP v3.0 (Invalid)", "NTTP v3.5 (Ok)";
+		};
+	};
+
+	ErrorLogger1 {
+		compatible = "eswin,eic7700,register", "eswin,eic7700,noc,filter,routeid";
+		offset,length = < 0x18 32>;
+		description = "Register 1 to log errors";
+		InitFlow {
+			compatible = "eswin,eic7700,bitfield";
+			offset,length = < 14 2 >;
+			lut =
+				"npu_lnoc_llc0/I/0",
+				"npu_lnoc_llc1/I/0",
+				"snoc_lnoc/I/0",
+				"RESERVED";
+		};
+
+		TargetFlow {
+			compatible = "eswin,eic7700,bitfield";
+			offset,length = < 12 2 >;
+			lut =
+				"lnoc_ddrt0_p0/T/0",
+				"lnoc_ddrt1_p0/T/0",
+				"lnoc_service/T/0",
+				"RESERVED";
+		};
+
+		TargetSubRange {
+			compatible = "eswin,eic7700,bitfield";
+			offset,length = < 8 4 >;
+		};
+
+		SeqId {
+			compatible = "eswin,eic7700,bitfield";
+			offset,length = < 0 8 >;
+		};
+	};
+
+	ErrorLogger3 {
+		/* This register does not really include a bitfield or its bitfield is 32 bits and it provides an offset address */
+		/* To calculate the absolute address, you must use the initflow:targetflow:subrange from ErrorLogger1 register */
+		/* And use it as an index in the aperture table. Then you must add the value of this register to the value given */
+		/* by the table to get the absolute address. */
+		compatible = "eswin,eic7700,register";
+		offset,length = <0x20 32>;
+		description = "Register 3 to log errors";
+		aperture-link = <1>; /* link to ErrorLogger whose information are required to calculate real absolute address */
+		msb-link = <4>; /*indicate which ErrorLogger contains the msb addrs, -1 means no*/
+		AbsoluteAddress {
+			compatible = "eswin,eic7700,bitfield";
+			offset,length = < 8 8 >;		/* bitfield initflow:targeflow:subrange from aperture-link register */
+			aperture-size= < 53 >;		/* Number of line in the aperture table below */
+			aperture-idx,aperture-base =		/* Aperture_idx is concatenation of initflow:targetflow:subrange bitfield from ErrorLogger1 */
+				/bits/ 64  <0x0	0x0	0x0	0x80000000      >,
+				/bits/ 64  <0x0	0x0	0x1	0x100000000     >,
+				/bits/ 64  <0x0	0x0	0x2	0x200000000     >,
+				/bits/ 64  <0x0	0x0	0x3	0x400000000     >,
+				/bits/ 64  <0x0	0x0	0x4	0x800000000     >,
+				/bits/ 64  <0x0	0x0	0x5	0x2000000000    >,
+				/bits/ 64  <0x0	0x0	0x6	0xc000000000    >,
+				/bits/ 64  <0x0	0x0	0x7	0xe000000000    >,
+				/bits/ 64  <0x0	0x0	0x8	0x4000000000    >,
+				/bits/ 64  <0x0	0x0	0x9	0x4000000100    >,
+				/bits/ 64  <0x0	0x0	0xa	0x10000000000   >,
+				/bits/ 64  <0x0	0x0	0xb	0x10000000100   >,
+				/bits/ 64  <0x0	0x0	0xc	0x0             >,
+				/bits/ 64  <0x0	0x1	0x0	0x80000080      >,
+				/bits/ 64  <0x0	0x1	0x1	0x100000080     >,
+				/bits/ 64  <0x0	0x1	0x2	0x200000080     >,
+				/bits/ 64  <0x0	0x1	0x3	0x400000080     >,
+				/bits/ 64  <0x0	0x1	0x4	0x800000080     >,
+				/bits/ 64  <0x0	0x1	0x5	0x2000000080    >,
+				/bits/ 64  <0x0	0x1	0x6	0xc000000080    >,
+				/bits/ 64  <0x0	0x1	0x7	0xe000000080    >,
+				/bits/ 64  <0x0	0x1	0x8	0x4000000080    >,
+				/bits/ 64  <0x0	0x1	0x9	0x4000000180    >,
+				/bits/ 64  <0x0	0x1	0xa	0x10000000080   >,
+				/bits/ 64  <0x0	0x1	0xb	0x10000000180   >,
+				/bits/ 64  <0x1	0x0	0x0	0x80000000      >,
+				/bits/ 64  <0x1	0x0	0x1	0x100000000     >,
+				/bits/ 64  <0x1	0x0	0x2	0x200000000     >,
+				/bits/ 64  <0x1	0x0	0x3	0x400000000     >,
+				/bits/ 64  <0x1	0x0	0x4	0x800000000     >,
+				/bits/ 64  <0x1	0x0	0x5	0x2000000000    >,
+				/bits/ 64  <0x1	0x0	0x6	0xc000000000    >,
+				/bits/ 64  <0x1	0x0	0x7	0xe000000000    >,
+				/bits/ 64  <0x1	0x0	0x8	0x4000000000    >,
+				/bits/ 64  <0x1	0x0	0x9	0x4000000100    >,
+				/bits/ 64  <0x1	0x0	0xa	0x10000000000   >,
+				/bits/ 64  <0x1	0x0	0xb	0x10000000100   >,
+				/bits/ 64  <0x1	0x0	0xc	0x0             >,
+				/bits/ 64  <0x1	0x1	0x0	0x80000080      >,
+				/bits/ 64  <0x1	0x1	0x1	0x100000080     >,
+				/bits/ 64  <0x1	0x1	0x2	0x200000080     >,
+				/bits/ 64  <0x1	0x1	0x3	0x400000080     >,
+				/bits/ 64  <0x1	0x1	0x4	0x800000080     >,
+				/bits/ 64  <0x1	0x1	0x5	0x2000000080    >,
+				/bits/ 64  <0x1	0x1	0x6	0xc000000080    >,
+				/bits/ 64  <0x1	0x1	0x7	0xe000000080    >,
+				/bits/ 64  <0x1	0x1	0x8	0x4000000080    >,
+				/bits/ 64  <0x1	0x1	0x9	0x4000000180    >,
+				/bits/ 64  <0x1	0x1	0xa	0x10000000080   >,
+				/bits/ 64  <0x1	0x1	0xb	0x10000000180   >,
+				/bits/ 64  <0x2	0x2	0x0	0x52080000      >,
+				/bits/ 64  <0x2	0x2	0x1	0x72080000      >,
+				/bits/ 64  <0x2	0x2	0x2	0x0             >;
+		};
+	};
+
+	ErrorLogger4 {
+		compatible = "eswin,eic7700,register";
+		offset,length = < 0x24 32>;
+		description = "Register 4 to log errors";
+		addr_msb {
+			compatible = "eswin,eic7700,bitfield";
+			description = "Stores NTTP packet header field Addr (MSBs) of the logged error";
+			offset,length = < 0 9 >;
+		};
+	};
+
+	ErrorLogger5 {
+		compatible = "eswin,eic7700,register";
+		offset,length = < 0x28 32 >;
+		description = "Register 5 to log errors";
+
+		User_flag {
+			compatible = "eswin,eic7700,bitfield";
+			offset,length = < 0x0 16 >;
+			lut =
+				"Cache_0",
+				"Cache_1",
+				"Cache_2",
+				"Cache_3",
+				"Prot_0",
+				"Prot_1",
+				"Prot_2",
+				"Qos_0",
+				"Qos_1",
+				"Qos_2",
+				"Qos_3",
+				"User_0",
+				"User_1",
+				"User_2",
+				"User_3",
+				"User_4";
+		};
+	};
+};
+
+d0_sys_noc:d0_sys_noc@52002C00 {
+	compatible = "eswin,eic7700-noc";
+	#address-cells = <2>;
+	#size-cells = <2>;
+	ranges;
+	reg = <0 0x52002C00 0 0x4000>;
+	interrupts = <431>;
+	interrupt-names = "error";
+	interrupt-parent = <&plic0>;
+	errlogger,idx = <0 1 3 4 5>;
+
+	eswin,qos-configs = "DSPT", "NPU", "SPISLV_TBU3";
+	eswin,DSPT-qos-base = <0x52002C80>;
+	eswin,DSPT-qos-settings = <
+		0x8 0x4        /* prio */
+		0xC 0x2        /* mode 0:fixed 1:limiter 2:bypass 3:regulator*/
+		/* a number of (1/256)th of Bytes/cycle.
+		   Ex:zebu zdfi design feature, dsp AXI Clk=1040MHz, BW=12.1875MB/s, register value = (9.375/1040)*256 = 0x03
+		*/
+		0x10 0x03    /* bandwidth. 12.1875MB/s */
+		/*
+		   Saturation(B) = ((Requried Bandwidth)*(Windows Time of Bandwidth Calculation))/16
+		   Ex:16 byte saturation for BW=12.1875MB/s means 1.313us window time.
+		   The desired value is number of saturation bytes divided by 16(ex,1 for 16byte B)
+		*/
+		0x14 0x1     /* saturation, 1.313us*/
+		0x18 0x1>;   /* QoSEn */
+
+	eswin,NPU-qos-base = <0x52002D00>;
+	eswin,NPU-qos-settings = <
+		0x8 0x4      /* prio */
+		0xC 0x2      /* mode */
+		0x10 0x18    /* bandwidth */
+		0x14 0x10    /* saturation */
+		0x18 0x1>;   /* QoSEn */
+
+	eswin,SPISLV_TBU3-qos-base = <0x52002D80>;
+	eswin,SPISLV_TBU3-qos-settings = <
+		0x8 0x4      /* prio */
+		0xC 0x2      /* mode */
+		0x10 0x18    /* bandwidth */
+		0x14 0x10    /* saturation */
+		0x18 0x1>;   /* QoSEn */
+	sideband_manager@52004000 {
+		compatible = "eswin,win2xxx-noc-sideband-manager";
+		reg = <0 0x52004000 0 0x10>;
+		SenseIn0 =
+			<SBM_AON_SNOC_SP0 	OFFSET0>,
+			<SBM_DSPT_SNOC 		OFFSET1>,
+			<SBM_JTAG_SNOC 		OFFSET2>,
+			<SBM_MCPUT_SNOC_D2D 	OFFSET3>,
+			<SBM_MCPUT_SNOC_MP 	OFFSET4>,
+			<SBM_MCPUT_SNOC_SP0 	OFFSET5>,
+			<SBM_MCPUT_SNOC_SP1 	OFFSET6>,
+			<SBM_NPU_SNOC_SP0 	OFFSET7>,
+			<SBM_NPU_SNOC_SP1 	OFFSET8>,
+			<SBM_PCIET_SNOC_P 	OFFSET9>,
+			<SBM_SPISLV_PCIET_SNOC	OFFSET10>,
+			<SBM_TBU4_SNOC 		OFFSET11>,
+			<SBM_TCU_SNOC 		OFFSET12>,
+			<SBM_SNOC_AON 		OFFSET13>,
+			<SBM_SNOC_DDR0_P1 	OFFSET14>,
+			<SBM_SNOC_DDR0_P2 	OFFSET15>,
+			<SBM_SNOC_DDR1_P1 	OFFSET16>,
+			<SBM_SNOC_DDR1_P2 	OFFSET17>,
+			<SBM_SNOC_DSPT 		OFFSET18>,
+			<SBM_SNOC_MCPUT_D2D 	OFFSET19>,
+			<SBM_SNOC_NPU 		OFFSET20>,
+			<SBM_SNOC_PCIET 	OFFSET21>;
+		bf-name =
+			"SBM_AON_SNOC_SP0",
+			"SBM_DSPT_SNOC",
+			"SBM_JTAG_SNOC",
+			"SBM_MCPUT_SNOC_D2D ",
+			"SBM_MCPUT_SNOC_MP",
+			"SBM_MCPUT_SNOC_SP0",
+			"SBM_MCPUT_SNOC_SP1",
+			"SBM_NPU_SNOC_SP0",
+			"SBM_NPU_SNOC_SP1",
+			"SBM_PCIET_SNOC_P",
+			"SBM_SPISLV_PCIET_SNOC",
+			"SBM_TBU4_SNOC",
+			"SBM_TCU_SNOC",
+			"SBM_SNOC_AON",
+			"SBM_SNOC_DDR0_P1",
+			"SBM_SNOC_DDR0_P2",
+			"SBM_SNOC_DDR1_P1",
+			"SBM_SNOC_DDR1_P2",
+			"SBM_SNOC_DSPT",
+			"SBM_SNOC_MCPUT_D2D",
+			"SBM_SNOC_NPU",
+			"SBM_SNOC_PCIET";
+	};
+	sysnoc_packet_ddr0_p1_req_probe@52000000 {
+		compatible = "eswin,win2xxx-noc-packet-probe";
+		reg = <0 0x52000000 0 0x4000>;
+		clocks =<&d0_clock EIC7700_CLK_DDRT0_P1_ACLK>;
+		clock-names = "clk";
+		interrupts = <439>;
+		interrupt-names = "stat";
+		interrupt-parent = <&plic0>;
+		filter,nr = <1>;
+		counter,nr = <2>;
+		portsel = "ddr0_p1_req";
+	};
+	sysnoc_packet_ddr0_p2_req_probe@52000800 {
+		compatible = "eswin,win2xxx-noc-packet-probe";
+		reg = <0 0x52000800 0 0x4000>;
+		clocks =<&d0_clock EIC7700_CLK_DDRT0_P2_ACLK>;
+		clock-names = "clk";
+		interrupts = <437>;
+		interrupt-names = "stat";
+		interrupt-parent = <&plic0>;
+		filter,nr = <1>;
+		counter,nr = <2>;
+		portsel = "ddr0_p2_req";
+	};
+	sysnoc_packet_ddr1_p1_req_probe@52001000 {
+		compatible = "eswin,win2xxx-noc-packet-probe";
+		reg = <0 0x52001000 0 0x4000>;
+		clocks =<&d0_clock EIC7700_CLK_DDRT1_P1_ACLK>;
+		clock-names = "clk";
+		interrupts = <435>;
+		interrupt-names = "stat";
+		interrupt-parent = <&plic0>;
+		filter,nr = <1>;
+		counter,nr = <2>;
+		portsel = "ddr1_p1_req";
+	};
+	sysnoc_packet_ddr1_p2_req_probe@52001800 {
+		compatible = "eswin,win2xxx-noc-packet-probe";
+		reg = <0 0x52001800 0 0x4000>;
+		clocks =<&d0_clock EIC7700_CLK_DDRT1_P2_ACLK>;
+		clock-names = "clk";
+		interrupts = <433>;
+		interrupt-names = "stat";
+		interrupt-parent = <&plic0>;
+		filter,nr = <1>;
+		counter,nr = <2>;
+		portsel = "ddr1_p2_req";
+	};
+	sysnoc_trans_probe_0@52002000 {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+		compatible = "eswin,win2xxx-noc-trans-probe";
+		reg = <0 0x52002000 0 0x4000>;
+		clocks =<&d0_clock EIC7700_CLK_NOC_NSP_CLK>;
+		clock-names = "clk";
+		interrupts = <430>;
+		interrupt-names = "stat";
+		interrupt-parent = <&plic0>;
+		filter,nr = <2>;
+		counter,nr = <8>;
+		profiler,nr = <1>;
+		portsel = "dspt_snoc", "npu_sp1";
+		sysnoc_trans_dspt_filter@52002E00 {
+			status = "disabled";
+			compatible = "eswin,win2xxx-noc-trans-filter";
+			reg = <0 0x52002E00 0 0x80>;
+		};
+		sysnoc_trans_npu_sp1_filter@52002F80 {
+			status = "disabled";
+			compatible = "eswin,win2xxx-noc-trans-filter";
+			reg = <0 0x52002F80 0 0x80>;
+		};
+		sysnoc_trans_profiler@52003180 {
+			compatible = "eswin,win2xxx-noc-trans-profiler";
+			reg = <0 0x52003180 0 0x80>;
+		};
+	};
+	sysnoc_trans_probe_1@52002400 {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+		compatible = "eswin,win2xxx-noc-trans-probe";
+		reg = <0 0x52002400 0 0x4000>;
+		clocks =<&d0_clock EIC7700_CLK_NOC_NSP_CLK>;
+		clock-names = "clk";
+		interrupts = <429>;
+		interrupt-names = "stat";
+		interrupt-parent = <&plic0>;
+		filter,nr = <3>;
+		counter,nr = <12>;
+		profiler,nr = <1>;
+		portsel = "mcput_mp", "mcput_sp1", "tcu";
+		sysnoc_trans_mcput_mp_filter@52002E80 {
+			status = "okay";
+			compatible = "eswin,win2xxx-noc-trans-filter";
+			reg = <0 0x52002E80 0 0x80>;
+		};
+		sysnoc_trans_mcput_sp1_filter@52002F00 {
+			status = "okay";
+			compatible = "eswin,win2xxx-noc-trans-filter";
+			reg = <0 0x52002F00 0 0x80>;
+		};
+		sysnoc_trans_tcu_filter@52003100 {
+			status = "okay";
+			compatible = "eswin,win2xxx-noc-trans-filter";
+			reg = <0 0x52003100 0 0x80>;
+		};
+		sysnoc_trans_profiler@52003200 {
+			compatible = "eswin,win2xxx-noc-trans-profiler";
+			reg = <0 0x52003200 0 0x80>;
+		};
+	};
+	sysnoc_trans_probe_2@52002800 {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+		compatible = "eswin,win2xxx-noc-trans-probe";
+		reg = <0 0x52002800 0 0x4000>;
+		clocks =<&d0_clock EIC7700_CLK_NOC_NSP_CLK>;
+		clock-names = "clk";
+		interrupts = <428>;
+		interrupt-names = "stat";
+		interrupt-parent = <&plic0>;
+		filter,nr = <2>;
+		counter,nr = <8>;
+		profiler,nr = <1>;
+		portsel = "spislv_tbu3", "tbu4_snoc";
+		sysnoc_trans_spislv_tbu3_filter@52003000 {	/*pcie subsys*/
+			status = "disabled";
+			compatible = "eswin,win2xxx-noc-trans-filter";
+			reg = <0 0x52003000 0 0x80>;
+		};
+		sysnoc_trans_tbu4_filter@52003080 {	/*aon subsys*/
+			status = "disabled";
+			compatible = "eswin,win2xxx-noc-trans-filter";
+			reg = <0 0x52003080 0 0x80>;
+		};
+		sysnoc_trans_profiler@52003280 {
+			compatible = "eswin,win2xxx-noc-trans-profiler";
+			reg = <0 0x52003280 0 0x80>;
+		};
+	};
+	ErrorLogger0 {
+		compatible = "eswin,eic7700,register";
+		offset,length = < 0x14 32 >;
+		description = "Register 0 to log errors";
+		lock {
+			compatible = "eswin,eic7700,bitfield";
+			offset,length = < 0 1>;
+			lut = "Not Locked", "Locked";
+		};
+		OpCode {
+			compatible = "eswin,eic7700,bitfield";
+			offset,length = < 1 4>;
+			lut = "RD: data read with incrementing address",
+				"RDW: data read with wrapping address",
+				"RDL: allocates monitor in the Target with incrementing address",
+				"RDX: exclusive read with incrementing address",
+				"WR: data write with incrementing address",
+				"WRW: data write with wrapping address",
+				"WRC: conditional write if matching monitor in Target is found",
+				"RSV: reserved",
+				"PRE: preamble packet of linked sequence (locked sequence)",
+				"URG: urgency packet used for QoS (status must be REQ)";
+		};
+		ErrCode {
+			compatible = "eswin,eic7700,bitfield";
+			offset,length = < 8 3 >;
+			lut = "SLV (error source: Target): error detected by the Slave without any information or no Error",
+				"DEC (error source: Initiator NIU): decode error",
+				"UNS (error source: Target NIU): unsupported access type",
+				"DISC (error source: Power Disconnect): disconnected Target or NoC domain",
+				"SEC (error source: Initiator NIU or Firewall): security error",
+				"HIDE (error source: Firewall): hidden security error. Will be reported as OK to the initiator",
+				"TMO (error source: Target NIU): time-out",
+				"RSV: reserved";
+
+		};
+		Len1 {
+			compatible = "eswin,eic7700,bitfield";
+			offset,length = < 16 12 >;
+		};
+		Format {
+			compatible = "eswin,eic7700,bitfield";
+			offset,length = < 31 1 >;
+			lut = "NTTP v3.0 (Invalid)", "NTTP v3.5 (Ok)";
+		};
+	};
+
+	ErrorLogger1 {
+		compatible = "eswin,eic7700,register", "eswin,eic7700,noc,filter,routeid";
+		offset,length = < 0x18 32>;
+		description = "Register 1 to log errors";
+		InitFlow {
+			compatible = "eswin,eic7700,bitfield";
+			offset,length = < 19 4 >;
+			lut =
+				"aon_snoc_sp0/I/0",
+				"dspt_snoc/I/0",
+				"jtag_snoc/I/0",
+				"mcput_snoc_d2d/I/0",
+				"mcput_snoc_mp/I/0",
+				"mcput_snoc_sp0/I/0",
+				"mcput_snoc_sp1/I/0",
+				"mnoc_snoc/I/0",
+				"npu_snoc_sp0/I/0",
+				"npu_snoc_sp1/I/0",
+				"pciet_snoc_p/I/0",
+				"rnoc_snoc/I/0",
+				"spislv_tbu3_snoc/I/0",
+				"tbu4_snoc/I/0",
+				"tcu_snoc/I/0",
+				"RESERVED0";
+		};
+
+		TargetFlow {
+			compatible = "eswin,eic7700,bitfield";
+			offset,length = < 15 4 >;
+			lut =
+				"snoc_aon/T/0",
+				"snoc_cnoc/T/0",
+				"snoc_ddrt0_p1/T/0",
+				"snoc_ddrt0_p2/T/0",
+				"snoc_ddrt1_p1/T/0",
+				"snoc_ddrt1_p2/T/0",
+				"snoc_dspt/T/0",
+				"snoc_lnoc/T/0",
+				"snoc_mcput_d2d/T/0",
+				"snoc_mnoc/T/0",
+				"snoc_npu/T/0",
+				"snoc_pciet/T/0",
+				"snoc_rnoc/T/0",
+				"snoc_service/T/0",
+				"RESERVED1",
+				"RESERVED2";
+		};
+
+		TargetSubRange {
+			compatible = "eswin,eic7700,bitfield";
+			offset,length = < 9 6 >;
+		};
+
+		SeqId {
+			compatible = "eswin,eic7700,bitfield";
+			offset,length = < 0 9 >;
+		};
+	};
+
+	ErrorLogger3 {
+		/* This register does not really include a bitfield or its bitfield is 32 bits and it provides an offset address */
+		/* To calculate the absolute address, you must use the initflow:targetflow:subrange from ErrorLogger1 register */
+		/* And use it as an index in the aperture table. Then you must add the value of this register to the value given */
+		/* by the table to get the absolute address. */
+		compatible = "eswin,eic7700,register";
+		offset,length = <0x20 32>;
+		description = "Register 3 to log errors";
+		aperture-link = <1>; /* link to ErrorLogger whose information are required to calculate real absolute address */
+		msb-link = <4>; /*indicate which ErrorLogger contains the msb addrs, -1 means no*/
+		AbsoluteAddress {
+			compatible = "eswin,eic7700,bitfield";
+			offset,length = < 9 14 >;		/* bitfield initflow:targeflow:subrange from aperture-link register */
+			aperture-size= < 1181 >;		/* Number of line in the aperture table below */
+			aperture-idx,aperture-base =		/* Aperture_idx is concatenation of initflow:targetflow:subrange bitfield from ErrorLogger1 */
+				/bits/ 64  <aon_snoc_sp0_I_O     snoc_cnoc_T_O      0x0             0x52060000        >,
+				/bits/ 64  <aon_snoc_sp0_I_O     snoc_cnoc_T_O      0x1             0x72060000        >,
+				/bits/ 64  <aon_snoc_sp0_I_O     snoc_cnoc_T_O      0x2             0x52100000        >,
+				/bits/ 64  <aon_snoc_sp0_I_O     snoc_cnoc_T_O      0x3             0x52200000        >,
+				/bits/ 64  <aon_snoc_sp0_I_O     snoc_cnoc_T_O      0x4             0x52300000        >,
+				/bits/ 64  <aon_snoc_sp0_I_O     snoc_cnoc_T_O      0x5             0x72100000        >,
+				/bits/ 64  <aon_snoc_sp0_I_O     snoc_cnoc_T_O      0x6             0x72200000        >,
+				/bits/ 64  <aon_snoc_sp0_I_O     snoc_cnoc_T_O      0x7             0x72300000        >,
+				/bits/ 64  <aon_snoc_sp0_I_O     snoc_cnoc_T_O      0x8             0x53000000        >,
+				/bits/ 64  <aon_snoc_sp0_I_O     snoc_cnoc_T_O      0x9             0x73000000        >,
+				/bits/ 64  <aon_snoc_sp0_I_O     snoc_cnoc_T_O      0xa             0x50000000        >,
+				/bits/ 64  <aon_snoc_sp0_I_O     snoc_cnoc_T_O      0xb             0x70000000        >,
+				/bits/ 64  <aon_snoc_sp0_I_O     snoc_cnoc_T_O      0xc             0x54000000        >,
+				/bits/ 64  <aon_snoc_sp0_I_O     snoc_cnoc_T_O      0xd             0x74000000        >,
+				/bits/ 64  <aon_snoc_sp0_I_O     snoc_cnoc_T_O      0xe             0x0               >,
+				/bits/ 64  <aon_snoc_sp0_I_O     snoc_cnoc_T_O      0xf             0x0               >,
+				/bits/ 64  <aon_snoc_sp0_I_O     snoc_cnoc_T_O      0x10            0x0               >,
+				/bits/ 64  <aon_snoc_sp0_I_O     snoc_dspt_T_O      0x0             0x520e0000        >,
+				/bits/ 64  <aon_snoc_sp0_I_O     snoc_dspt_T_O      0x1             0x720e0000        >,
+				/bits/ 64  <aon_snoc_sp0_I_O     snoc_dspt_T_O      0x2             0x5b000000        >,
+				/bits/ 64  <aon_snoc_sp0_I_O     snoc_dspt_T_O      0x3             0x7b000000        >,
+				/bits/ 64  <aon_snoc_sp0_I_O     snoc_lnoc_T_O      0x0             0x52080000        >,
+				/bits/ 64  <aon_snoc_sp0_I_O     snoc_lnoc_T_O      0x1             0x72080000        >,
+				/bits/ 64  <aon_snoc_sp0_I_O     snoc_mcput_d2d_T_O 0x0             0x58400000        >,
+				/bits/ 64  <aon_snoc_sp0_I_O     snoc_mcput_d2d_T_O 0x1             0x78400000        >,
+				/bits/ 64  <aon_snoc_sp0_I_O     snoc_mcput_d2d_T_O 0x2             0x58800000        >,
+				/bits/ 64  <aon_snoc_sp0_I_O     snoc_mcput_d2d_T_O 0x3             0x78800000        >,
+				/bits/ 64  <aon_snoc_sp0_I_O     snoc_mcput_d2d_T_O 0x4             0x59000000        >,
+				/bits/ 64  <aon_snoc_sp0_I_O     snoc_mcput_d2d_T_O 0x5             0x5a000000        >,
+				/bits/ 64  <aon_snoc_sp0_I_O     snoc_mcput_d2d_T_O 0x6             0x5b000000        >,
+				/bits/ 64  <aon_snoc_sp0_I_O     snoc_mcput_d2d_T_O 0x7             0x79000000        >,
+				/bits/ 64  <aon_snoc_sp0_I_O     snoc_mcput_d2d_T_O 0x8             0x7a000000        >,
+				/bits/ 64  <aon_snoc_sp0_I_O     snoc_mcput_d2d_T_O 0x9             0x7b000000        >,
+				/bits/ 64  <aon_snoc_sp0_I_O     snoc_mcput_d2d_T_O 0xa             0x50000000        >,
+				/bits/ 64  <aon_snoc_sp0_I_O     snoc_mcput_d2d_T_O 0xb             0x70000000        >,
+				/bits/ 64  <aon_snoc_sp0_I_O     snoc_mcput_d2d_T_O 0xc             0x40000000        >,
+				/bits/ 64  <aon_snoc_sp0_I_O     snoc_mcput_d2d_T_O 0xd             0x60000000        >,
+				/bits/ 64  <aon_snoc_sp0_I_O     snoc_mnoc_T_O      0x0             0x52020000        >,
+				/bits/ 64  <aon_snoc_sp0_I_O     snoc_mnoc_T_O      0x1             0x72020000        >,
+				/bits/ 64  <aon_snoc_sp0_I_O     snoc_npu_T_O       0x0             0x52080000        >,
+				/bits/ 64  <aon_snoc_sp0_I_O     snoc_npu_T_O       0x1             0x72080000        >,
+				/bits/ 64  <aon_snoc_sp0_I_O     snoc_npu_T_O       0x2             0x59000000        >,
+				/bits/ 64  <aon_snoc_sp0_I_O     snoc_npu_T_O       0x3             0x5a000000        >,
+				/bits/ 64  <aon_snoc_sp0_I_O     snoc_npu_T_O       0x4             0x79000000        >,
+				/bits/ 64  <aon_snoc_sp0_I_O     snoc_npu_T_O       0x5             0x7a000000        >,
+				/bits/ 64  <aon_snoc_sp0_I_O     snoc_pciet_T_O     0x0             0x40000000        >,
+				/bits/ 64  <aon_snoc_sp0_I_O     snoc_pciet_T_O     0x1             0x60000000        >,
+				/bits/ 64  <aon_snoc_sp0_I_O     snoc_rnoc_T_O      0x0             0x52040000        >,
+				/bits/ 64  <aon_snoc_sp0_I_O     snoc_rnoc_T_O      0x1             0x72040000        >,
+				/bits/ 64  <aon_snoc_sp0_I_O     snoc_service_T_O   0x0             0x52000000        >,
+				/bits/ 64  <aon_snoc_sp0_I_O     snoc_service_T_O   0x1             0x72000000        >,
+				/bits/ 64  <dspt_snoc_I_O        snoc_aon_T_O       0x0             0x520c0000        >,
+				/bits/ 64  <dspt_snoc_I_O        snoc_aon_T_O       0x1             0x720c0000        >,
+				/bits/ 64  <dspt_snoc_I_O        snoc_aon_T_O       0x2             0x58400000        >,
+				/bits/ 64  <dspt_snoc_I_O        snoc_aon_T_O       0x3             0x78400000        >,
+				/bits/ 64  <dspt_snoc_I_O        snoc_aon_T_O       0x4             0x14000400000     >,
+				/bits/ 64  <dspt_snoc_I_O        snoc_aon_T_O       0x5             0x14008400000     >,
+				/bits/ 64  <dspt_snoc_I_O        snoc_aon_T_O       0x6             0x58800000        >,
+				/bits/ 64  <dspt_snoc_I_O        snoc_aon_T_O       0x7             0x78800000        >,
+				/bits/ 64  <dspt_snoc_I_O        snoc_aon_T_O       0x8             0x14000800000     >,
+				/bits/ 64  <dspt_snoc_I_O        snoc_aon_T_O       0x9             0x14008800000     >,
+				/bits/ 64  <dspt_snoc_I_O        snoc_aon_T_O       0xa             0x5c000000        >,
+				/bits/ 64  <dspt_snoc_I_O        snoc_aon_T_O       0xb             0x7c000000        >,
+				/bits/ 64  <dspt_snoc_I_O        snoc_aon_T_O       0xc             0x14004000000     >,
+				/bits/ 64  <dspt_snoc_I_O        snoc_aon_T_O       0xd             0x1400c000000     >,
+				/bits/ 64  <dspt_snoc_I_O        snoc_cnoc_T_O      0x0             0x52060000        >,
+				/bits/ 64  <dspt_snoc_I_O        snoc_cnoc_T_O      0x1             0x72060000        >,
+				/bits/ 64  <dspt_snoc_I_O        snoc_cnoc_T_O      0x2             0x52100000        >,
+				/bits/ 64  <dspt_snoc_I_O        snoc_cnoc_T_O      0x3             0x52200000        >,
+				/bits/ 64  <dspt_snoc_I_O        snoc_cnoc_T_O      0x4             0x52300000        >,
+				/bits/ 64  <dspt_snoc_I_O        snoc_cnoc_T_O      0x5             0x72100000        >,
+				/bits/ 64  <dspt_snoc_I_O        snoc_cnoc_T_O      0x6             0x72200000        >,
+				/bits/ 64  <dspt_snoc_I_O        snoc_cnoc_T_O      0x7             0x72300000        >,
+				/bits/ 64  <dspt_snoc_I_O        snoc_cnoc_T_O      0x8             0x53000000        >,
+				/bits/ 64  <dspt_snoc_I_O        snoc_cnoc_T_O      0x9             0x73000000        >,
+				/bits/ 64  <dspt_snoc_I_O        snoc_cnoc_T_O      0xa             0x50000000        >,
+				/bits/ 64  <dspt_snoc_I_O        snoc_cnoc_T_O      0xb             0x70000000        >,
+				/bits/ 64  <dspt_snoc_I_O        snoc_cnoc_T_O      0xc             0x54000000        >,
+				/bits/ 64  <dspt_snoc_I_O        snoc_cnoc_T_O      0xd             0x74000000        >,
+				/bits/ 64  <dspt_snoc_I_O        snoc_cnoc_T_O      0xe             0x0               >,
+				/bits/ 64  <dspt_snoc_I_O        snoc_ddrt0_p2_T_O  0x0             0x80000000        >,
+				/bits/ 64  <dspt_snoc_I_O        snoc_ddrt0_p2_T_O  0x1             0x100000000       >,
+				/bits/ 64  <dspt_snoc_I_O        snoc_ddrt0_p2_T_O  0x2             0x200000000       >,
+				/bits/ 64  <dspt_snoc_I_O        snoc_ddrt0_p2_T_O  0x3             0x400000000       >,
+				/bits/ 64  <dspt_snoc_I_O        snoc_ddrt0_p2_T_O  0x4             0x800000000       >,
+				/bits/ 64  <dspt_snoc_I_O        snoc_ddrt0_p2_T_O  0x5             0x2000000000      >,
+				/bits/ 64  <dspt_snoc_I_O        snoc_ddrt0_p2_T_O  0x6             0xc000000000      >,
+				/bits/ 64  <dspt_snoc_I_O        snoc_ddrt0_p2_T_O  0x7             0xe000000000      >,
+				/bits/ 64  <dspt_snoc_I_O        snoc_ddrt0_p2_T_O  0x8             0x4000000000      >,
+				/bits/ 64  <dspt_snoc_I_O        snoc_ddrt0_p2_T_O  0x9             0x4000000100      >,
+				/bits/ 64  <dspt_snoc_I_O        snoc_ddrt0_p2_T_O  0xa             0x10000000000     >,
+				/bits/ 64  <dspt_snoc_I_O        snoc_ddrt0_p2_T_O  0xb             0x10000000100     >,
+				/bits/ 64  <dspt_snoc_I_O        snoc_ddrt1_p2_T_O  0x0             0x80000080        >,
+				/bits/ 64  <dspt_snoc_I_O        snoc_ddrt1_p2_T_O  0x1             0x100000080       >,
+				/bits/ 64  <dspt_snoc_I_O        snoc_ddrt1_p2_T_O  0x2             0x200000080       >,
+				/bits/ 64  <dspt_snoc_I_O        snoc_ddrt1_p2_T_O  0x3             0x400000080       >,
+				/bits/ 64  <dspt_snoc_I_O        snoc_ddrt1_p2_T_O  0x4             0x800000080       >,
+				/bits/ 64  <dspt_snoc_I_O        snoc_ddrt1_p2_T_O  0x5             0x2000000080      >,
+				/bits/ 64  <dspt_snoc_I_O        snoc_ddrt1_p2_T_O  0x6             0xc000000080      >,
+				/bits/ 64  <dspt_snoc_I_O        snoc_ddrt1_p2_T_O  0x7             0xe000000080      >,
+				/bits/ 64  <dspt_snoc_I_O        snoc_ddrt1_p2_T_O  0x8             0x4000000080      >,
+				/bits/ 64  <dspt_snoc_I_O        snoc_ddrt1_p2_T_O  0x9             0x4000000180      >,
+				/bits/ 64  <dspt_snoc_I_O        snoc_ddrt1_p2_T_O  0xa             0x10000000080     >,
+				/bits/ 64  <dspt_snoc_I_O        snoc_ddrt1_p2_T_O  0xb             0x10000000180     >,
+				/bits/ 64  <dspt_snoc_I_O        snoc_mcput_d2d_T_O 0x0             0x58400000        >,
+				/bits/ 64  <dspt_snoc_I_O        snoc_mcput_d2d_T_O 0x1             0x78400000        >,
+				/bits/ 64  <dspt_snoc_I_O        snoc_mcput_d2d_T_O 0x2             0x14000400000     >,
+				/bits/ 64  <dspt_snoc_I_O        snoc_mcput_d2d_T_O 0x3             0x14008400000     >,
+				/bits/ 64  <dspt_snoc_I_O        snoc_mcput_d2d_T_O 0x4             0x58800000        >,
+				/bits/ 64  <dspt_snoc_I_O        snoc_mcput_d2d_T_O 0x5             0x78800000        >,
+				/bits/ 64  <dspt_snoc_I_O        snoc_mcput_d2d_T_O 0x6             0x14000800000     >,
+				/bits/ 64  <dspt_snoc_I_O        snoc_mcput_d2d_T_O 0x7             0x14008800000     >,
+				/bits/ 64  <dspt_snoc_I_O        snoc_mcput_d2d_T_O 0x8             0x59000000        >,
+				/bits/ 64  <dspt_snoc_I_O        snoc_mcput_d2d_T_O 0x9             0x5a000000        >,
+				/bits/ 64  <dspt_snoc_I_O        snoc_mcput_d2d_T_O 0xa             0x5b000000        >,
+				/bits/ 64  <dspt_snoc_I_O        snoc_mcput_d2d_T_O 0xb             0x79000000        >,
+				/bits/ 64  <dspt_snoc_I_O        snoc_mcput_d2d_T_O 0xc             0x7a000000        >,
+				/bits/ 64  <dspt_snoc_I_O        snoc_mcput_d2d_T_O 0xd             0x7b000000        >,
+				/bits/ 64  <dspt_snoc_I_O        snoc_mcput_d2d_T_O 0xe             0x14001000000     >,
+				/bits/ 64  <dspt_snoc_I_O        snoc_mcput_d2d_T_O 0xf             0x14002000000     >,
+				/bits/ 64  <dspt_snoc_I_O        snoc_mcput_d2d_T_O 0x10            0x14003000000     >,
+				/bits/ 64  <dspt_snoc_I_O        snoc_mcput_d2d_T_O 0x11            0x14009000000     >,
+				/bits/ 64  <dspt_snoc_I_O        snoc_mcput_d2d_T_O 0x12            0x1400a000000     >,
+				/bits/ 64  <dspt_snoc_I_O        snoc_mcput_d2d_T_O 0x13            0x1400b000000     >,
+				/bits/ 64  <dspt_snoc_I_O        snoc_mcput_d2d_T_O 0x14            0x50000000        >,
+				/bits/ 64  <dspt_snoc_I_O        snoc_mcput_d2d_T_O 0x15            0x70000000        >,
+				/bits/ 64  <dspt_snoc_I_O        snoc_mcput_d2d_T_O 0x16            0x40000000        >,
+				/bits/ 64  <dspt_snoc_I_O        snoc_mcput_d2d_T_O 0x17            0x60000000        >,
+				/bits/ 64  <dspt_snoc_I_O        snoc_mcput_d2d_T_O 0x18            0x80000000        >,
+				/bits/ 64  <dspt_snoc_I_O        snoc_mcput_d2d_T_O 0x19            0x100000000       >,
+				/bits/ 64  <dspt_snoc_I_O        snoc_mcput_d2d_T_O 0x1a            0x200000000       >,
+				/bits/ 64  <dspt_snoc_I_O        snoc_mcput_d2d_T_O 0x1b            0x400000000       >,
+				/bits/ 64  <dspt_snoc_I_O        snoc_mcput_d2d_T_O 0x1c            0x800000000       >,
+				/bits/ 64  <dspt_snoc_I_O        snoc_mcput_d2d_T_O 0x1d            0x1800000000      >,
+				/bits/ 64  <dspt_snoc_I_O        snoc_mcput_d2d_T_O 0x1e            0x3800000000      >,
+				/bits/ 64  <dspt_snoc_I_O        snoc_mcput_d2d_T_O 0x1f            0xd800000000      >,
+				/bits/ 64  <dspt_snoc_I_O        snoc_mcput_d2d_T_O 0x20            0xf800000000      >,
+				/bits/ 64  <dspt_snoc_I_O        snoc_mcput_d2d_T_O 0x21            0x2000000000      >,
+				/bits/ 64  <dspt_snoc_I_O        snoc_mcput_d2d_T_O 0x22            0x7000000000      >,
+				/bits/ 64  <dspt_snoc_I_O        snoc_mcput_d2d_T_O 0x23            0x7000000100      >,
+				/bits/ 64  <dspt_snoc_I_O        snoc_mcput_d2d_T_O 0x24            0xc000000000      >,
+				/bits/ 64  <dspt_snoc_I_O        snoc_mcput_d2d_T_O 0x25            0xe000000000      >,
+				/bits/ 64  <dspt_snoc_I_O        snoc_mcput_d2d_T_O 0x26            0x13000000000     >,
+				/bits/ 64  <dspt_snoc_I_O        snoc_mcput_d2d_T_O 0x27            0x13000000100     >,
+				/bits/ 64  <dspt_snoc_I_O        snoc_mcput_d2d_T_O 0x28            0x4000000000      >,
+				/bits/ 64  <dspt_snoc_I_O        snoc_mcput_d2d_T_O 0x29            0x4000000100      >,
+				/bits/ 64  <dspt_snoc_I_O        snoc_mcput_d2d_T_O 0x2a            0x8000000000      >,
+				/bits/ 64  <dspt_snoc_I_O        snoc_mcput_d2d_T_O 0x2b            0xa000000000      >,
+				/bits/ 64  <dspt_snoc_I_O        snoc_mcput_d2d_T_O 0x2c            0x10000000000     >,
+				/bits/ 64  <dspt_snoc_I_O        snoc_mcput_d2d_T_O 0x2d            0x10000000100     >,
+				/bits/ 64  <dspt_snoc_I_O        snoc_npu_T_O       0x0             0x52080000        >,
+				/bits/ 64  <dspt_snoc_I_O        snoc_npu_T_O       0x1             0x72080000        >,
+				/bits/ 64  <dspt_snoc_I_O        snoc_npu_T_O       0x2             0x59000000        >,
+				/bits/ 64  <dspt_snoc_I_O        snoc_npu_T_O       0x3             0x5a000000        >,
+				/bits/ 64  <dspt_snoc_I_O        snoc_npu_T_O       0x4             0x79000000        >,
+				/bits/ 64  <dspt_snoc_I_O        snoc_npu_T_O       0x5             0x7a000000        >,
+				/bits/ 64  <dspt_snoc_I_O        snoc_npu_T_O       0x6             0x14001000000     >,
+				/bits/ 64  <dspt_snoc_I_O        snoc_npu_T_O       0x7             0x14002000000     >,
+				/bits/ 64  <dspt_snoc_I_O        snoc_npu_T_O       0x8             0x14009000000     >,
+				/bits/ 64  <dspt_snoc_I_O        snoc_npu_T_O       0x9             0x1400a000000     >,
+				/bits/ 64  <dspt_snoc_I_O        snoc_npu_T_O       0xa             0x1800000000      >,
+				/bits/ 64  <dspt_snoc_I_O        snoc_npu_T_O       0xb             0x3800000000      >,
+				/bits/ 64  <dspt_snoc_I_O        snoc_npu_T_O       0xc             0xd800000000      >,
+				/bits/ 64  <dspt_snoc_I_O        snoc_npu_T_O       0xd             0xf800000000      >,
+				/bits/ 64  <dspt_snoc_I_O        snoc_npu_T_O       0xe             0x7000000000      >,
+				/bits/ 64  <dspt_snoc_I_O        snoc_npu_T_O       0xf             0x7000000100      >,
+				/bits/ 64  <dspt_snoc_I_O        snoc_npu_T_O       0x10            0x13000000000     >,
+				/bits/ 64  <dspt_snoc_I_O        snoc_npu_T_O       0x11            0x13000000100     >,
+				/bits/ 64  <dspt_snoc_I_O        snoc_pciet_T_O     0x0             0x40000000        >,
+				/bits/ 64  <dspt_snoc_I_O        snoc_pciet_T_O     0x1             0x60000000        >,
+				/bits/ 64  <dspt_snoc_I_O        snoc_pciet_T_O     0x2             0x8000000000      >,
+				/bits/ 64  <dspt_snoc_I_O        snoc_pciet_T_O     0x3             0xa000000000      >,
+				/bits/ 64  <jtag_snoc_I_O        snoc_cnoc_T_O      0x0             0x52060000        >,
+				/bits/ 64  <jtag_snoc_I_O        snoc_cnoc_T_O      0x1             0x72060000        >,
+				/bits/ 64  <jtag_snoc_I_O        snoc_cnoc_T_O      0x2             0x52100000        >,
+				/bits/ 64  <jtag_snoc_I_O        snoc_cnoc_T_O      0x3             0x52200000        >,
+				/bits/ 64  <jtag_snoc_I_O        snoc_cnoc_T_O      0x4             0x52300000        >,
+				/bits/ 64  <jtag_snoc_I_O        snoc_cnoc_T_O      0x5             0x72100000        >,
+				/bits/ 64  <jtag_snoc_I_O        snoc_cnoc_T_O      0x6             0x72200000        >,
+				/bits/ 64  <jtag_snoc_I_O        snoc_cnoc_T_O      0x7             0x72300000        >,
+				/bits/ 64  <jtag_snoc_I_O        snoc_cnoc_T_O      0x8             0x53000000        >,
+				/bits/ 64  <jtag_snoc_I_O        snoc_cnoc_T_O      0x9             0x73000000        >,
+				/bits/ 64  <jtag_snoc_I_O        snoc_cnoc_T_O      0xa             0x50000000        >,
+				/bits/ 64  <jtag_snoc_I_O        snoc_cnoc_T_O      0xb             0x70000000        >,
+				/bits/ 64  <jtag_snoc_I_O        snoc_cnoc_T_O      0xc             0x54000000        >,
+				/bits/ 64  <jtag_snoc_I_O        snoc_cnoc_T_O      0xd             0x74000000        >,
+				/bits/ 64  <jtag_snoc_I_O        snoc_cnoc_T_O      0xe             0x0               >,
+				/bits/ 64  <jtag_snoc_I_O        snoc_cnoc_T_O      0xf             0x0               >,
+				/bits/ 64  <jtag_snoc_I_O        snoc_cnoc_T_O      0x10            0x0               >,
+				/bits/ 64  <jtag_snoc_I_O        snoc_lnoc_T_O      0x0             0x52080000        >,
+				/bits/ 64  <jtag_snoc_I_O        snoc_lnoc_T_O      0x1             0x72080000        >,
+				/bits/ 64  <jtag_snoc_I_O        snoc_mnoc_T_O      0x0             0x52020000        >,
+				/bits/ 64  <jtag_snoc_I_O        snoc_mnoc_T_O      0x1             0x72020000        >,
+				/bits/ 64  <jtag_snoc_I_O        snoc_rnoc_T_O      0x0             0x52040000        >,
+				/bits/ 64  <jtag_snoc_I_O        snoc_rnoc_T_O      0x1             0x72040000        >,
+				/bits/ 64  <jtag_snoc_I_O        snoc_service_T_O   0x0             0x52000000        >,
+				/bits/ 64  <jtag_snoc_I_O        snoc_service_T_O   0x1             0x72000000        >,
+				/bits/ 64  <mcput_snoc_d2d_I_O   snoc_aon_T_O       0x0             0x520c0000        >,
+				/bits/ 64  <mcput_snoc_d2d_I_O   snoc_aon_T_O       0x1             0x720c0000        >,
+				/bits/ 64  <mcput_snoc_d2d_I_O   snoc_aon_T_O       0x2             0x58400000        >,
+				/bits/ 64  <mcput_snoc_d2d_I_O   snoc_aon_T_O       0x3             0x78400000        >,
+				/bits/ 64  <mcput_snoc_d2d_I_O   snoc_aon_T_O       0x4             0x14000400000     >,
+				/bits/ 64  <mcput_snoc_d2d_I_O   snoc_aon_T_O       0x5             0x14008400000     >,
+				/bits/ 64  <mcput_snoc_d2d_I_O   snoc_aon_T_O       0x6             0x58800000        >,
+				/bits/ 64  <mcput_snoc_d2d_I_O   snoc_aon_T_O       0x7             0x78800000        >,
+				/bits/ 64  <mcput_snoc_d2d_I_O   snoc_aon_T_O       0x8             0x14000800000     >,
+				/bits/ 64  <mcput_snoc_d2d_I_O   snoc_aon_T_O       0x9             0x14008800000     >,
+				/bits/ 64  <mcput_snoc_d2d_I_O   snoc_aon_T_O       0xa             0x5c000000        >,
+				/bits/ 64  <mcput_snoc_d2d_I_O   snoc_aon_T_O       0xb             0x7c000000        >,
+				/bits/ 64  <mcput_snoc_d2d_I_O   snoc_aon_T_O       0xc             0x14004000000     >,
+				/bits/ 64  <mcput_snoc_d2d_I_O   snoc_aon_T_O       0xd             0x1400c000000     >,
+				/bits/ 64  <mcput_snoc_d2d_I_O   snoc_cnoc_T_O      0x0             0x52060000        >,
+				/bits/ 64  <mcput_snoc_d2d_I_O   snoc_cnoc_T_O      0x1             0x72060000        >,
+				/bits/ 64  <mcput_snoc_d2d_I_O   snoc_cnoc_T_O      0x2             0x52100000        >,
+				/bits/ 64  <mcput_snoc_d2d_I_O   snoc_cnoc_T_O      0x3             0x52200000        >,
+				/bits/ 64  <mcput_snoc_d2d_I_O   snoc_cnoc_T_O      0x4             0x52300000        >,
+				/bits/ 64  <mcput_snoc_d2d_I_O   snoc_cnoc_T_O      0x5             0x72100000        >,
+				/bits/ 64  <mcput_snoc_d2d_I_O   snoc_cnoc_T_O      0x6             0x72200000        >,
+				/bits/ 64  <mcput_snoc_d2d_I_O   snoc_cnoc_T_O      0x7             0x72300000        >,
+				/bits/ 64  <mcput_snoc_d2d_I_O   snoc_cnoc_T_O      0x8             0x53000000        >,
+				/bits/ 64  <mcput_snoc_d2d_I_O   snoc_cnoc_T_O      0x9             0x73000000        >,
+				/bits/ 64  <mcput_snoc_d2d_I_O   snoc_cnoc_T_O      0xa             0x50000000        >,
+				/bits/ 64  <mcput_snoc_d2d_I_O   snoc_cnoc_T_O      0xb             0x70000000        >,
+				/bits/ 64  <mcput_snoc_d2d_I_O   snoc_cnoc_T_O      0xc             0x54000000        >,
+				/bits/ 64  <mcput_snoc_d2d_I_O   snoc_cnoc_T_O      0xd             0x74000000        >,
+				/bits/ 64  <mcput_snoc_d2d_I_O   snoc_cnoc_T_O      0xe             0x0               >,
+				/bits/ 64  <mcput_snoc_d2d_I_O   snoc_ddrt0_p2_T_O  0x0             0x80000000        >,
+				/bits/ 64  <mcput_snoc_d2d_I_O   snoc_ddrt0_p2_T_O  0x1             0x100000000       >,
+				/bits/ 64  <mcput_snoc_d2d_I_O   snoc_ddrt0_p2_T_O  0x2             0x200000000       >,
+				/bits/ 64  <mcput_snoc_d2d_I_O   snoc_ddrt0_p2_T_O  0x3             0x400000000       >,
+				/bits/ 64  <mcput_snoc_d2d_I_O   snoc_ddrt0_p2_T_O  0x4             0x800000000       >,
+				/bits/ 64  <mcput_snoc_d2d_I_O   snoc_ddrt0_p2_T_O  0x5             0x2000000000      >,
+				/bits/ 64  <mcput_snoc_d2d_I_O   snoc_ddrt0_p2_T_O  0x6             0xc000000000      >,
+				/bits/ 64  <mcput_snoc_d2d_I_O   snoc_ddrt0_p2_T_O  0x7             0xe000000000      >,
+				/bits/ 64  <mcput_snoc_d2d_I_O   snoc_ddrt0_p2_T_O  0x8             0x4000000000      >,
+				/bits/ 64  <mcput_snoc_d2d_I_O   snoc_ddrt0_p2_T_O  0x9             0x4000000100      >,
+				/bits/ 64  <mcput_snoc_d2d_I_O   snoc_ddrt0_p2_T_O  0xa             0x10000000000     >,
+				/bits/ 64  <mcput_snoc_d2d_I_O   snoc_ddrt0_p2_T_O  0xb             0x10000000100     >,
+				/bits/ 64  <mcput_snoc_d2d_I_O   snoc_ddrt1_p2_T_O  0x0             0x80000080        >,
+				/bits/ 64  <mcput_snoc_d2d_I_O   snoc_ddrt1_p2_T_O  0x1             0x100000080       >,
+				/bits/ 64  <mcput_snoc_d2d_I_O   snoc_ddrt1_p2_T_O  0x2             0x200000080       >,
+				/bits/ 64  <mcput_snoc_d2d_I_O   snoc_ddrt1_p2_T_O  0x3             0x400000080       >,
+				/bits/ 64  <mcput_snoc_d2d_I_O   snoc_ddrt1_p2_T_O  0x4             0x800000080       >,
+				/bits/ 64  <mcput_snoc_d2d_I_O   snoc_ddrt1_p2_T_O  0x5             0x2000000080      >,
+				/bits/ 64  <mcput_snoc_d2d_I_O   snoc_ddrt1_p2_T_O  0x6             0xc000000080      >,
+				/bits/ 64  <mcput_snoc_d2d_I_O   snoc_ddrt1_p2_T_O  0x7             0xe000000080      >,
+				/bits/ 64  <mcput_snoc_d2d_I_O   snoc_ddrt1_p2_T_O  0x8             0x4000000080      >,
+				/bits/ 64  <mcput_snoc_d2d_I_O   snoc_ddrt1_p2_T_O  0x9             0x4000000180      >,
+				/bits/ 64  <mcput_snoc_d2d_I_O   snoc_ddrt1_p2_T_O  0xa             0x10000000080     >,
+				/bits/ 64  <mcput_snoc_d2d_I_O   snoc_ddrt1_p2_T_O  0xb             0x10000000180     >,
+				/bits/ 64  <mcput_snoc_d2d_I_O   snoc_dspt_T_O      0x0             0x520e0000        >,
+				/bits/ 64  <mcput_snoc_d2d_I_O   snoc_dspt_T_O      0x1             0x720e0000        >,
+				/bits/ 64  <mcput_snoc_d2d_I_O   snoc_dspt_T_O      0x2             0x5b000000        >,
+				/bits/ 64  <mcput_snoc_d2d_I_O   snoc_dspt_T_O      0x3             0x7b000000        >,
+				/bits/ 64  <mcput_snoc_d2d_I_O   snoc_dspt_T_O      0x4             0x14003000000     >,
+				/bits/ 64  <mcput_snoc_d2d_I_O   snoc_dspt_T_O      0x5             0x1400b000000     >,
+				/bits/ 64  <mcput_snoc_d2d_I_O   snoc_lnoc_T_O      0x0             0x52080000        >,
+				/bits/ 64  <mcput_snoc_d2d_I_O   snoc_lnoc_T_O      0x1             0x72080000        >,
+				/bits/ 64  <mcput_snoc_d2d_I_O   snoc_mnoc_T_O      0x0             0x52020000        >,
+				/bits/ 64  <mcput_snoc_d2d_I_O   snoc_mnoc_T_O      0x1             0x72020000        >,
+				/bits/ 64  <mcput_snoc_d2d_I_O   snoc_npu_T_O       0x0             0x52080000        >,
+				/bits/ 64  <mcput_snoc_d2d_I_O   snoc_npu_T_O       0x1             0x72080000        >,
+				/bits/ 64  <mcput_snoc_d2d_I_O   snoc_npu_T_O       0x2             0x59000000        >,
+				/bits/ 64  <mcput_snoc_d2d_I_O   snoc_npu_T_O       0x3             0x5a000000        >,
+				/bits/ 64  <mcput_snoc_d2d_I_O   snoc_npu_T_O       0x4             0x79000000        >,
+				/bits/ 64  <mcput_snoc_d2d_I_O   snoc_npu_T_O       0x5             0x7a000000        >,
+				/bits/ 64  <mcput_snoc_d2d_I_O   snoc_npu_T_O       0x6             0x14001000000     >,
+				/bits/ 64  <mcput_snoc_d2d_I_O   snoc_npu_T_O       0x7             0x14002000000     >,
+				/bits/ 64  <mcput_snoc_d2d_I_O   snoc_npu_T_O       0x8             0x14009000000     >,
+				/bits/ 64  <mcput_snoc_d2d_I_O   snoc_npu_T_O       0x9             0x1400a000000     >,
+				/bits/ 64  <mcput_snoc_d2d_I_O   snoc_npu_T_O       0xa             0x1800000000      >,
+				/bits/ 64  <mcput_snoc_d2d_I_O   snoc_npu_T_O       0xb             0x3800000000      >,
+				/bits/ 64  <mcput_snoc_d2d_I_O   snoc_npu_T_O       0xc             0xd800000000      >,
+				/bits/ 64  <mcput_snoc_d2d_I_O   snoc_npu_T_O       0xd             0xf800000000      >,
+				/bits/ 64  <mcput_snoc_d2d_I_O   snoc_npu_T_O       0xe             0x7000000000      >,
+				/bits/ 64  <mcput_snoc_d2d_I_O   snoc_npu_T_O       0xf             0x7000000100      >,
+				/bits/ 64  <mcput_snoc_d2d_I_O   snoc_npu_T_O       0x10            0x13000000000     >,
+				/bits/ 64  <mcput_snoc_d2d_I_O   snoc_npu_T_O       0x11            0x13000000100     >,
+				/bits/ 64  <mcput_snoc_d2d_I_O   snoc_pciet_T_O     0x0             0x40000000        >,
+				/bits/ 64  <mcput_snoc_d2d_I_O   snoc_pciet_T_O     0x1             0x60000000        >,
+				/bits/ 64  <mcput_snoc_d2d_I_O   snoc_pciet_T_O     0x2             0x8000000000      >,
+				/bits/ 64  <mcput_snoc_d2d_I_O   snoc_pciet_T_O     0x3             0xa000000000      >,
+				/bits/ 64  <mcput_snoc_d2d_I_O   snoc_rnoc_T_O      0x0             0x52040000        >,
+				/bits/ 64  <mcput_snoc_d2d_I_O   snoc_rnoc_T_O      0x1             0x72040000        >,
+				/bits/ 64  <mcput_snoc_d2d_I_O   snoc_service_T_O   0x0             0x52000000        >,
+				/bits/ 64  <mcput_snoc_d2d_I_O   snoc_service_T_O   0x1             0x72000000        >,
+				/bits/ 64  <mcput_snoc_mp_I_O    snoc_ddrt0_p1_T_O  0x0             0x80000000        >,
+				/bits/ 64  <mcput_snoc_mp_I_O    snoc_ddrt0_p1_T_O  0x1             0x100000000       >,
+				/bits/ 64  <mcput_snoc_mp_I_O    snoc_ddrt0_p1_T_O  0x2             0x200000000       >,
+				/bits/ 64  <mcput_snoc_mp_I_O    snoc_ddrt0_p1_T_O  0x3             0x400000000       >,
+				/bits/ 64  <mcput_snoc_mp_I_O    snoc_ddrt0_p1_T_O  0x4             0x800000000       >,
+				/bits/ 64  <mcput_snoc_mp_I_O    snoc_ddrt0_p1_T_O  0x5             0x2000000000      >,
+				/bits/ 64  <mcput_snoc_mp_I_O    snoc_ddrt0_p1_T_O  0x6             0x4000000000      >,
+				/bits/ 64  <mcput_snoc_mp_I_O    snoc_ddrt0_p1_T_O  0x7             0x4000000100      >,
+				/bits/ 64  <mcput_snoc_mp_I_O    snoc_ddrt1_p1_T_O  0x0             0x80000080        >,
+				/bits/ 64  <mcput_snoc_mp_I_O    snoc_ddrt1_p1_T_O  0x1             0x100000080       >,
+				/bits/ 64  <mcput_snoc_mp_I_O    snoc_ddrt1_p1_T_O  0x2             0x200000080       >,
+				/bits/ 64  <mcput_snoc_mp_I_O    snoc_ddrt1_p1_T_O  0x3             0x400000080       >,
+				/bits/ 64  <mcput_snoc_mp_I_O    snoc_ddrt1_p1_T_O  0x4             0x800000080       >,
+				/bits/ 64  <mcput_snoc_mp_I_O    snoc_ddrt1_p1_T_O  0x5             0x2000000080      >,
+				/bits/ 64  <mcput_snoc_mp_I_O    snoc_ddrt1_p1_T_O  0x6             0x4000000080      >,
+				/bits/ 64  <mcput_snoc_mp_I_O    snoc_ddrt1_p1_T_O  0x7             0x4000000180      >,
+				/bits/ 64  <mcput_snoc_mp_I_O    snoc_npu_T_O       0x0             0x52080000        >,
+				/bits/ 64  <mcput_snoc_mp_I_O    snoc_npu_T_O       0x1             0x72080000        >,
+				/bits/ 64  <mcput_snoc_mp_I_O    snoc_npu_T_O       0x2             0x59000000        >,
+				/bits/ 64  <mcput_snoc_mp_I_O    snoc_npu_T_O       0x3             0x5a000000        >,
+				/bits/ 64  <mcput_snoc_mp_I_O    snoc_npu_T_O       0x4             0x79000000        >,
+				/bits/ 64  <mcput_snoc_mp_I_O    snoc_npu_T_O       0x5             0x7a000000        >,
+				/bits/ 64  <mcput_snoc_mp_I_O    snoc_npu_T_O       0x6             0x1800000000      >,
+				/bits/ 64  <mcput_snoc_mp_I_O    snoc_npu_T_O       0x7             0x3800000000      >,
+				/bits/ 64  <mcput_snoc_mp_I_O    snoc_npu_T_O       0x8             0x7000000000      >,
+				/bits/ 64  <mcput_snoc_mp_I_O    snoc_npu_T_O       0x9             0x7000000100      >,
+				/bits/ 64  <mcput_snoc_mp_I_O    snoc_npu_T_O       0xa             0x0               >,
+				/bits/ 64  <mcput_snoc_mp_I_O    snoc_npu_T_O       0xb             0x0               >,
+				/bits/ 64  <mcput_snoc_sp0_I_O   snoc_aon_T_O       0x0             0x520c0000        >,
+				/bits/ 64  <mcput_snoc_sp0_I_O   snoc_aon_T_O       0x1             0x720c0000        >,
+				/bits/ 64  <mcput_snoc_sp0_I_O   snoc_aon_T_O       0x2             0x58400000        >,
+				/bits/ 64  <mcput_snoc_sp0_I_O   snoc_aon_T_O       0x3             0x78400000        >,
+				/bits/ 64  <mcput_snoc_sp0_I_O   snoc_aon_T_O       0x4             0x58800000        >,
+				/bits/ 64  <mcput_snoc_sp0_I_O   snoc_aon_T_O       0x5             0x78800000        >,
+				/bits/ 64  <mcput_snoc_sp0_I_O   snoc_aon_T_O       0x6             0x5c000000        >,
+				/bits/ 64  <mcput_snoc_sp0_I_O   snoc_aon_T_O       0x7             0x7c000000        >,
+				/bits/ 64  <mcput_snoc_sp0_I_O   snoc_cnoc_T_O      0x0             0x52060000        >,
+				/bits/ 64  <mcput_snoc_sp0_I_O   snoc_cnoc_T_O      0x1             0x72060000        >,
+				/bits/ 64  <mcput_snoc_sp0_I_O   snoc_cnoc_T_O      0x2             0x52100000        >,
+				/bits/ 64  <mcput_snoc_sp0_I_O   snoc_cnoc_T_O      0x3             0x52200000        >,
+				/bits/ 64  <mcput_snoc_sp0_I_O   snoc_cnoc_T_O      0x4             0x52300000        >,
+				/bits/ 64  <mcput_snoc_sp0_I_O   snoc_cnoc_T_O      0x5             0x72100000        >,
+				/bits/ 64  <mcput_snoc_sp0_I_O   snoc_cnoc_T_O      0x6             0x72200000        >,
+				/bits/ 64  <mcput_snoc_sp0_I_O   snoc_cnoc_T_O      0x7             0x72300000        >,
+				/bits/ 64  <mcput_snoc_sp0_I_O   snoc_cnoc_T_O      0x8             0x53000000        >,
+				/bits/ 64  <mcput_snoc_sp0_I_O   snoc_cnoc_T_O      0x9             0x73000000        >,
+				/bits/ 64  <mcput_snoc_sp0_I_O   snoc_cnoc_T_O      0xa             0x50000000        >,
+				/bits/ 64  <mcput_snoc_sp0_I_O   snoc_cnoc_T_O      0xb             0x70000000        >,
+				/bits/ 64  <mcput_snoc_sp0_I_O   snoc_cnoc_T_O      0xc             0x54000000        >,
+				/bits/ 64  <mcput_snoc_sp0_I_O   snoc_cnoc_T_O      0xd             0x74000000        >,
+				/bits/ 64  <mcput_snoc_sp0_I_O   snoc_cnoc_T_O      0xe             0x0               >,
+				/bits/ 64  <mcput_snoc_sp0_I_O   snoc_dspt_T_O      0x0             0x520e0000        >,
+				/bits/ 64  <mcput_snoc_sp0_I_O   snoc_dspt_T_O      0x1             0x720e0000        >,
+				/bits/ 64  <mcput_snoc_sp0_I_O   snoc_dspt_T_O      0x2             0x5b000000        >,
+				/bits/ 64  <mcput_snoc_sp0_I_O   snoc_dspt_T_O      0x3             0x7b000000        >,
+				/bits/ 64  <mcput_snoc_sp0_I_O   snoc_lnoc_T_O      0x0             0x52080000        >,
+				/bits/ 64  <mcput_snoc_sp0_I_O   snoc_lnoc_T_O      0x1             0x72080000        >,
+				/bits/ 64  <mcput_snoc_sp0_I_O   snoc_mcput_d2d_T_O 0x0             0x58400000        >,
+				/bits/ 64  <mcput_snoc_sp0_I_O   snoc_mcput_d2d_T_O 0x1             0x78400000        >,
+				/bits/ 64  <mcput_snoc_sp0_I_O   snoc_mcput_d2d_T_O 0x2             0x58800000        >,
+				/bits/ 64  <mcput_snoc_sp0_I_O   snoc_mcput_d2d_T_O 0x3             0x78800000        >,
+				/bits/ 64  <mcput_snoc_sp0_I_O   snoc_mcput_d2d_T_O 0x4             0x59000000        >,
+				/bits/ 64  <mcput_snoc_sp0_I_O   snoc_mcput_d2d_T_O 0x5             0x5a000000        >,
+				/bits/ 64  <mcput_snoc_sp0_I_O   snoc_mcput_d2d_T_O 0x6             0x5b000000        >,
+				/bits/ 64  <mcput_snoc_sp0_I_O   snoc_mcput_d2d_T_O 0x7             0x79000000        >,
+				/bits/ 64  <mcput_snoc_sp0_I_O   snoc_mcput_d2d_T_O 0x8             0x7a000000        >,
+				/bits/ 64  <mcput_snoc_sp0_I_O   snoc_mcput_d2d_T_O 0x9             0x7b000000        >,
+				/bits/ 64  <mcput_snoc_sp0_I_O   snoc_mcput_d2d_T_O 0xa             0x50000000        >,
+				/bits/ 64  <mcput_snoc_sp0_I_O   snoc_mcput_d2d_T_O 0xb             0x70000000        >,
+				/bits/ 64  <mcput_snoc_sp0_I_O   snoc_mcput_d2d_T_O 0xc             0x40000000        >,
+				/bits/ 64  <mcput_snoc_sp0_I_O   snoc_mcput_d2d_T_O 0xd             0x60000000        >,
+				/bits/ 64  <mcput_snoc_sp0_I_O   snoc_mnoc_T_O      0x0             0x52020000        >,
+				/bits/ 64  <mcput_snoc_sp0_I_O   snoc_mnoc_T_O      0x1             0x72020000        >,
+				/bits/ 64  <mcput_snoc_sp0_I_O   snoc_npu_T_O       0x0             0x52080000        >,
+				/bits/ 64  <mcput_snoc_sp0_I_O   snoc_npu_T_O       0x1             0x72080000        >,
+				/bits/ 64  <mcput_snoc_sp0_I_O   snoc_npu_T_O       0x2             0x59000000        >,
+				/bits/ 64  <mcput_snoc_sp0_I_O   snoc_npu_T_O       0x3             0x5a000000        >,
+				/bits/ 64  <mcput_snoc_sp0_I_O   snoc_npu_T_O       0x4             0x79000000        >,
+				/bits/ 64  <mcput_snoc_sp0_I_O   snoc_npu_T_O       0x5             0x7a000000        >,
+				/bits/ 64  <mcput_snoc_sp0_I_O   snoc_pciet_T_O     0x0             0x40000000        >,
+				/bits/ 64  <mcput_snoc_sp0_I_O   snoc_pciet_T_O     0x1             0x60000000        >,
+				/bits/ 64  <mcput_snoc_sp0_I_O   snoc_rnoc_T_O      0x0             0x52040000        >,
+				/bits/ 64  <mcput_snoc_sp0_I_O   snoc_rnoc_T_O      0x1             0x72040000        >,
+				/bits/ 64  <mcput_snoc_sp0_I_O   snoc_service_T_O   0x0             0x52000000        >,
+				/bits/ 64  <mcput_snoc_sp0_I_O   snoc_service_T_O   0x1             0x72000000        >,
+				/bits/ 64  <mcput_snoc_sp1_I_O   snoc_aon_T_O       0x0             0x520c0000        >,
+				/bits/ 64  <mcput_snoc_sp1_I_O   snoc_aon_T_O       0x1             0x720c0000        >,
+				/bits/ 64  <mcput_snoc_sp1_I_O   snoc_aon_T_O       0x2             0x58400000        >,
+				/bits/ 64  <mcput_snoc_sp1_I_O   snoc_aon_T_O       0x3             0x78400000        >,
+				/bits/ 64  <mcput_snoc_sp1_I_O   snoc_aon_T_O       0x4             0x14000400000     >,
+				/bits/ 64  <mcput_snoc_sp1_I_O   snoc_aon_T_O       0x5             0x14008400000     >,
+				/bits/ 64  <mcput_snoc_sp1_I_O   snoc_aon_T_O       0x6             0x58800000        >,
+				/bits/ 64  <mcput_snoc_sp1_I_O   snoc_aon_T_O       0x7             0x78800000        >,
+				/bits/ 64  <mcput_snoc_sp1_I_O   snoc_aon_T_O       0x8             0x14000800000     >,
+				/bits/ 64  <mcput_snoc_sp1_I_O   snoc_aon_T_O       0x9             0x14008800000     >,
+				/bits/ 64  <mcput_snoc_sp1_I_O   snoc_aon_T_O       0xa             0x5c000000        >,
+				/bits/ 64  <mcput_snoc_sp1_I_O   snoc_aon_T_O       0xb             0x7c000000        >,
+				/bits/ 64  <mcput_snoc_sp1_I_O   snoc_aon_T_O       0xc             0x14004000000     >,
+				/bits/ 64  <mcput_snoc_sp1_I_O   snoc_aon_T_O       0xd             0x1400c000000     >,
+				/bits/ 64  <mcput_snoc_sp1_I_O   snoc_aon_T_O       0xe             0x0               >,
+				/bits/ 64  <mcput_snoc_sp1_I_O   snoc_aon_T_O       0xf             0x0               >,
+				/bits/ 64  <mcput_snoc_sp1_I_O   snoc_ddrt0_p2_T_O  0x0             0x80000000        >,
+				/bits/ 64  <mcput_snoc_sp1_I_O   snoc_ddrt0_p2_T_O  0x1             0x100000000       >,
+				/bits/ 64  <mcput_snoc_sp1_I_O   snoc_ddrt0_p2_T_O  0x2             0x200000000       >,
+				/bits/ 64  <mcput_snoc_sp1_I_O   snoc_ddrt0_p2_T_O  0x3             0x400000000       >,
+				/bits/ 64  <mcput_snoc_sp1_I_O   snoc_ddrt0_p2_T_O  0x4             0x800000000       >,
+				/bits/ 64  <mcput_snoc_sp1_I_O   snoc_ddrt0_p2_T_O  0x5             0x2000000000      >,
+				/bits/ 64  <mcput_snoc_sp1_I_O   snoc_ddrt0_p2_T_O  0x6             0xc000000000      >,
+				/bits/ 64  <mcput_snoc_sp1_I_O   snoc_ddrt0_p2_T_O  0x7             0xe000000000      >,
+				/bits/ 64  <mcput_snoc_sp1_I_O   snoc_ddrt0_p2_T_O  0x8             0x4000000000      >,
+				/bits/ 64  <mcput_snoc_sp1_I_O   snoc_ddrt0_p2_T_O  0x9             0x4000000100      >,
+				/bits/ 64  <mcput_snoc_sp1_I_O   snoc_ddrt0_p2_T_O  0xa             0x10000000000     >,
+				/bits/ 64  <mcput_snoc_sp1_I_O   snoc_ddrt0_p2_T_O  0xb             0x10000000100     >,
+				/bits/ 64  <mcput_snoc_sp1_I_O   snoc_ddrt1_p2_T_O  0x0             0x80000080        >,
+				/bits/ 64  <mcput_snoc_sp1_I_O   snoc_ddrt1_p2_T_O  0x1             0x100000080       >,
+				/bits/ 64  <mcput_snoc_sp1_I_O   snoc_ddrt1_p2_T_O  0x2             0x200000080       >,
+				/bits/ 64  <mcput_snoc_sp1_I_O   snoc_ddrt1_p2_T_O  0x3             0x400000080       >,
+				/bits/ 64  <mcput_snoc_sp1_I_O   snoc_ddrt1_p2_T_O  0x4             0x800000080       >,
+				/bits/ 64  <mcput_snoc_sp1_I_O   snoc_ddrt1_p2_T_O  0x5             0x2000000080      >,
+				/bits/ 64  <mcput_snoc_sp1_I_O   snoc_ddrt1_p2_T_O  0x6             0xc000000080      >,
+				/bits/ 64  <mcput_snoc_sp1_I_O   snoc_ddrt1_p2_T_O  0x7             0xe000000080      >,
+				/bits/ 64  <mcput_snoc_sp1_I_O   snoc_ddrt1_p2_T_O  0x8             0x4000000080      >,
+				/bits/ 64  <mcput_snoc_sp1_I_O   snoc_ddrt1_p2_T_O  0x9             0x4000000180      >,
+				/bits/ 64  <mcput_snoc_sp1_I_O   snoc_ddrt1_p2_T_O  0xa             0x10000000080     >,
+				/bits/ 64  <mcput_snoc_sp1_I_O   snoc_ddrt1_p2_T_O  0xb             0x10000000180     >,
+				/bits/ 64  <mcput_snoc_sp1_I_O   snoc_dspt_T_O      0x0             0x520e0000        >,
+				/bits/ 64  <mcput_snoc_sp1_I_O   snoc_dspt_T_O      0x1             0x720e0000        >,
+				/bits/ 64  <mcput_snoc_sp1_I_O   snoc_dspt_T_O      0x2             0x5b000000        >,
+				/bits/ 64  <mcput_snoc_sp1_I_O   snoc_dspt_T_O      0x3             0x7b000000        >,
+				/bits/ 64  <mcput_snoc_sp1_I_O   snoc_dspt_T_O      0x4             0x14003000000     >,
+				/bits/ 64  <mcput_snoc_sp1_I_O   snoc_dspt_T_O      0x5             0x1400b000000     >,
+				/bits/ 64  <mcput_snoc_sp1_I_O   snoc_mcput_d2d_T_O 0x0             0x58400000        >,
+				/bits/ 64  <mcput_snoc_sp1_I_O   snoc_mcput_d2d_T_O 0x1             0x78400000        >,
+				/bits/ 64  <mcput_snoc_sp1_I_O   snoc_mcput_d2d_T_O 0x2             0x14000400000     >,
+				/bits/ 64  <mcput_snoc_sp1_I_O   snoc_mcput_d2d_T_O 0x3             0x14008400000     >,
+				/bits/ 64  <mcput_snoc_sp1_I_O   snoc_mcput_d2d_T_O 0x4             0x58800000        >,
+				/bits/ 64  <mcput_snoc_sp1_I_O   snoc_mcput_d2d_T_O 0x5             0x78800000        >,
+				/bits/ 64  <mcput_snoc_sp1_I_O   snoc_mcput_d2d_T_O 0x6             0x14000800000     >,
+				/bits/ 64  <mcput_snoc_sp1_I_O   snoc_mcput_d2d_T_O 0x7             0x14008800000     >,
+				/bits/ 64  <mcput_snoc_sp1_I_O   snoc_mcput_d2d_T_O 0x8             0x59000000        >,
+				/bits/ 64  <mcput_snoc_sp1_I_O   snoc_mcput_d2d_T_O 0x9             0x5a000000        >,
+				/bits/ 64  <mcput_snoc_sp1_I_O   snoc_mcput_d2d_T_O 0xa             0x5b000000        >,
+				/bits/ 64  <mcput_snoc_sp1_I_O   snoc_mcput_d2d_T_O 0xb             0x79000000        >,
+				/bits/ 64  <mcput_snoc_sp1_I_O   snoc_mcput_d2d_T_O 0xc             0x7a000000        >,
+				/bits/ 64  <mcput_snoc_sp1_I_O   snoc_mcput_d2d_T_O 0xd             0x7b000000        >,
+				/bits/ 64  <mcput_snoc_sp1_I_O   snoc_mcput_d2d_T_O 0xe             0x14001000000     >,
+				/bits/ 64  <mcput_snoc_sp1_I_O   snoc_mcput_d2d_T_O 0xf             0x14002000000     >,
+				/bits/ 64  <mcput_snoc_sp1_I_O   snoc_mcput_d2d_T_O 0x10            0x14003000000     >,
+				/bits/ 64  <mcput_snoc_sp1_I_O   snoc_mcput_d2d_T_O 0x11            0x14009000000     >,
+				/bits/ 64  <mcput_snoc_sp1_I_O   snoc_mcput_d2d_T_O 0x12            0x1400a000000     >,
+				/bits/ 64  <mcput_snoc_sp1_I_O   snoc_mcput_d2d_T_O 0x13            0x1400b000000     >,
+				/bits/ 64  <mcput_snoc_sp1_I_O   snoc_mcput_d2d_T_O 0x14            0x50000000        >,
+				/bits/ 64  <mcput_snoc_sp1_I_O   snoc_mcput_d2d_T_O 0x15            0x70000000        >,
+				/bits/ 64  <mcput_snoc_sp1_I_O   snoc_mcput_d2d_T_O 0x16            0x40000000        >,
+				/bits/ 64  <mcput_snoc_sp1_I_O   snoc_mcput_d2d_T_O 0x17            0x60000000        >,
+				/bits/ 64  <mcput_snoc_sp1_I_O   snoc_mcput_d2d_T_O 0x18            0x80000000        >,
+				/bits/ 64  <mcput_snoc_sp1_I_O   snoc_mcput_d2d_T_O 0x19            0x100000000       >,
+				/bits/ 64  <mcput_snoc_sp1_I_O   snoc_mcput_d2d_T_O 0x1a            0x200000000       >,
+				/bits/ 64  <mcput_snoc_sp1_I_O   snoc_mcput_d2d_T_O 0x1b            0x400000000       >,
+				/bits/ 64  <mcput_snoc_sp1_I_O   snoc_mcput_d2d_T_O 0x1c            0x800000000       >,
+				/bits/ 64  <mcput_snoc_sp1_I_O   snoc_mcput_d2d_T_O 0x1d            0x1800000000      >,
+				/bits/ 64  <mcput_snoc_sp1_I_O   snoc_mcput_d2d_T_O 0x1e            0x3800000000      >,
+				/bits/ 64  <mcput_snoc_sp1_I_O   snoc_mcput_d2d_T_O 0x1f            0xd800000000      >,
+				/bits/ 64  <mcput_snoc_sp1_I_O   snoc_mcput_d2d_T_O 0x20            0xf800000000      >,
+				/bits/ 64  <mcput_snoc_sp1_I_O   snoc_mcput_d2d_T_O 0x21            0x2000000000      >,
+				/bits/ 64  <mcput_snoc_sp1_I_O   snoc_mcput_d2d_T_O 0x22            0x7000000000      >,
+				/bits/ 64  <mcput_snoc_sp1_I_O   snoc_mcput_d2d_T_O 0x23            0x7000000100      >,
+				/bits/ 64  <mcput_snoc_sp1_I_O   snoc_mcput_d2d_T_O 0x24            0xc000000000      >,
+				/bits/ 64  <mcput_snoc_sp1_I_O   snoc_mcput_d2d_T_O 0x25            0xe000000000      >,
+				/bits/ 64  <mcput_snoc_sp1_I_O   snoc_mcput_d2d_T_O 0x26            0x13000000000     >,
+				/bits/ 64  <mcput_snoc_sp1_I_O   snoc_mcput_d2d_T_O 0x27            0x13000000100     >,
+				/bits/ 64  <mcput_snoc_sp1_I_O   snoc_mcput_d2d_T_O 0x28            0x4000000000      >,
+				/bits/ 64  <mcput_snoc_sp1_I_O   snoc_mcput_d2d_T_O 0x29            0x4000000100      >,
+				/bits/ 64  <mcput_snoc_sp1_I_O   snoc_mcput_d2d_T_O 0x2a            0x8000000000      >,
+				/bits/ 64  <mcput_snoc_sp1_I_O   snoc_mcput_d2d_T_O 0x2b            0xa000000000      >,
+				/bits/ 64  <mcput_snoc_sp1_I_O   snoc_mcput_d2d_T_O 0x2c            0x10000000000     >,
+				/bits/ 64  <mcput_snoc_sp1_I_O   snoc_mcput_d2d_T_O 0x2d            0x10000000100     >,
+				/bits/ 64  <mcput_snoc_sp1_I_O   snoc_npu_T_O       0x0             0x52080000        >,
+				/bits/ 64  <mcput_snoc_sp1_I_O   snoc_npu_T_O       0x1             0x72080000        >,
+				/bits/ 64  <mcput_snoc_sp1_I_O   snoc_npu_T_O       0x2             0x59000000        >,
+				/bits/ 64  <mcput_snoc_sp1_I_O   snoc_npu_T_O       0x3             0x5a000000        >,
+				/bits/ 64  <mcput_snoc_sp1_I_O   snoc_npu_T_O       0x4             0x79000000        >,
+				/bits/ 64  <mcput_snoc_sp1_I_O   snoc_npu_T_O       0x5             0x7a000000        >,
+				/bits/ 64  <mcput_snoc_sp1_I_O   snoc_npu_T_O       0x6             0x14001000000     >,
+				/bits/ 64  <mcput_snoc_sp1_I_O   snoc_npu_T_O       0x7             0x14002000000     >,
+				/bits/ 64  <mcput_snoc_sp1_I_O   snoc_npu_T_O       0x8             0x14009000000     >,
+				/bits/ 64  <mcput_snoc_sp1_I_O   snoc_npu_T_O       0x9             0x1400a000000     >,
+				/bits/ 64  <mcput_snoc_sp1_I_O   snoc_npu_T_O       0xa             0x1800000000      >,
+				/bits/ 64  <mcput_snoc_sp1_I_O   snoc_npu_T_O       0xb             0x3800000000      >,
+				/bits/ 64  <mcput_snoc_sp1_I_O   snoc_npu_T_O       0xc             0xd800000000      >,
+				/bits/ 64  <mcput_snoc_sp1_I_O   snoc_npu_T_O       0xd             0xf800000000      >,
+				/bits/ 64  <mcput_snoc_sp1_I_O   snoc_npu_T_O       0xe             0x7000000000      >,
+				/bits/ 64  <mcput_snoc_sp1_I_O   snoc_npu_T_O       0xf             0x7000000100      >,
+				/bits/ 64  <mcput_snoc_sp1_I_O   snoc_npu_T_O       0x10            0x13000000000     >,
+				/bits/ 64  <mcput_snoc_sp1_I_O   snoc_npu_T_O       0x11            0x13000000100     >,
+				/bits/ 64  <mcput_snoc_sp1_I_O   snoc_pciet_T_O     0x0             0x40000000        >,
+				/bits/ 64  <mcput_snoc_sp1_I_O   snoc_pciet_T_O     0x1             0x60000000        >,
+				/bits/ 64  <mcput_snoc_sp1_I_O   snoc_pciet_T_O     0x2             0x8000000000      >,
+				/bits/ 64  <mcput_snoc_sp1_I_O   snoc_pciet_T_O     0x3             0xa000000000      >,
+				/bits/ 64  <mnoc_snoc_I_O        snoc_cnoc_T_O      0x0             0x52060000        >,
+				/bits/ 64  <mnoc_snoc_I_O        snoc_cnoc_T_O      0x1             0x72060000        >,
+				/bits/ 64  <mnoc_snoc_I_O        snoc_cnoc_T_O      0x2             0x52100000        >,
+				/bits/ 64  <mnoc_snoc_I_O        snoc_cnoc_T_O      0x3             0x52200000        >,
+				/bits/ 64  <mnoc_snoc_I_O        snoc_cnoc_T_O      0x4             0x52300000        >,
+				/bits/ 64  <mnoc_snoc_I_O        snoc_cnoc_T_O      0x5             0x72100000        >,
+				/bits/ 64  <mnoc_snoc_I_O        snoc_cnoc_T_O      0x6             0x72200000        >,
+				/bits/ 64  <mnoc_snoc_I_O        snoc_cnoc_T_O      0x7             0x72300000        >,
+				/bits/ 64  <mnoc_snoc_I_O        snoc_cnoc_T_O      0x8             0x53000000        >,
+				/bits/ 64  <mnoc_snoc_I_O        snoc_cnoc_T_O      0x9             0x73000000        >,
+				/bits/ 64  <mnoc_snoc_I_O        snoc_cnoc_T_O      0xa             0x50000000        >,
+				/bits/ 64  <mnoc_snoc_I_O        snoc_cnoc_T_O      0xb             0x70000000        >,
+				/bits/ 64  <mnoc_snoc_I_O        snoc_cnoc_T_O      0xc             0x54000000        >,
+				/bits/ 64  <mnoc_snoc_I_O        snoc_cnoc_T_O      0xd             0x74000000        >,
+				/bits/ 64  <mnoc_snoc_I_O        snoc_cnoc_T_O      0xe             0x0               >,
+				/bits/ 64  <mnoc_snoc_I_O        snoc_dspt_T_O      0x0             0x520e0000        >,
+				/bits/ 64  <mnoc_snoc_I_O        snoc_dspt_T_O      0x1             0x720e0000        >,
+				/bits/ 64  <mnoc_snoc_I_O        snoc_dspt_T_O      0x2             0x5b000000        >,
+				/bits/ 64  <mnoc_snoc_I_O        snoc_dspt_T_O      0x3             0x7b000000        >,
+				/bits/ 64  <mnoc_snoc_I_O        snoc_dspt_T_O      0x4             0x14003000000     >,
+				/bits/ 64  <mnoc_snoc_I_O        snoc_dspt_T_O      0x5             0x1400b000000     >,
+				/bits/ 64  <mnoc_snoc_I_O        snoc_mcput_d2d_T_O 0x0             0x58400000        >,
+				/bits/ 64  <mnoc_snoc_I_O        snoc_mcput_d2d_T_O 0x1             0x78400000        >,
+				/bits/ 64  <mnoc_snoc_I_O        snoc_mcput_d2d_T_O 0x2             0x14000400000     >,
+				/bits/ 64  <mnoc_snoc_I_O        snoc_mcput_d2d_T_O 0x3             0x14008400000     >,
+				/bits/ 64  <mnoc_snoc_I_O        snoc_mcput_d2d_T_O 0x4             0x58800000        >,
+				/bits/ 64  <mnoc_snoc_I_O        snoc_mcput_d2d_T_O 0x5             0x78800000        >,
+				/bits/ 64  <mnoc_snoc_I_O        snoc_mcput_d2d_T_O 0x6             0x14000800000     >,
+				/bits/ 64  <mnoc_snoc_I_O        snoc_mcput_d2d_T_O 0x7             0x14008800000     >,
+				/bits/ 64  <mnoc_snoc_I_O        snoc_mcput_d2d_T_O 0x8             0x59000000        >,
+				/bits/ 64  <mnoc_snoc_I_O        snoc_mcput_d2d_T_O 0x9             0x5a000000        >,
+				/bits/ 64  <mnoc_snoc_I_O        snoc_mcput_d2d_T_O 0xa             0x5b000000        >,
+				/bits/ 64  <mnoc_snoc_I_O        snoc_mcput_d2d_T_O 0xb             0x79000000        >,
+				/bits/ 64  <mnoc_snoc_I_O        snoc_mcput_d2d_T_O 0xc             0x7a000000        >,
+				/bits/ 64  <mnoc_snoc_I_O        snoc_mcput_d2d_T_O 0xd             0x7b000000        >,
+				/bits/ 64  <mnoc_snoc_I_O        snoc_mcput_d2d_T_O 0xe             0x14001000000     >,
+				/bits/ 64  <mnoc_snoc_I_O        snoc_mcput_d2d_T_O 0xf             0x14002000000     >,
+				/bits/ 64  <mnoc_snoc_I_O        snoc_mcput_d2d_T_O 0x10            0x14003000000     >,
+				/bits/ 64  <mnoc_snoc_I_O        snoc_mcput_d2d_T_O 0x11            0x14009000000     >,
+				/bits/ 64  <mnoc_snoc_I_O        snoc_mcput_d2d_T_O 0x12            0x1400a000000     >,
+				/bits/ 64  <mnoc_snoc_I_O        snoc_mcput_d2d_T_O 0x13            0x1400b000000     >,
+				/bits/ 64  <mnoc_snoc_I_O        snoc_mcput_d2d_T_O 0x14            0x50000000        >,
+				/bits/ 64  <mnoc_snoc_I_O        snoc_mcput_d2d_T_O 0x15            0x70000000        >,
+				/bits/ 64  <mnoc_snoc_I_O        snoc_mcput_d2d_T_O 0x16            0x40000000        >,
+				/bits/ 64  <mnoc_snoc_I_O        snoc_mcput_d2d_T_O 0x17            0x60000000        >,
+				/bits/ 64  <mnoc_snoc_I_O        snoc_mcput_d2d_T_O 0x18            0x80000000        >,
+				/bits/ 64  <mnoc_snoc_I_O        snoc_mcput_d2d_T_O 0x19            0x100000000       >,
+				/bits/ 64  <mnoc_snoc_I_O        snoc_mcput_d2d_T_O 0x1a            0x200000000       >,
+				/bits/ 64  <mnoc_snoc_I_O        snoc_mcput_d2d_T_O 0x1b            0x400000000       >,
+				/bits/ 64  <mnoc_snoc_I_O        snoc_mcput_d2d_T_O 0x1c            0x800000000       >,
+				/bits/ 64  <mnoc_snoc_I_O        snoc_mcput_d2d_T_O 0x1d            0x1800000000      >,
+				/bits/ 64  <mnoc_snoc_I_O        snoc_mcput_d2d_T_O 0x1e            0x3800000000      >,
+				/bits/ 64  <mnoc_snoc_I_O        snoc_mcput_d2d_T_O 0x1f            0xd800000000      >,
+				/bits/ 64  <mnoc_snoc_I_O        snoc_mcput_d2d_T_O 0x20            0xf800000000      >,
+				/bits/ 64  <mnoc_snoc_I_O        snoc_mcput_d2d_T_O 0x21            0x2000000000      >,
+				/bits/ 64  <mnoc_snoc_I_O        snoc_mcput_d2d_T_O 0x22            0x7000000000      >,
+				/bits/ 64  <mnoc_snoc_I_O        snoc_mcput_d2d_T_O 0x23            0x7000000100      >,
+				/bits/ 64  <mnoc_snoc_I_O        snoc_mcput_d2d_T_O 0x24            0xc000000000      >,
+				/bits/ 64  <mnoc_snoc_I_O        snoc_mcput_d2d_T_O 0x25            0xe000000000      >,
+				/bits/ 64  <mnoc_snoc_I_O        snoc_mcput_d2d_T_O 0x26            0x13000000000     >,
+				/bits/ 64  <mnoc_snoc_I_O        snoc_mcput_d2d_T_O 0x27            0x13000000100     >,
+				/bits/ 64  <mnoc_snoc_I_O        snoc_mcput_d2d_T_O 0x28            0x4000000000      >,
+				/bits/ 64  <mnoc_snoc_I_O        snoc_mcput_d2d_T_O 0x29            0x4000000100      >,
+				/bits/ 64  <mnoc_snoc_I_O        snoc_mcput_d2d_T_O 0x2a            0x8000000000      >,
+				/bits/ 64  <mnoc_snoc_I_O        snoc_mcput_d2d_T_O 0x2b            0xa000000000      >,
+				/bits/ 64  <mnoc_snoc_I_O        snoc_mcput_d2d_T_O 0x2c            0x10000000000     >,
+				/bits/ 64  <mnoc_snoc_I_O        snoc_mcput_d2d_T_O 0x2d            0x10000000100     >,
+				/bits/ 64  <mnoc_snoc_I_O        snoc_npu_T_O       0x0             0x52080000        >,
+				/bits/ 64  <mnoc_snoc_I_O        snoc_npu_T_O       0x1             0x72080000        >,
+				/bits/ 64  <mnoc_snoc_I_O        snoc_npu_T_O       0x2             0x59000000        >,
+				/bits/ 64  <mnoc_snoc_I_O        snoc_npu_T_O       0x3             0x5a000000        >,
+				/bits/ 64  <mnoc_snoc_I_O        snoc_npu_T_O       0x4             0x79000000        >,
+				/bits/ 64  <mnoc_snoc_I_O        snoc_npu_T_O       0x5             0x7a000000        >,
+				/bits/ 64  <mnoc_snoc_I_O        snoc_npu_T_O       0x6             0x14001000000     >,
+				/bits/ 64  <mnoc_snoc_I_O        snoc_npu_T_O       0x7             0x14002000000     >,
+				/bits/ 64  <mnoc_snoc_I_O        snoc_npu_T_O       0x8             0x14009000000     >,
+				/bits/ 64  <mnoc_snoc_I_O        snoc_npu_T_O       0x9             0x1400a000000     >,
+				/bits/ 64  <mnoc_snoc_I_O        snoc_npu_T_O       0xa             0x1800000000      >,
+				/bits/ 64  <mnoc_snoc_I_O        snoc_npu_T_O       0xb             0x3800000000      >,
+				/bits/ 64  <mnoc_snoc_I_O        snoc_npu_T_O       0xc             0xd800000000      >,
+				/bits/ 64  <mnoc_snoc_I_O        snoc_npu_T_O       0xd             0xf800000000      >,
+				/bits/ 64  <mnoc_snoc_I_O        snoc_npu_T_O       0xe             0x7000000000      >,
+				/bits/ 64  <mnoc_snoc_I_O        snoc_npu_T_O       0xf             0x7000000100      >,
+				/bits/ 64  <mnoc_snoc_I_O        snoc_npu_T_O       0x10            0x13000000000     >,
+				/bits/ 64  <mnoc_snoc_I_O        snoc_npu_T_O       0x11            0x13000000100     >,
+				/bits/ 64  <mnoc_snoc_I_O        snoc_pciet_T_O     0x0             0x40000000        >,
+				/bits/ 64  <mnoc_snoc_I_O        snoc_pciet_T_O     0x1             0x60000000        >,
+				/bits/ 64  <mnoc_snoc_I_O        snoc_pciet_T_O     0x2             0x8000000000      >,
+				/bits/ 64  <mnoc_snoc_I_O        snoc_pciet_T_O     0x3             0xa000000000      >,
+				/bits/ 64  <npu_snoc_sp0_I_O     snoc_aon_T_O       0x0             0x520c0000        >,
+				/bits/ 64  <npu_snoc_sp0_I_O     snoc_aon_T_O       0x1             0x720c0000        >,
+				/bits/ 64  <npu_snoc_sp0_I_O     snoc_aon_T_O       0x2             0x58400000        >,
+				/bits/ 64  <npu_snoc_sp0_I_O     snoc_aon_T_O       0x3             0x78400000        >,
+				/bits/ 64  <npu_snoc_sp0_I_O     snoc_aon_T_O       0x4             0x58800000        >,
+				/bits/ 64  <npu_snoc_sp0_I_O     snoc_aon_T_O       0x5             0x78800000        >,
+				/bits/ 64  <npu_snoc_sp0_I_O     snoc_aon_T_O       0x6             0x5c000000        >,
+				/bits/ 64  <npu_snoc_sp0_I_O     snoc_aon_T_O       0x7             0x7c000000        >,
+				/bits/ 64  <npu_snoc_sp0_I_O     snoc_cnoc_T_O      0x0             0x52060000        >,
+				/bits/ 64  <npu_snoc_sp0_I_O     snoc_cnoc_T_O      0x1             0x72060000        >,
+				/bits/ 64  <npu_snoc_sp0_I_O     snoc_cnoc_T_O      0x2             0x52100000        >,
+				/bits/ 64  <npu_snoc_sp0_I_O     snoc_cnoc_T_O      0x3             0x52200000        >,
+				/bits/ 64  <npu_snoc_sp0_I_O     snoc_cnoc_T_O      0x4             0x52300000        >,
+				/bits/ 64  <npu_snoc_sp0_I_O     snoc_cnoc_T_O      0x5             0x72100000        >,
+				/bits/ 64  <npu_snoc_sp0_I_O     snoc_cnoc_T_O      0x6             0x72200000        >,
+				/bits/ 64  <npu_snoc_sp0_I_O     snoc_cnoc_T_O      0x7             0x72300000        >,
+				/bits/ 64  <npu_snoc_sp0_I_O     snoc_cnoc_T_O      0x8             0x53000000        >,
+				/bits/ 64  <npu_snoc_sp0_I_O     snoc_cnoc_T_O      0x9             0x73000000        >,
+				/bits/ 64  <npu_snoc_sp0_I_O     snoc_cnoc_T_O      0xa             0x50000000        >,
+				/bits/ 64  <npu_snoc_sp0_I_O     snoc_cnoc_T_O      0xb             0x70000000        >,
+				/bits/ 64  <npu_snoc_sp0_I_O     snoc_cnoc_T_O      0xc             0x54000000        >,
+				/bits/ 64  <npu_snoc_sp0_I_O     snoc_cnoc_T_O      0xd             0x74000000        >,
+				/bits/ 64  <npu_snoc_sp0_I_O     snoc_cnoc_T_O      0xe             0x0               >,
+				/bits/ 64  <npu_snoc_sp0_I_O     snoc_cnoc_T_O      0xf             0x0               >,
+				/bits/ 64  <npu_snoc_sp0_I_O     snoc_cnoc_T_O      0x10            0x0               >,
+				/bits/ 64  <npu_snoc_sp0_I_O     snoc_dspt_T_O      0x0             0x520e0000        >,
+				/bits/ 64  <npu_snoc_sp0_I_O     snoc_dspt_T_O      0x1             0x720e0000        >,
+				/bits/ 64  <npu_snoc_sp0_I_O     snoc_dspt_T_O      0x2             0x5b000000        >,
+				/bits/ 64  <npu_snoc_sp0_I_O     snoc_dspt_T_O      0x3             0x7b000000        >,
+				/bits/ 64  <npu_snoc_sp0_I_O     snoc_lnoc_T_O      0x0             0x52080000        >,
+				/bits/ 64  <npu_snoc_sp0_I_O     snoc_lnoc_T_O      0x1             0x72080000        >,
+				/bits/ 64  <npu_snoc_sp0_I_O     snoc_mcput_d2d_T_O 0x0             0x58400000        >,
+				/bits/ 64  <npu_snoc_sp0_I_O     snoc_mcput_d2d_T_O 0x1             0x78400000        >,
+				/bits/ 64  <npu_snoc_sp0_I_O     snoc_mcput_d2d_T_O 0x2             0x58800000        >,
+				/bits/ 64  <npu_snoc_sp0_I_O     snoc_mcput_d2d_T_O 0x3             0x78800000        >,
+				/bits/ 64  <npu_snoc_sp0_I_O     snoc_mcput_d2d_T_O 0x4             0x59000000        >,
+				/bits/ 64  <npu_snoc_sp0_I_O     snoc_mcput_d2d_T_O 0x5             0x5a000000        >,
+				/bits/ 64  <npu_snoc_sp0_I_O     snoc_mcput_d2d_T_O 0x6             0x5b000000        >,
+				/bits/ 64  <npu_snoc_sp0_I_O     snoc_mcput_d2d_T_O 0x7             0x79000000        >,
+				/bits/ 64  <npu_snoc_sp0_I_O     snoc_mcput_d2d_T_O 0x8             0x7a000000        >,
+				/bits/ 64  <npu_snoc_sp0_I_O     snoc_mcput_d2d_T_O 0x9             0x7b000000        >,
+				/bits/ 64  <npu_snoc_sp0_I_O     snoc_mcput_d2d_T_O 0xa             0x50000000        >,
+				/bits/ 64  <npu_snoc_sp0_I_O     snoc_mcput_d2d_T_O 0xb             0x70000000        >,
+				/bits/ 64  <npu_snoc_sp0_I_O     snoc_mcput_d2d_T_O 0xc             0x40000000        >,
+				/bits/ 64  <npu_snoc_sp0_I_O     snoc_mcput_d2d_T_O 0xd             0x60000000        >,
+				/bits/ 64  <npu_snoc_sp0_I_O     snoc_mnoc_T_O      0x0             0x52020000        >,
+				/bits/ 64  <npu_snoc_sp0_I_O     snoc_mnoc_T_O      0x1             0x72020000        >,
+				/bits/ 64  <npu_snoc_sp0_I_O     snoc_pciet_T_O     0x0             0x40000000        >,
+				/bits/ 64  <npu_snoc_sp0_I_O     snoc_pciet_T_O     0x1             0x60000000        >,
+				/bits/ 64  <npu_snoc_sp0_I_O     snoc_rnoc_T_O      0x0             0x52040000        >,
+				/bits/ 64  <npu_snoc_sp0_I_O     snoc_rnoc_T_O      0x1             0x72040000        >,
+				/bits/ 64  <npu_snoc_sp0_I_O     snoc_service_T_O   0x0             0x52000000        >,
+				/bits/ 64  <npu_snoc_sp0_I_O     snoc_service_T_O   0x1             0x72000000        >,
+				/bits/ 64  <npu_snoc_sp1_I_O     snoc_aon_T_O       0x0             0x520c0000        >,
+				/bits/ 64  <npu_snoc_sp1_I_O     snoc_aon_T_O       0x1             0x720c0000        >,
+				/bits/ 64  <npu_snoc_sp1_I_O     snoc_aon_T_O       0x2             0x58400000        >,
+				/bits/ 64  <npu_snoc_sp1_I_O     snoc_aon_T_O       0x3             0x78400000        >,
+				/bits/ 64  <npu_snoc_sp1_I_O     snoc_aon_T_O       0x4             0x14000400000     >,
+				/bits/ 64  <npu_snoc_sp1_I_O     snoc_aon_T_O       0x5             0x14008400000     >,
+				/bits/ 64  <npu_snoc_sp1_I_O     snoc_aon_T_O       0x6             0x58800000        >,
+				/bits/ 64  <npu_snoc_sp1_I_O     snoc_aon_T_O       0x7             0x78800000        >,
+				/bits/ 64  <npu_snoc_sp1_I_O     snoc_aon_T_O       0x8             0x14000800000     >,
+				/bits/ 64  <npu_snoc_sp1_I_O     snoc_aon_T_O       0x9             0x14008800000     >,
+				/bits/ 64  <npu_snoc_sp1_I_O     snoc_aon_T_O       0xa             0x5c000000        >,
+				/bits/ 64  <npu_snoc_sp1_I_O     snoc_aon_T_O       0xb             0x7c000000        >,
+				/bits/ 64  <npu_snoc_sp1_I_O     snoc_aon_T_O       0xc             0x14004000000     >,
+				/bits/ 64  <npu_snoc_sp1_I_O     snoc_aon_T_O       0xd             0x1400c000000     >,
+				/bits/ 64  <npu_snoc_sp1_I_O     snoc_aon_T_O       0xe             0x0               >,
+				/bits/ 64  <npu_snoc_sp1_I_O     snoc_aon_T_O       0xf             0x0               >,
+				/bits/ 64  <npu_snoc_sp1_I_O     snoc_ddrt0_p2_T_O  0x0             0x80000000        >,
+				/bits/ 64  <npu_snoc_sp1_I_O     snoc_ddrt0_p2_T_O  0x1             0x100000000       >,
+				/bits/ 64  <npu_snoc_sp1_I_O     snoc_ddrt0_p2_T_O  0x2             0x200000000       >,
+				/bits/ 64  <npu_snoc_sp1_I_O     snoc_ddrt0_p2_T_O  0x3             0x400000000       >,
+				/bits/ 64  <npu_snoc_sp1_I_O     snoc_ddrt0_p2_T_O  0x4             0x800000000       >,
+				/bits/ 64  <npu_snoc_sp1_I_O     snoc_ddrt0_p2_T_O  0x5             0x2000000000      >,
+				/bits/ 64  <npu_snoc_sp1_I_O     snoc_ddrt0_p2_T_O  0x6             0xc000000000      >,
+				/bits/ 64  <npu_snoc_sp1_I_O     snoc_ddrt0_p2_T_O  0x7             0xe000000000      >,
+				/bits/ 64  <npu_snoc_sp1_I_O     snoc_ddrt0_p2_T_O  0x8             0x4000000000      >,
+				/bits/ 64  <npu_snoc_sp1_I_O     snoc_ddrt0_p2_T_O  0x9             0x4000000100      >,
+				/bits/ 64  <npu_snoc_sp1_I_O     snoc_ddrt0_p2_T_O  0xa             0x10000000000     >,
+				/bits/ 64  <npu_snoc_sp1_I_O     snoc_ddrt0_p2_T_O  0xb             0x10000000100     >,
+				/bits/ 64  <npu_snoc_sp1_I_O     snoc_ddrt1_p2_T_O  0x0             0x80000080        >,
+				/bits/ 64  <npu_snoc_sp1_I_O     snoc_ddrt1_p2_T_O  0x1             0x100000080       >,
+				/bits/ 64  <npu_snoc_sp1_I_O     snoc_ddrt1_p2_T_O  0x2             0x200000080       >,
+				/bits/ 64  <npu_snoc_sp1_I_O     snoc_ddrt1_p2_T_O  0x3             0x400000080       >,
+				/bits/ 64  <npu_snoc_sp1_I_O     snoc_ddrt1_p2_T_O  0x4             0x800000080       >,
+				/bits/ 64  <npu_snoc_sp1_I_O     snoc_ddrt1_p2_T_O  0x5             0x2000000080      >,
+				/bits/ 64  <npu_snoc_sp1_I_O     snoc_ddrt1_p2_T_O  0x6             0xc000000080      >,
+				/bits/ 64  <npu_snoc_sp1_I_O     snoc_ddrt1_p2_T_O  0x7             0xe000000080      >,
+				/bits/ 64  <npu_snoc_sp1_I_O     snoc_ddrt1_p2_T_O  0x8             0x4000000080      >,
+				/bits/ 64  <npu_snoc_sp1_I_O     snoc_ddrt1_p2_T_O  0x9             0x4000000180      >,
+				/bits/ 64  <npu_snoc_sp1_I_O     snoc_ddrt1_p2_T_O  0xa             0x10000000080     >,
+				/bits/ 64  <npu_snoc_sp1_I_O     snoc_ddrt1_p2_T_O  0xb             0x10000000180     >,
+				/bits/ 64  <npu_snoc_sp1_I_O     snoc_dspt_T_O      0x0             0x520e0000        >,
+				/bits/ 64  <npu_snoc_sp1_I_O     snoc_dspt_T_O      0x1             0x720e0000        >,
+				/bits/ 64  <npu_snoc_sp1_I_O     snoc_dspt_T_O      0x2             0x5b000000        >,
+				/bits/ 64  <npu_snoc_sp1_I_O     snoc_dspt_T_O      0x3             0x7b000000        >,
+				/bits/ 64  <npu_snoc_sp1_I_O     snoc_dspt_T_O      0x4             0x14003000000     >,
+				/bits/ 64  <npu_snoc_sp1_I_O     snoc_dspt_T_O      0x5             0x1400b000000     >,
+				/bits/ 64  <npu_snoc_sp1_I_O     snoc_mcput_d2d_T_O 0x0             0x58400000        >,
+				/bits/ 64  <npu_snoc_sp1_I_O     snoc_mcput_d2d_T_O 0x1             0x78400000        >,
+				/bits/ 64  <npu_snoc_sp1_I_O     snoc_mcput_d2d_T_O 0x2             0x14000400000     >,
+				/bits/ 64  <npu_snoc_sp1_I_O     snoc_mcput_d2d_T_O 0x3             0x14008400000     >,
+				/bits/ 64  <npu_snoc_sp1_I_O     snoc_mcput_d2d_T_O 0x4             0x58800000        >,
+				/bits/ 64  <npu_snoc_sp1_I_O     snoc_mcput_d2d_T_O 0x5             0x78800000        >,
+				/bits/ 64  <npu_snoc_sp1_I_O     snoc_mcput_d2d_T_O 0x6             0x14000800000     >,
+				/bits/ 64  <npu_snoc_sp1_I_O     snoc_mcput_d2d_T_O 0x7             0x14008800000     >,
+				/bits/ 64  <npu_snoc_sp1_I_O     snoc_mcput_d2d_T_O 0x8             0x59000000        >,
+				/bits/ 64  <npu_snoc_sp1_I_O     snoc_mcput_d2d_T_O 0x9             0x5a000000        >,
+				/bits/ 64  <npu_snoc_sp1_I_O     snoc_mcput_d2d_T_O 0xa             0x5b000000        >,
+				/bits/ 64  <npu_snoc_sp1_I_O     snoc_mcput_d2d_T_O 0xb             0x79000000        >,
+				/bits/ 64  <npu_snoc_sp1_I_O     snoc_mcput_d2d_T_O 0xc             0x7a000000        >,
+				/bits/ 64  <npu_snoc_sp1_I_O     snoc_mcput_d2d_T_O 0xd             0x7b000000        >,
+				/bits/ 64  <npu_snoc_sp1_I_O     snoc_mcput_d2d_T_O 0xe             0x14001000000     >,
+				/bits/ 64  <npu_snoc_sp1_I_O     snoc_mcput_d2d_T_O 0xf             0x14002000000     >,
+				/bits/ 64  <npu_snoc_sp1_I_O     snoc_mcput_d2d_T_O 0x10            0x14003000000     >,
+				/bits/ 64  <npu_snoc_sp1_I_O     snoc_mcput_d2d_T_O 0x11            0x14009000000     >,
+				/bits/ 64  <npu_snoc_sp1_I_O     snoc_mcput_d2d_T_O 0x12            0x1400a000000     >,
+				/bits/ 64  <npu_snoc_sp1_I_O     snoc_mcput_d2d_T_O 0x13            0x1400b000000     >,
+				/bits/ 64  <npu_snoc_sp1_I_O     snoc_mcput_d2d_T_O 0x14            0x50000000        >,
+				/bits/ 64  <npu_snoc_sp1_I_O     snoc_mcput_d2d_T_O 0x15            0x70000000        >,
+				/bits/ 64  <npu_snoc_sp1_I_O     snoc_mcput_d2d_T_O 0x16            0x40000000        >,
+				/bits/ 64  <npu_snoc_sp1_I_O     snoc_mcput_d2d_T_O 0x17            0x60000000        >,
+				/bits/ 64  <npu_snoc_sp1_I_O     snoc_mcput_d2d_T_O 0x18            0x80000000        >,
+				/bits/ 64  <npu_snoc_sp1_I_O     snoc_mcput_d2d_T_O 0x19            0x100000000       >,
+				/bits/ 64  <npu_snoc_sp1_I_O     snoc_mcput_d2d_T_O 0x1a            0x200000000       >,
+				/bits/ 64  <npu_snoc_sp1_I_O     snoc_mcput_d2d_T_O 0x1b            0x400000000       >,
+				/bits/ 64  <npu_snoc_sp1_I_O     snoc_mcput_d2d_T_O 0x1c            0x800000000       >,
+				/bits/ 64  <npu_snoc_sp1_I_O     snoc_mcput_d2d_T_O 0x1d            0x1800000000      >,
+				/bits/ 64  <npu_snoc_sp1_I_O     snoc_mcput_d2d_T_O 0x1e            0x3800000000      >,
+				/bits/ 64  <npu_snoc_sp1_I_O     snoc_mcput_d2d_T_O 0x1f            0xd800000000      >,
+				/bits/ 64  <npu_snoc_sp1_I_O     snoc_mcput_d2d_T_O 0x20            0xf800000000      >,
+				/bits/ 64  <npu_snoc_sp1_I_O     snoc_mcput_d2d_T_O 0x21            0x2000000000      >,
+				/bits/ 64  <npu_snoc_sp1_I_O     snoc_mcput_d2d_T_O 0x22            0x7000000000      >,
+				/bits/ 64  <npu_snoc_sp1_I_O     snoc_mcput_d2d_T_O 0x23            0x7000000100      >,
+				/bits/ 64  <npu_snoc_sp1_I_O     snoc_mcput_d2d_T_O 0x24            0xc000000000      >,
+				/bits/ 64  <npu_snoc_sp1_I_O     snoc_mcput_d2d_T_O 0x25            0xe000000000      >,
+				/bits/ 64  <npu_snoc_sp1_I_O     snoc_mcput_d2d_T_O 0x26            0x13000000000     >,
+				/bits/ 64  <npu_snoc_sp1_I_O     snoc_mcput_d2d_T_O 0x27            0x13000000100     >,
+				/bits/ 64  <npu_snoc_sp1_I_O     snoc_mcput_d2d_T_O 0x28            0x4000000000      >,
+				/bits/ 64  <npu_snoc_sp1_I_O     snoc_mcput_d2d_T_O 0x29            0x4000000100      >,
+				/bits/ 64  <npu_snoc_sp1_I_O     snoc_mcput_d2d_T_O 0x2a            0x8000000000      >,
+				/bits/ 64  <npu_snoc_sp1_I_O     snoc_mcput_d2d_T_O 0x2b            0xa000000000      >,
+				/bits/ 64  <npu_snoc_sp1_I_O     snoc_mcput_d2d_T_O 0x2c            0x10000000000     >,
+				/bits/ 64  <npu_snoc_sp1_I_O     snoc_mcput_d2d_T_O 0x2d            0x10000000100     >,
+				/bits/ 64  <npu_snoc_sp1_I_O     snoc_pciet_T_O     0x0             0x40000000        >,
+				/bits/ 64  <npu_snoc_sp1_I_O     snoc_pciet_T_O     0x1             0x60000000        >,
+				/bits/ 64  <npu_snoc_sp1_I_O     snoc_pciet_T_O     0x2             0x8000000000      >,
+				/bits/ 64  <npu_snoc_sp1_I_O     snoc_pciet_T_O     0x3             0xa000000000      >,
+				/bits/ 64  <pciet_snoc_p_I_O     snoc_cnoc_T_O      0x0             0x52060000        >,
+				/bits/ 64  <pciet_snoc_p_I_O     snoc_cnoc_T_O      0x1             0x72060000        >,
+				/bits/ 64  <pciet_snoc_p_I_O     snoc_cnoc_T_O      0x2             0x52100000        >,
+				/bits/ 64  <pciet_snoc_p_I_O     snoc_cnoc_T_O      0x3             0x52200000        >,
+				/bits/ 64  <pciet_snoc_p_I_O     snoc_cnoc_T_O      0x4             0x52300000        >,
+				/bits/ 64  <pciet_snoc_p_I_O     snoc_cnoc_T_O      0x5             0x72100000        >,
+				/bits/ 64  <pciet_snoc_p_I_O     snoc_cnoc_T_O      0x6             0x72200000        >,
+				/bits/ 64  <pciet_snoc_p_I_O     snoc_cnoc_T_O      0x7             0x72300000        >,
+				/bits/ 64  <pciet_snoc_p_I_O     snoc_cnoc_T_O      0x8             0x53000000        >,
+				/bits/ 64  <pciet_snoc_p_I_O     snoc_cnoc_T_O      0x9             0x73000000        >,
+				/bits/ 64  <pciet_snoc_p_I_O     snoc_cnoc_T_O      0xa             0x50000000        >,
+				/bits/ 64  <pciet_snoc_p_I_O     snoc_cnoc_T_O      0xb             0x70000000        >,
+				/bits/ 64  <pciet_snoc_p_I_O     snoc_cnoc_T_O      0xc             0x54000000        >,
+				/bits/ 64  <pciet_snoc_p_I_O     snoc_cnoc_T_O      0xd             0x74000000        >,
+				/bits/ 64  <pciet_snoc_p_I_O     snoc_cnoc_T_O      0xe             0x0               >,
+				/bits/ 64  <pciet_snoc_p_I_O     snoc_cnoc_T_O      0xf             0x0               >,
+				/bits/ 64  <pciet_snoc_p_I_O     snoc_cnoc_T_O      0x10            0x0               >,
+				/bits/ 64  <pciet_snoc_p_I_O     snoc_lnoc_T_O      0x0             0x52080000        >,
+				/bits/ 64  <pciet_snoc_p_I_O     snoc_lnoc_T_O      0x1             0x72080000        >,
+				/bits/ 64  <pciet_snoc_p_I_O     snoc_mnoc_T_O      0x0             0x52020000        >,
+				/bits/ 64  <pciet_snoc_p_I_O     snoc_mnoc_T_O      0x1             0x72020000        >,
+				/bits/ 64  <pciet_snoc_p_I_O     snoc_rnoc_T_O      0x0             0x52040000        >,
+				/bits/ 64  <pciet_snoc_p_I_O     snoc_rnoc_T_O      0x1             0x72040000        >,
+				/bits/ 64  <pciet_snoc_p_I_O     snoc_service_T_O   0x0             0x52000000        >,
+				/bits/ 64  <pciet_snoc_p_I_O     snoc_service_T_O   0x1             0x72000000        >,
+				/bits/ 64  <rnoc_snoc_I_O        snoc_npu_T_O       0x0             0x52080000        >,
+				/bits/ 64  <rnoc_snoc_I_O        snoc_npu_T_O       0x1             0x72080000        >,
+				/bits/ 64  <rnoc_snoc_I_O        snoc_npu_T_O       0x2             0x59000000        >,
+				/bits/ 64  <rnoc_snoc_I_O        snoc_npu_T_O       0x3             0x5a000000        >,
+				/bits/ 64  <rnoc_snoc_I_O        snoc_npu_T_O       0x4             0x79000000        >,
+				/bits/ 64  <rnoc_snoc_I_O        snoc_npu_T_O       0x5             0x7a000000        >,
+				/bits/ 64  <rnoc_snoc_I_O        snoc_npu_T_O       0x6             0x14001000000     >,
+				/bits/ 64  <rnoc_snoc_I_O        snoc_npu_T_O       0x7             0x14002000000     >,
+				/bits/ 64  <rnoc_snoc_I_O        snoc_npu_T_O       0x8             0x14009000000     >,
+				/bits/ 64  <rnoc_snoc_I_O        snoc_npu_T_O       0x9             0x1400a000000     >,
+				/bits/ 64  <rnoc_snoc_I_O        snoc_npu_T_O       0xa             0x1800000000      >,
+				/bits/ 64  <rnoc_snoc_I_O        snoc_npu_T_O       0xb             0x3800000000      >,
+				/bits/ 64  <rnoc_snoc_I_O        snoc_npu_T_O       0xc             0xd800000000      >,
+				/bits/ 64  <rnoc_snoc_I_O        snoc_npu_T_O       0xd             0xf800000000      >,
+				/bits/ 64  <rnoc_snoc_I_O        snoc_npu_T_O       0xe             0x7000000000      >,
+				/bits/ 64  <rnoc_snoc_I_O        snoc_npu_T_O       0xf             0x7000000100      >,
+				/bits/ 64  <rnoc_snoc_I_O        snoc_npu_T_O       0x10            0x13000000000     >,
+				/bits/ 64  <rnoc_snoc_I_O        snoc_npu_T_O       0x11            0x13000000100     >,
+				/bits/ 64  <rnoc_snoc_I_O        snoc_npu_T_O       0x12            0x0               >,
+				/bits/ 64  <rnoc_snoc_I_O        snoc_npu_T_O       0x13            0x0               >,
+				/bits/ 64  <spislv_tbu3_snoc_I_O snoc_aon_T_O       0x0             0x520c0000        >,
+				/bits/ 64  <spislv_tbu3_snoc_I_O snoc_aon_T_O       0x1             0x720c0000        >,
+				/bits/ 64  <spislv_tbu3_snoc_I_O snoc_aon_T_O       0x2             0x58400000        >,
+				/bits/ 64  <spislv_tbu3_snoc_I_O snoc_aon_T_O       0x3             0x78400000        >,
+				/bits/ 64  <spislv_tbu3_snoc_I_O snoc_aon_T_O       0x4             0x14000400000     >,
+				/bits/ 64  <spislv_tbu3_snoc_I_O snoc_aon_T_O       0x5             0x14008400000     >,
+				/bits/ 64  <spislv_tbu3_snoc_I_O snoc_aon_T_O       0x6             0x58800000        >,
+				/bits/ 64  <spislv_tbu3_snoc_I_O snoc_aon_T_O       0x7             0x78800000        >,
+				/bits/ 64  <spislv_tbu3_snoc_I_O snoc_aon_T_O       0x8             0x14000800000     >,
+				/bits/ 64  <spislv_tbu3_snoc_I_O snoc_aon_T_O       0x9             0x14008800000     >,
+				/bits/ 64  <spislv_tbu3_snoc_I_O snoc_aon_T_O       0xa             0x5c000000        >,
+				/bits/ 64  <spislv_tbu3_snoc_I_O snoc_aon_T_O       0xb             0x7c000000        >,
+				/bits/ 64  <spislv_tbu3_snoc_I_O snoc_aon_T_O       0xc             0x14004000000     >,
+				/bits/ 64  <spislv_tbu3_snoc_I_O snoc_aon_T_O       0xd             0x1400c000000     >,
+				/bits/ 64  <spislv_tbu3_snoc_I_O snoc_cnoc_T_O      0x0             0x52060000        >,
+				/bits/ 64  <spislv_tbu3_snoc_I_O snoc_cnoc_T_O      0x1             0x72060000        >,
+				/bits/ 64  <spislv_tbu3_snoc_I_O snoc_cnoc_T_O      0x2             0x52100000        >,
+				/bits/ 64  <spislv_tbu3_snoc_I_O snoc_cnoc_T_O      0x3             0x52200000        >,
+				/bits/ 64  <spislv_tbu3_snoc_I_O snoc_cnoc_T_O      0x4             0x52300000        >,
+				/bits/ 64  <spislv_tbu3_snoc_I_O snoc_cnoc_T_O      0x5             0x72100000        >,
+				/bits/ 64  <spislv_tbu3_snoc_I_O snoc_cnoc_T_O      0x6             0x72200000        >,
+				/bits/ 64  <spislv_tbu3_snoc_I_O snoc_cnoc_T_O      0x7             0x72300000        >,
+				/bits/ 64  <spislv_tbu3_snoc_I_O snoc_cnoc_T_O      0x8             0x53000000        >,
+				/bits/ 64  <spislv_tbu3_snoc_I_O snoc_cnoc_T_O      0x9             0x73000000        >,
+				/bits/ 64  <spislv_tbu3_snoc_I_O snoc_cnoc_T_O      0xa             0x50000000        >,
+				/bits/ 64  <spislv_tbu3_snoc_I_O snoc_cnoc_T_O      0xb             0x70000000        >,
+				/bits/ 64  <spislv_tbu3_snoc_I_O snoc_cnoc_T_O      0xc             0x54000000        >,
+				/bits/ 64  <spislv_tbu3_snoc_I_O snoc_cnoc_T_O      0xd             0x74000000        >,
+				/bits/ 64  <spislv_tbu3_snoc_I_O snoc_cnoc_T_O      0xe             0x0               >,
+				/bits/ 64  <spislv_tbu3_snoc_I_O snoc_ddrt0_p2_T_O  0x0             0x80000000        >,
+				/bits/ 64  <spislv_tbu3_snoc_I_O snoc_ddrt0_p2_T_O  0x1             0x100000000       >,
+				/bits/ 64  <spislv_tbu3_snoc_I_O snoc_ddrt0_p2_T_O  0x2             0x200000000       >,
+				/bits/ 64  <spislv_tbu3_snoc_I_O snoc_ddrt0_p2_T_O  0x3             0x400000000       >,
+				/bits/ 64  <spislv_tbu3_snoc_I_O snoc_ddrt0_p2_T_O  0x4             0x800000000       >,
+				/bits/ 64  <spislv_tbu3_snoc_I_O snoc_ddrt0_p2_T_O  0x5             0x2000000000      >,
+				/bits/ 64  <spislv_tbu3_snoc_I_O snoc_ddrt0_p2_T_O  0x6             0xc000000000      >,
+				/bits/ 64  <spislv_tbu3_snoc_I_O snoc_ddrt0_p2_T_O  0x7             0xe000000000      >,
+				/bits/ 64  <spislv_tbu3_snoc_I_O snoc_ddrt0_p2_T_O  0x8             0x4000000000      >,
+				/bits/ 64  <spislv_tbu3_snoc_I_O snoc_ddrt0_p2_T_O  0x9             0x4000000100      >,
+				/bits/ 64  <spislv_tbu3_snoc_I_O snoc_ddrt0_p2_T_O  0xa             0x10000000000     >,
+				/bits/ 64  <spislv_tbu3_snoc_I_O snoc_ddrt0_p2_T_O  0xb             0x10000000100     >,
+				/bits/ 64  <spislv_tbu3_snoc_I_O snoc_ddrt1_p2_T_O  0x0             0x80000080        >,
+				/bits/ 64  <spislv_tbu3_snoc_I_O snoc_ddrt1_p2_T_O  0x1             0x100000080       >,
+				/bits/ 64  <spislv_tbu3_snoc_I_O snoc_ddrt1_p2_T_O  0x2             0x200000080       >,
+				/bits/ 64  <spislv_tbu3_snoc_I_O snoc_ddrt1_p2_T_O  0x3             0x400000080       >,
+				/bits/ 64  <spislv_tbu3_snoc_I_O snoc_ddrt1_p2_T_O  0x4             0x800000080       >,
+				/bits/ 64  <spislv_tbu3_snoc_I_O snoc_ddrt1_p2_T_O  0x5             0x2000000080      >,
+				/bits/ 64  <spislv_tbu3_snoc_I_O snoc_ddrt1_p2_T_O  0x6             0xc000000080      >,
+				/bits/ 64  <spislv_tbu3_snoc_I_O snoc_ddrt1_p2_T_O  0x7             0xe000000080      >,
+				/bits/ 64  <spislv_tbu3_snoc_I_O snoc_ddrt1_p2_T_O  0x8             0x4000000080      >,
+				/bits/ 64  <spislv_tbu3_snoc_I_O snoc_ddrt1_p2_T_O  0x9             0x4000000180      >,
+				/bits/ 64  <spislv_tbu3_snoc_I_O snoc_ddrt1_p2_T_O  0xa             0x10000000080     >,
+				/bits/ 64  <spislv_tbu3_snoc_I_O snoc_ddrt1_p2_T_O  0xb             0x10000000180     >,
+				/bits/ 64  <spislv_tbu3_snoc_I_O snoc_dspt_T_O      0x0             0x520e0000        >,
+				/bits/ 64  <spislv_tbu3_snoc_I_O snoc_dspt_T_O      0x1             0x720e0000        >,
+				/bits/ 64  <spislv_tbu3_snoc_I_O snoc_dspt_T_O      0x2             0x5b000000        >,
+				/bits/ 64  <spislv_tbu3_snoc_I_O snoc_dspt_T_O      0x3             0x7b000000        >,
+				/bits/ 64  <spislv_tbu3_snoc_I_O snoc_dspt_T_O      0x4             0x14003000000     >,
+				/bits/ 64  <spislv_tbu3_snoc_I_O snoc_dspt_T_O      0x5             0x1400b000000     >,
+				/bits/ 64  <spislv_tbu3_snoc_I_O snoc_lnoc_T_O      0x0             0x52080000        >,
+				/bits/ 64  <spislv_tbu3_snoc_I_O snoc_lnoc_T_O      0x1             0x72080000        >,
+				/bits/ 64  <spislv_tbu3_snoc_I_O snoc_mcput_d2d_T_O 0x0             0x58400000        >,
+				/bits/ 64  <spislv_tbu3_snoc_I_O snoc_mcput_d2d_T_O 0x1             0x78400000        >,
+				/bits/ 64  <spislv_tbu3_snoc_I_O snoc_mcput_d2d_T_O 0x2             0x14000400000     >,
+				/bits/ 64  <spislv_tbu3_snoc_I_O snoc_mcput_d2d_T_O 0x3             0x14008400000     >,
+				/bits/ 64  <spislv_tbu3_snoc_I_O snoc_mcput_d2d_T_O 0x4             0x58800000        >,
+				/bits/ 64  <spislv_tbu3_snoc_I_O snoc_mcput_d2d_T_O 0x5             0x78800000        >,
+				/bits/ 64  <spislv_tbu3_snoc_I_O snoc_mcput_d2d_T_O 0x6             0x14000800000     >,
+				/bits/ 64  <spislv_tbu3_snoc_I_O snoc_mcput_d2d_T_O 0x7             0x14008800000     >,
+				/bits/ 64  <spislv_tbu3_snoc_I_O snoc_mcput_d2d_T_O 0x8             0x59000000        >,
+				/bits/ 64  <spislv_tbu3_snoc_I_O snoc_mcput_d2d_T_O 0x9             0x5a000000        >,
+				/bits/ 64  <spislv_tbu3_snoc_I_O snoc_mcput_d2d_T_O 0xa             0x5b000000        >,
+				/bits/ 64  <spislv_tbu3_snoc_I_O snoc_mcput_d2d_T_O 0xb             0x79000000        >,
+				/bits/ 64  <spislv_tbu3_snoc_I_O snoc_mcput_d2d_T_O 0xc             0x7a000000        >,
+				/bits/ 64  <spislv_tbu3_snoc_I_O snoc_mcput_d2d_T_O 0xd             0x7b000000        >,
+				/bits/ 64  <spislv_tbu3_snoc_I_O snoc_mcput_d2d_T_O 0xe             0x14001000000     >,
+				/bits/ 64  <spislv_tbu3_snoc_I_O snoc_mcput_d2d_T_O 0xf             0x14002000000     >,
+				/bits/ 64  <spislv_tbu3_snoc_I_O snoc_mcput_d2d_T_O 0x10            0x14003000000     >,
+				/bits/ 64  <spislv_tbu3_snoc_I_O snoc_mcput_d2d_T_O 0x11            0x14009000000     >,
+				/bits/ 64  <spislv_tbu3_snoc_I_O snoc_mcput_d2d_T_O 0x12            0x1400a000000     >,
+				/bits/ 64  <spislv_tbu3_snoc_I_O snoc_mcput_d2d_T_O 0x13            0x1400b000000     >,
+				/bits/ 64  <spislv_tbu3_snoc_I_O snoc_mcput_d2d_T_O 0x14            0x50000000        >,
+				/bits/ 64  <spislv_tbu3_snoc_I_O snoc_mcput_d2d_T_O 0x15            0x70000000        >,
+				/bits/ 64  <spislv_tbu3_snoc_I_O snoc_mcput_d2d_T_O 0x16            0x40000000        >,
+				/bits/ 64  <spislv_tbu3_snoc_I_O snoc_mcput_d2d_T_O 0x17            0x60000000        >,
+				/bits/ 64  <spislv_tbu3_snoc_I_O snoc_mcput_d2d_T_O 0x18            0x80000000        >,
+				/bits/ 64  <spislv_tbu3_snoc_I_O snoc_mcput_d2d_T_O 0x19            0x100000000       >,
+				/bits/ 64  <spislv_tbu3_snoc_I_O snoc_mcput_d2d_T_O 0x1a            0x200000000       >,
+				/bits/ 64  <spislv_tbu3_snoc_I_O snoc_mcput_d2d_T_O 0x1b            0x400000000       >,
+				/bits/ 64  <spislv_tbu3_snoc_I_O snoc_mcput_d2d_T_O 0x1c            0x800000000       >,
+				/bits/ 64  <spislv_tbu3_snoc_I_O snoc_mcput_d2d_T_O 0x1d            0x1800000000      >,
+				/bits/ 64  <spislv_tbu3_snoc_I_O snoc_mcput_d2d_T_O 0x1e            0x3800000000      >,
+				/bits/ 64  <spislv_tbu3_snoc_I_O snoc_mcput_d2d_T_O 0x1f            0xd800000000      >,
+				/bits/ 64  <spislv_tbu3_snoc_I_O snoc_mcput_d2d_T_O 0x20            0xf800000000      >,
+				/bits/ 64  <spislv_tbu3_snoc_I_O snoc_mcput_d2d_T_O 0x21            0x2000000000      >,
+				/bits/ 64  <spislv_tbu3_snoc_I_O snoc_mcput_d2d_T_O 0x22            0x7000000000      >,
+				/bits/ 64  <spislv_tbu3_snoc_I_O snoc_mcput_d2d_T_O 0x23            0x7000000100      >,
+				/bits/ 64  <spislv_tbu3_snoc_I_O snoc_mcput_d2d_T_O 0x24            0xc000000000      >,
+				/bits/ 64  <spislv_tbu3_snoc_I_O snoc_mcput_d2d_T_O 0x25            0xe000000000      >,
+				/bits/ 64  <spislv_tbu3_snoc_I_O snoc_mcput_d2d_T_O 0x26            0x13000000000     >,
+				/bits/ 64  <spislv_tbu3_snoc_I_O snoc_mcput_d2d_T_O 0x27            0x13000000100     >,
+				/bits/ 64  <spislv_tbu3_snoc_I_O snoc_mcput_d2d_T_O 0x28            0x4000000000      >,
+				/bits/ 64  <spislv_tbu3_snoc_I_O snoc_mcput_d2d_T_O 0x29            0x4000000100      >,
+				/bits/ 64  <spislv_tbu3_snoc_I_O snoc_mcput_d2d_T_O 0x2a            0x8000000000      >,
+				/bits/ 64  <spislv_tbu3_snoc_I_O snoc_mcput_d2d_T_O 0x2b            0xa000000000      >,
+				/bits/ 64  <spislv_tbu3_snoc_I_O snoc_mcput_d2d_T_O 0x2c            0x10000000000     >,
+				/bits/ 64  <spislv_tbu3_snoc_I_O snoc_mcput_d2d_T_O 0x2d            0x10000000100     >,
+				/bits/ 64  <spislv_tbu3_snoc_I_O snoc_mnoc_T_O      0x0             0x52020000        >,
+				/bits/ 64  <spislv_tbu3_snoc_I_O snoc_mnoc_T_O      0x1             0x72020000        >,
+				/bits/ 64  <spislv_tbu3_snoc_I_O snoc_npu_T_O       0x0             0x52080000        >,
+				/bits/ 64  <spislv_tbu3_snoc_I_O snoc_npu_T_O       0x1             0x72080000        >,
+				/bits/ 64  <spislv_tbu3_snoc_I_O snoc_npu_T_O       0x2             0x59000000        >,
+				/bits/ 64  <spislv_tbu3_snoc_I_O snoc_npu_T_O       0x3             0x5a000000        >,
+				/bits/ 64  <spislv_tbu3_snoc_I_O snoc_npu_T_O       0x4             0x79000000        >,
+				/bits/ 64  <spislv_tbu3_snoc_I_O snoc_npu_T_O       0x5             0x7a000000        >,
+				/bits/ 64  <spislv_tbu3_snoc_I_O snoc_npu_T_O       0x6             0x14001000000     >,
+				/bits/ 64  <spislv_tbu3_snoc_I_O snoc_npu_T_O       0x7             0x14002000000     >,
+				/bits/ 64  <spislv_tbu3_snoc_I_O snoc_npu_T_O       0x8             0x14009000000     >,
+				/bits/ 64  <spislv_tbu3_snoc_I_O snoc_npu_T_O       0x9             0x1400a000000     >,
+				/bits/ 64  <spislv_tbu3_snoc_I_O snoc_npu_T_O       0xa             0x1800000000      >,
+				/bits/ 64  <spislv_tbu3_snoc_I_O snoc_npu_T_O       0xb             0x3800000000      >,
+				/bits/ 64  <spislv_tbu3_snoc_I_O snoc_npu_T_O       0xc             0xd800000000      >,
+				/bits/ 64  <spislv_tbu3_snoc_I_O snoc_npu_T_O       0xd             0xf800000000      >,
+				/bits/ 64  <spislv_tbu3_snoc_I_O snoc_npu_T_O       0xe             0x7000000000      >,
+				/bits/ 64  <spislv_tbu3_snoc_I_O snoc_npu_T_O       0xf             0x7000000100      >,
+				/bits/ 64  <spislv_tbu3_snoc_I_O snoc_npu_T_O       0x10            0x13000000000     >,
+				/bits/ 64  <spislv_tbu3_snoc_I_O snoc_npu_T_O       0x11            0x13000000100     >,
+				/bits/ 64  <spislv_tbu3_snoc_I_O snoc_rnoc_T_O      0x0             0x52040000        >,
+				/bits/ 64  <spislv_tbu3_snoc_I_O snoc_rnoc_T_O      0x1             0x72040000        >,
+				/bits/ 64  <spislv_tbu3_snoc_I_O snoc_service_T_O   0x0             0x52000000        >,
+				/bits/ 64  <spislv_tbu3_snoc_I_O snoc_service_T_O   0x1             0x72000000        >,
+				/bits/ 64  <tbu4_snoc_I_O        snoc_ddrt0_p2_T_O  0x0             0x80000000        >,
+				/bits/ 64  <tbu4_snoc_I_O        snoc_ddrt0_p2_T_O  0x1             0x100000000       >,
+				/bits/ 64  <tbu4_snoc_I_O        snoc_ddrt0_p2_T_O  0x2             0x200000000       >,
+				/bits/ 64  <tbu4_snoc_I_O        snoc_ddrt0_p2_T_O  0x3             0x400000000       >,
+				/bits/ 64  <tbu4_snoc_I_O        snoc_ddrt0_p2_T_O  0x4             0x800000000       >,
+				/bits/ 64  <tbu4_snoc_I_O        snoc_ddrt0_p2_T_O  0x5             0x2000000000      >,
+				/bits/ 64  <tbu4_snoc_I_O        snoc_ddrt0_p2_T_O  0x6             0xc000000000      >,
+				/bits/ 64  <tbu4_snoc_I_O        snoc_ddrt0_p2_T_O  0x7             0xe000000000      >,
+				/bits/ 64  <tbu4_snoc_I_O        snoc_ddrt0_p2_T_O  0x8             0x4000000000      >,
+				/bits/ 64  <tbu4_snoc_I_O        snoc_ddrt0_p2_T_O  0x9             0x4000000100      >,
+				/bits/ 64  <tbu4_snoc_I_O        snoc_ddrt0_p2_T_O  0xa             0x10000000000     >,
+				/bits/ 64  <tbu4_snoc_I_O        snoc_ddrt0_p2_T_O  0xb             0x10000000100     >,
+				/bits/ 64  <tbu4_snoc_I_O        snoc_ddrt1_p2_T_O  0x0             0x80000080        >,
+				/bits/ 64  <tbu4_snoc_I_O        snoc_ddrt1_p2_T_O  0x1             0x100000080       >,
+				/bits/ 64  <tbu4_snoc_I_O        snoc_ddrt1_p2_T_O  0x2             0x200000080       >,
+				/bits/ 64  <tbu4_snoc_I_O        snoc_ddrt1_p2_T_O  0x3             0x400000080       >,
+				/bits/ 64  <tbu4_snoc_I_O        snoc_ddrt1_p2_T_O  0x4             0x800000080       >,
+				/bits/ 64  <tbu4_snoc_I_O        snoc_ddrt1_p2_T_O  0x5             0x2000000080      >,
+				/bits/ 64  <tbu4_snoc_I_O        snoc_ddrt1_p2_T_O  0x6             0xc000000080      >,
+				/bits/ 64  <tbu4_snoc_I_O        snoc_ddrt1_p2_T_O  0x7             0xe000000080      >,
+				/bits/ 64  <tbu4_snoc_I_O        snoc_ddrt1_p2_T_O  0x8             0x4000000080      >,
+				/bits/ 64  <tbu4_snoc_I_O        snoc_ddrt1_p2_T_O  0x9             0x4000000180      >,
+				/bits/ 64  <tbu4_snoc_I_O        snoc_ddrt1_p2_T_O  0xa             0x10000000080     >,
+				/bits/ 64  <tbu4_snoc_I_O        snoc_ddrt1_p2_T_O  0xb             0x10000000180     >,
+				/bits/ 64  <tbu4_snoc_I_O        snoc_dspt_T_O      0x0             0x520e0000        >,
+				/bits/ 64  <tbu4_snoc_I_O        snoc_dspt_T_O      0x1             0x720e0000        >,
+				/bits/ 64  <tbu4_snoc_I_O        snoc_dspt_T_O      0x2             0x5b000000        >,
+				/bits/ 64  <tbu4_snoc_I_O        snoc_dspt_T_O      0x3             0x7b000000        >,
+				/bits/ 64  <tbu4_snoc_I_O        snoc_dspt_T_O      0x4             0x14003000000     >,
+				/bits/ 64  <tbu4_snoc_I_O        snoc_dspt_T_O      0x5             0x1400b000000     >,
+				/bits/ 64  <tbu4_snoc_I_O        snoc_mcput_d2d_T_O 0x0             0x58400000        >,
+				/bits/ 64  <tbu4_snoc_I_O        snoc_mcput_d2d_T_O 0x1             0x78400000        >,
+				/bits/ 64  <tbu4_snoc_I_O        snoc_mcput_d2d_T_O 0x2             0x14000400000     >,
+				/bits/ 64  <tbu4_snoc_I_O        snoc_mcput_d2d_T_O 0x3             0x14008400000     >,
+				/bits/ 64  <tbu4_snoc_I_O        snoc_mcput_d2d_T_O 0x4             0x58800000        >,
+				/bits/ 64  <tbu4_snoc_I_O        snoc_mcput_d2d_T_O 0x5             0x78800000        >,
+				/bits/ 64  <tbu4_snoc_I_O        snoc_mcput_d2d_T_O 0x6             0x14000800000     >,
+				/bits/ 64  <tbu4_snoc_I_O        snoc_mcput_d2d_T_O 0x7             0x14008800000     >,
+				/bits/ 64  <tbu4_snoc_I_O        snoc_mcput_d2d_T_O 0x8             0x59000000        >,
+				/bits/ 64  <tbu4_snoc_I_O        snoc_mcput_d2d_T_O 0x9             0x5a000000        >,
+				/bits/ 64  <tbu4_snoc_I_O        snoc_mcput_d2d_T_O 0xa             0x5b000000        >,
+				/bits/ 64  <tbu4_snoc_I_O        snoc_mcput_d2d_T_O 0xb             0x79000000        >,
+				/bits/ 64  <tbu4_snoc_I_O        snoc_mcput_d2d_T_O 0xc             0x7a000000        >,
+				/bits/ 64  <tbu4_snoc_I_O        snoc_mcput_d2d_T_O 0xd             0x7b000000        >,
+				/bits/ 64  <tbu4_snoc_I_O        snoc_mcput_d2d_T_O 0xe             0x14001000000     >,
+				/bits/ 64  <tbu4_snoc_I_O        snoc_mcput_d2d_T_O 0xf             0x14002000000     >,
+				/bits/ 64  <tbu4_snoc_I_O        snoc_mcput_d2d_T_O 0x10            0x14003000000     >,
+				/bits/ 64  <tbu4_snoc_I_O        snoc_mcput_d2d_T_O 0x11            0x14009000000     >,
+				/bits/ 64  <tbu4_snoc_I_O        snoc_mcput_d2d_T_O 0x12            0x1400a000000     >,
+				/bits/ 64  <tbu4_snoc_I_O        snoc_mcput_d2d_T_O 0x13            0x1400b000000     >,
+				/bits/ 64  <tbu4_snoc_I_O        snoc_mcput_d2d_T_O 0x14            0x50000000        >,
+				/bits/ 64  <tbu4_snoc_I_O        snoc_mcput_d2d_T_O 0x15            0x70000000        >,
+				/bits/ 64  <tbu4_snoc_I_O        snoc_mcput_d2d_T_O 0x16            0x40000000        >,
+				/bits/ 64  <tbu4_snoc_I_O        snoc_mcput_d2d_T_O 0x17            0x60000000        >,
+				/bits/ 64  <tbu4_snoc_I_O        snoc_mcput_d2d_T_O 0x18            0x80000000        >,
+				/bits/ 64  <tbu4_snoc_I_O        snoc_mcput_d2d_T_O 0x19            0x100000000       >,
+				/bits/ 64  <tbu4_snoc_I_O        snoc_mcput_d2d_T_O 0x1a            0x200000000       >,
+				/bits/ 64  <tbu4_snoc_I_O        snoc_mcput_d2d_T_O 0x1b            0x400000000       >,
+				/bits/ 64  <tbu4_snoc_I_O        snoc_mcput_d2d_T_O 0x1c            0x800000000       >,
+				/bits/ 64  <tbu4_snoc_I_O        snoc_mcput_d2d_T_O 0x1d            0x1800000000      >,
+				/bits/ 64  <tbu4_snoc_I_O        snoc_mcput_d2d_T_O 0x1e            0x3800000000      >,
+				/bits/ 64  <tbu4_snoc_I_O        snoc_mcput_d2d_T_O 0x1f            0xd800000000      >,
+				/bits/ 64  <tbu4_snoc_I_O        snoc_mcput_d2d_T_O 0x20            0xf800000000      >,
+				/bits/ 64  <tbu4_snoc_I_O        snoc_mcput_d2d_T_O 0x21            0x2000000000      >,
+				/bits/ 64  <tbu4_snoc_I_O        snoc_mcput_d2d_T_O 0x22            0x7000000000      >,
+				/bits/ 64  <tbu4_snoc_I_O        snoc_mcput_d2d_T_O 0x23            0x7000000100      >,
+				/bits/ 64  <tbu4_snoc_I_O        snoc_mcput_d2d_T_O 0x24            0xc000000000      >,
+				/bits/ 64  <tbu4_snoc_I_O        snoc_mcput_d2d_T_O 0x25            0xe000000000      >,
+				/bits/ 64  <tbu4_snoc_I_O        snoc_mcput_d2d_T_O 0x26            0x13000000000     >,
+				/bits/ 64  <tbu4_snoc_I_O        snoc_mcput_d2d_T_O 0x27            0x13000000100     >,
+				/bits/ 64  <tbu4_snoc_I_O        snoc_mcput_d2d_T_O 0x28            0x4000000000      >,
+				/bits/ 64  <tbu4_snoc_I_O        snoc_mcput_d2d_T_O 0x29            0x4000000100      >,
+				/bits/ 64  <tbu4_snoc_I_O        snoc_mcput_d2d_T_O 0x2a            0x8000000000      >,
+				/bits/ 64  <tbu4_snoc_I_O        snoc_mcput_d2d_T_O 0x2b            0xa000000000      >,
+				/bits/ 64  <tbu4_snoc_I_O        snoc_mcput_d2d_T_O 0x2c            0x10000000000     >,
+				/bits/ 64  <tbu4_snoc_I_O        snoc_mcput_d2d_T_O 0x2d            0x10000000100     >,
+				/bits/ 64  <tbu4_snoc_I_O        snoc_npu_T_O       0x0             0x52080000        >,
+				/bits/ 64  <tbu4_snoc_I_O        snoc_npu_T_O       0x1             0x72080000        >,
+				/bits/ 64  <tbu4_snoc_I_O        snoc_npu_T_O       0x2             0x59000000        >,
+				/bits/ 64  <tbu4_snoc_I_O        snoc_npu_T_O       0x3             0x5a000000        >,
+				/bits/ 64  <tbu4_snoc_I_O        snoc_npu_T_O       0x4             0x79000000        >,
+				/bits/ 64  <tbu4_snoc_I_O        snoc_npu_T_O       0x5             0x7a000000        >,
+				/bits/ 64  <tbu4_snoc_I_O        snoc_npu_T_O       0x6             0x14001000000     >,
+				/bits/ 64  <tbu4_snoc_I_O        snoc_npu_T_O       0x7             0x14002000000     >,
+				/bits/ 64  <tbu4_snoc_I_O        snoc_npu_T_O       0x8             0x14009000000     >,
+				/bits/ 64  <tbu4_snoc_I_O        snoc_npu_T_O       0x9             0x1400a000000     >,
+				/bits/ 64  <tbu4_snoc_I_O        snoc_npu_T_O       0xa             0x1800000000      >,
+				/bits/ 64  <tbu4_snoc_I_O        snoc_npu_T_O       0xb             0x3800000000      >,
+				/bits/ 64  <tbu4_snoc_I_O        snoc_npu_T_O       0xc             0xd800000000      >,
+				/bits/ 64  <tbu4_snoc_I_O        snoc_npu_T_O       0xd             0xf800000000      >,
+				/bits/ 64  <tbu4_snoc_I_O        snoc_npu_T_O       0xe             0x7000000000      >,
+				/bits/ 64  <tbu4_snoc_I_O        snoc_npu_T_O       0xf             0x7000000100      >,
+				/bits/ 64  <tbu4_snoc_I_O        snoc_npu_T_O       0x10            0x13000000000     >,
+				/bits/ 64  <tbu4_snoc_I_O        snoc_npu_T_O       0x11            0x13000000100     >,
+				/bits/ 64  <tbu4_snoc_I_O        snoc_npu_T_O       0x12            0x0               >,
+				/bits/ 64  <tbu4_snoc_I_O        snoc_npu_T_O       0x13            0x0               >,
+				/bits/ 64  <tbu4_snoc_I_O        snoc_pciet_T_O     0x0             0x40000000        >,
+				/bits/ 64  <tbu4_snoc_I_O        snoc_pciet_T_O     0x1             0x60000000        >,
+				/bits/ 64  <tbu4_snoc_I_O        snoc_pciet_T_O     0x2             0x8000000000      >,
+				/bits/ 64  <tbu4_snoc_I_O        snoc_pciet_T_O     0x3             0xa000000000      >,
+				/bits/ 64  <tcu_snoc_I_O         snoc_ddrt0_p2_T_O  0x0             0x80000000        >,
+				/bits/ 64  <tcu_snoc_I_O         snoc_ddrt0_p2_T_O  0x1             0x100000000       >,
+				/bits/ 64  <tcu_snoc_I_O         snoc_ddrt0_p2_T_O  0x2             0x200000000       >,
+				/bits/ 64  <tcu_snoc_I_O         snoc_ddrt0_p2_T_O  0x3             0x400000000       >,
+				/bits/ 64  <tcu_snoc_I_O         snoc_ddrt0_p2_T_O  0x4             0x800000000       >,
+				/bits/ 64  <tcu_snoc_I_O         snoc_ddrt0_p2_T_O  0x5             0x2000000000      >,
+				/bits/ 64  <tcu_snoc_I_O         snoc_ddrt0_p2_T_O  0x6             0xc000000000      >,
+				/bits/ 64  <tcu_snoc_I_O         snoc_ddrt0_p2_T_O  0x7             0xe000000000      >,
+				/bits/ 64  <tcu_snoc_I_O         snoc_ddrt0_p2_T_O  0x8             0x4000000000      >,
+				/bits/ 64  <tcu_snoc_I_O         snoc_ddrt0_p2_T_O  0x9             0x4000000100      >,
+				/bits/ 64  <tcu_snoc_I_O         snoc_ddrt0_p2_T_O  0xa             0x10000000000     >,
+				/bits/ 64  <tcu_snoc_I_O         snoc_ddrt0_p2_T_O  0xb             0x10000000100     >,
+				/bits/ 64  <tcu_snoc_I_O         snoc_ddrt1_p2_T_O  0x0             0x80000080        >,
+				/bits/ 64  <tcu_snoc_I_O         snoc_ddrt1_p2_T_O  0x1             0x100000080       >,
+				/bits/ 64  <tcu_snoc_I_O         snoc_ddrt1_p2_T_O  0x2             0x200000080       >,
+				/bits/ 64  <tcu_snoc_I_O         snoc_ddrt1_p2_T_O  0x3             0x400000080       >,
+				/bits/ 64  <tcu_snoc_I_O         snoc_ddrt1_p2_T_O  0x4             0x800000080       >,
+				/bits/ 64  <tcu_snoc_I_O         snoc_ddrt1_p2_T_O  0x5             0x2000000080      >,
+				/bits/ 64  <tcu_snoc_I_O         snoc_ddrt1_p2_T_O  0x6             0xc000000080      >,
+				/bits/ 64  <tcu_snoc_I_O         snoc_ddrt1_p2_T_O  0x7             0xe000000080      >,
+				/bits/ 64  <tcu_snoc_I_O         snoc_ddrt1_p2_T_O  0x8             0x4000000080      >,
+				/bits/ 64  <tcu_snoc_I_O         snoc_ddrt1_p2_T_O  0x9             0x4000000180      >,
+				/bits/ 64  <tcu_snoc_I_O         snoc_ddrt1_p2_T_O  0xa             0x10000000080     >,
+				/bits/ 64  <tcu_snoc_I_O         snoc_ddrt1_p2_T_O  0xb             0x10000000180     >,
+				/bits/ 64  <tcu_snoc_I_O         snoc_dspt_T_O      0x0             0x520e0000        >,
+				/bits/ 64  <tcu_snoc_I_O         snoc_dspt_T_O      0x1             0x720e0000        >,
+				/bits/ 64  <tcu_snoc_I_O         snoc_dspt_T_O      0x2             0x5b000000        >,
+				/bits/ 64  <tcu_snoc_I_O         snoc_dspt_T_O      0x3             0x7b000000        >,
+				/bits/ 64  <tcu_snoc_I_O         snoc_dspt_T_O      0x4             0x14003000000     >,
+				/bits/ 64  <tcu_snoc_I_O         snoc_dspt_T_O      0x5             0x1400b000000     >,
+				/bits/ 64  <tcu_snoc_I_O         snoc_mcput_d2d_T_O 0x0             0x58400000        >,
+				/bits/ 64  <tcu_snoc_I_O         snoc_mcput_d2d_T_O 0x1             0x78400000        >,
+				/bits/ 64  <tcu_snoc_I_O         snoc_mcput_d2d_T_O 0x2             0x14000400000     >,
+				/bits/ 64  <tcu_snoc_I_O         snoc_mcput_d2d_T_O 0x3             0x14008400000     >,
+				/bits/ 64  <tcu_snoc_I_O         snoc_mcput_d2d_T_O 0x4             0x58800000        >,
+				/bits/ 64  <tcu_snoc_I_O         snoc_mcput_d2d_T_O 0x5             0x78800000        >,
+				/bits/ 64  <tcu_snoc_I_O         snoc_mcput_d2d_T_O 0x6             0x14000800000     >,
+				/bits/ 64  <tcu_snoc_I_O         snoc_mcput_d2d_T_O 0x7             0x14008800000     >,
+				/bits/ 64  <tcu_snoc_I_O         snoc_mcput_d2d_T_O 0x8             0x59000000        >,
+				/bits/ 64  <tcu_snoc_I_O         snoc_mcput_d2d_T_O 0x9             0x5a000000        >,
+				/bits/ 64  <tcu_snoc_I_O         snoc_mcput_d2d_T_O 0xa             0x5b000000        >,
+				/bits/ 64  <tcu_snoc_I_O         snoc_mcput_d2d_T_O 0xb             0x79000000        >,
+				/bits/ 64  <tcu_snoc_I_O         snoc_mcput_d2d_T_O 0xc             0x7a000000        >,
+				/bits/ 64  <tcu_snoc_I_O         snoc_mcput_d2d_T_O 0xd             0x7b000000        >,
+				/bits/ 64  <tcu_snoc_I_O         snoc_mcput_d2d_T_O 0xe             0x14001000000     >,
+				/bits/ 64  <tcu_snoc_I_O         snoc_mcput_d2d_T_O 0xf             0x14002000000     >,
+				/bits/ 64  <tcu_snoc_I_O         snoc_mcput_d2d_T_O 0x10            0x14003000000     >,
+				/bits/ 64  <tcu_snoc_I_O         snoc_mcput_d2d_T_O 0x11            0x14009000000     >,
+				/bits/ 64  <tcu_snoc_I_O         snoc_mcput_d2d_T_O 0x12            0x1400a000000     >,
+				/bits/ 64  <tcu_snoc_I_O         snoc_mcput_d2d_T_O 0x13            0x1400b000000     >,
+				/bits/ 64  <tcu_snoc_I_O         snoc_mcput_d2d_T_O 0x14            0x50000000        >,
+				/bits/ 64  <tcu_snoc_I_O         snoc_mcput_d2d_T_O 0x15            0x70000000        >,
+				/bits/ 64  <tcu_snoc_I_O         snoc_mcput_d2d_T_O 0x16            0x40000000        >,
+				/bits/ 64  <tcu_snoc_I_O         snoc_mcput_d2d_T_O 0x17            0x60000000        >,
+				/bits/ 64  <tcu_snoc_I_O         snoc_mcput_d2d_T_O 0x18            0x80000000        >,
+				/bits/ 64  <tcu_snoc_I_O         snoc_mcput_d2d_T_O 0x19            0x100000000       >,
+				/bits/ 64  <tcu_snoc_I_O         snoc_mcput_d2d_T_O 0x1a            0x200000000       >,
+				/bits/ 64  <tcu_snoc_I_O         snoc_mcput_d2d_T_O 0x1b            0x400000000       >,
+				/bits/ 64  <tcu_snoc_I_O         snoc_mcput_d2d_T_O 0x1c            0x800000000       >,
+				/bits/ 64  <tcu_snoc_I_O         snoc_mcput_d2d_T_O 0x1d            0x1800000000      >,
+				/bits/ 64  <tcu_snoc_I_O         snoc_mcput_d2d_T_O 0x1e            0x3800000000      >,
+				/bits/ 64  <tcu_snoc_I_O         snoc_mcput_d2d_T_O 0x1f            0xd800000000      >,
+				/bits/ 64  <tcu_snoc_I_O         snoc_mcput_d2d_T_O 0x20            0xf800000000      >,
+				/bits/ 64  <tcu_snoc_I_O         snoc_mcput_d2d_T_O 0x21            0x2000000000      >,
+				/bits/ 64  <tcu_snoc_I_O         snoc_mcput_d2d_T_O 0x22            0x7000000000      >,
+				/bits/ 64  <tcu_snoc_I_O         snoc_mcput_d2d_T_O 0x23            0x7000000100      >,
+				/bits/ 64  <tcu_snoc_I_O         snoc_mcput_d2d_T_O 0x24            0xc000000000      >,
+				/bits/ 64  <tcu_snoc_I_O         snoc_mcput_d2d_T_O 0x25            0xe000000000      >,
+				/bits/ 64  <tcu_snoc_I_O         snoc_mcput_d2d_T_O 0x26            0x13000000000     >,
+				/bits/ 64  <tcu_snoc_I_O         snoc_mcput_d2d_T_O 0x27            0x13000000100     >,
+				/bits/ 64  <tcu_snoc_I_O         snoc_mcput_d2d_T_O 0x28            0x4000000000      >,
+				/bits/ 64  <tcu_snoc_I_O         snoc_mcput_d2d_T_O 0x29            0x4000000100      >,
+				/bits/ 64  <tcu_snoc_I_O         snoc_mcput_d2d_T_O 0x2a            0x8000000000      >,
+				/bits/ 64  <tcu_snoc_I_O         snoc_mcput_d2d_T_O 0x2b            0xa000000000      >,
+				/bits/ 64  <tcu_snoc_I_O         snoc_mcput_d2d_T_O 0x2c            0x10000000000     >,
+				/bits/ 64  <tcu_snoc_I_O         snoc_mcput_d2d_T_O 0x2d            0x10000000100     >,
+				/bits/ 64  <tcu_snoc_I_O         snoc_npu_T_O       0x0             0x52080000        >,
+				/bits/ 64  <tcu_snoc_I_O         snoc_npu_T_O       0x1             0x72080000        >,
+				/bits/ 64  <tcu_snoc_I_O         snoc_npu_T_O       0x2             0x59000000        >,
+				/bits/ 64  <tcu_snoc_I_O         snoc_npu_T_O       0x3             0x5a000000        >,
+				/bits/ 64  <tcu_snoc_I_O         snoc_npu_T_O       0x4             0x79000000        >,
+				/bits/ 64  <tcu_snoc_I_O         snoc_npu_T_O       0x5             0x7a000000        >,
+				/bits/ 64  <tcu_snoc_I_O         snoc_npu_T_O       0x6             0x14001000000     >,
+				/bits/ 64  <tcu_snoc_I_O         snoc_npu_T_O       0x7             0x14002000000     >,
+				/bits/ 64  <tcu_snoc_I_O         snoc_npu_T_O       0x8             0x14009000000     >,
+				/bits/ 64  <tcu_snoc_I_O         snoc_npu_T_O       0x9             0x1400a000000     >,
+				/bits/ 64  <tcu_snoc_I_O         snoc_npu_T_O       0xa             0x1800000000      >,
+				/bits/ 64  <tcu_snoc_I_O         snoc_npu_T_O       0xb             0x3800000000      >,
+				/bits/ 64  <tcu_snoc_I_O         snoc_npu_T_O       0xc             0xd800000000      >,
+				/bits/ 64  <tcu_snoc_I_O         snoc_npu_T_O       0xd             0xf800000000      >,
+				/bits/ 64  <tcu_snoc_I_O         snoc_npu_T_O       0xe             0x7000000000      >,
+				/bits/ 64  <tcu_snoc_I_O         snoc_npu_T_O       0xf             0x7000000100      >,
+				/bits/ 64  <tcu_snoc_I_O         snoc_npu_T_O       0x10            0x13000000000     >,
+				/bits/ 64  <tcu_snoc_I_O         snoc_npu_T_O       0x11            0x13000000100     >,
+				/bits/ 64  <tcu_snoc_I_O         snoc_npu_T_O       0x12            0x0               >,
+				/bits/ 64  <tcu_snoc_I_O         snoc_npu_T_O       0x13            0x0               >;
+			};
+	};
+
+	ErrorLogger4 {
+		compatible = "eswin,eic7700,register";
+		offset,length = < 0x24 32>;
+		description = "Register 4 to log errors";
+		addr_msb {
+			compatible = "eswin,eic7700,bitfield";
+			description = "Stores NTTP packet header field Addr (MSBs) of the logged error";
+			offset,length = < 0 9 >;
+		};
+	};
+
+	ErrorLogger5 {
+		compatible = "eswin,eic7700,register";
+		offset,length = < 0x28 32>;
+		description = "Register 5 to log errors";
+
+		User_flag {
+			compatible = "eswin,eic7700,bitfield";
+			offset,length = < 0x0 18 >;
+			lut =
+				"Cache_0",
+				"Cache_1",
+				"Cache_2",
+				"Cache_3",
+				"Prot_0 ",
+				"Prot_1 ",
+				"Prot_2 ",
+				"User_0 ",
+				"User_1 ",
+				"User_2 ",
+				"User_3 ",
+				"User_4 ",
+				"User_5 ",
+				"User_6 ",
+				"qos0",
+				"qos1",
+				"qos2",
+				"qos3";
+		};
+	};
+};
+
+d0_media_noc:d0_media_noc@52021400 {
+	compatible = "eswin,eic7700-noc";
+	#address-cells = <2>;
+	#size-cells = <2>;
+	ranges;
+	reg = <0 0x52021400 0 0x4000>;
+	interrupts = <454>;
+	interrupt-names = "error";
+	interrupt-parent = <&plic0>;
+	errlogger,idx = <0 1 3 4 5>;
+	eswin,qos-configs = "GPU", "TBU2", "VC";
+	eswin,GPU-qos-base = <0x52021480>;
+	eswin,GPU-qos-settings = <
+		0x8 0x4        /* prio */
+		0xC 0x2        /* mode */
+		0x10 0x1E0    /* bandwidth*/
+		0x14 0x1     /* saturation*/
+		0x18 0x1>;   /* QoSEn */
+
+	eswin,TBU2-qos-base = <0x52021500>;
+	eswin,TBU2-qos-settings = <
+		0x8 0x4      /* prio */
+		0xC 0x2      /* mode */
+		0x10 0x18    /* bandwidth */
+		0x14 0x10    /* saturation */
+		0x18 0x1>;   /* QoSEn */
+
+	eswin,VC-qos-base = <0x52021580>;
+	eswin,VC-qos-settings = <
+		0x8 0x4      /* prio */
+		0xC 0x2      /* mode */
+		0x10 0x18    /* bandwidth */
+		0x14 0x10    /* saturation */
+		0x18 0x1>;   /* QoSEn */
+	sideband_manager@52022000 {
+		compatible = "eswin,win2xxx-noc-sideband-manager";
+		reg = <0 0x52022000 0 0x10>;
+		SenseIn0 =
+			<SBM_MNOC_GPU 	OFFSET0>,
+			<SBM_MNOC_TBU2 	OFFSET1>,
+			<SBM_MNOC_VC 	OFFSET2>,
+			<SBM_MNOC_DDRT0_P3 	OFFSET3>,
+			<SBM_MNOC_DDRT1_P3 	OFFSET4>;
+		bf-name =
+			"SBM_MNOC_GPU",
+			"SBM_MNOC_TBU2",
+			"SBM_MNOC_VC",
+			"SBM_MNOC_DDRT0_P3",
+			"SBM_MNOC_DDRT1_P3";
+	};
+
+	mnoc_packet_ddr0_p3_req_probe@52020000 {
+		compatible = "eswin,win2xxx-noc-packet-probe";
+		reg = <0 0x52020000 0 0x4000>;
+		clocks = <&d0_clock EIC7700_CLK_DDRT0_P3_ACLK>;
+		clock-names = "clk";
+		interrupts = <458>;
+		interrupt-names = "stat";
+		interrupt-parent = <&plic0>;
+		filter,nr = <1>;
+		counter,nr = <2>;
+		portsel = "ddr0_p3_req";
+	};
+	mnoc_packet_ddr1_p3_req_probe@52020800 {
+		compatible = "eswin,win2xxx-noc-packet-probe";
+		reg = <0 0x52020800 0 0x4000>;
+		clocks =<&d0_clock EIC7700_CLK_DDRT1_P3_ACLK>;
+		clock-names = "clk";
+		interrupts = <456>;
+		interrupt-names = "stat";
+		interrupt-parent = <&plic0>;
+		filter,nr = <1>;
+		counter,nr = <2>;
+		portsel = "ddr1_p3_req";
+	};
+	mnoc_trans_probe@52021000 {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+		compatible = "eswin,win2xxx-noc-trans-probe";
+		reg = <0 0x52021000 0 0x4000>;
+		clocks =<&d0_clock EIC7700_CLK_NOC_NSP_CLK>;
+		clock-names = "clk";
+		interrupts = <453>;
+		interrupt-names = "stat";
+		interrupt-parent = <&plic0>;
+		filter,nr = <3>;
+		counter,nr = <12>;
+		profiler,nr = <1>;
+		portsel = "gpu", "tbu2", "vc";
+		mnoc_trans_gpu_filter@52021600 {
+			status = "disabled";
+			compatible = "eswin,win2xxx-noc-trans-filter";
+			reg = <0 0x52021600 0 0x80>;
+		};
+		mnoc_trans_tbu2_filter@52021680 {	/*hsp subsys*/
+			status = "disabled";
+			compatible = "eswin,win2xxx-noc-trans-filter";
+			reg = <0 0x52021680 0 0x80>;
+		};
+		mnoc_trans_vc_filter@52021700 {
+			status = "disabled";
+			compatible = "eswin,win2xxx-noc-trans-filter";
+			reg = <0 0x52021700 0 0x80>;
+		};
+		mnoc_trans_profiler@52021780 {
+			compatible = "eswin,win2xxx-noc-trans-profiler";
+			reg = <0 0x52021780 0 0x80>;
+		};
+	};
+	ErrorLogger0 {
+		compatible = "eswin,eic7700,register";
+		offset,length = < 0x14 32 >;
+		description = "Register 0 to log errors";
+		lock {
+			compatible = "eswin,eic7700,bitfield";
+			offset,length = < 0 1 >;
+			lut = "Not Locked", "Locked";
+		};
+		OpCode {
+			compatible = "eswin,eic7700,bitfield";
+			offset,length = < 1 4 >;
+			lut = "RD: data read with incrementing address",
+				"RDW: data read with wrapping address",
+				"RDL: allocates monitor in the Target with incrementing address",
+				"RDX: exclusive read with incrementing address",
+				"WR: data write with incrementing address",
+				"WRW: data write with wrapping address",
+				"WRC: conditional write if matching monitor in Target is found",
+				"RSV: reserved",
+				"PRE: preamble packet of linked sequence (locked sequence)",
+				"URG: urgency packet used for QoS (status must be REQ)";
+		};
+		ErrCode {
+			compatible = "eswin,eic7700,bitfield";
+			offset,length = < 8 3 >;
+			lut = "SLV (error source: Target): error detected by the Slave without any information or no Error",
+				"DEC (error source: Initiator NIU): decode error",
+				"UNS (error source: Target NIU): unsupported access type",
+				"DISC (error source: Power Disconnect): disconnected Target or NoC domain",
+				"SEC (error source: Initiator NIU or Firewall): security error",
+				"HIDE (error source: Firewall): hidden security error. Will be reported as OK to the initiator",
+				"TMO (error source: Target NIU): time-out",
+				"RSV: reserved";
+
+		};
+		Len1 {
+			compatible = "eswin,eic7700,bitfield";
+			offset,length = < 16 12 >;
+		};
+		Format {
+			compatible = "eswin,eic7700,bitfield";
+			offset,length = < 31 1 >;
+			lut = "NTTP v3.0 (Invalid)", "NTTP v3.5 (Ok)";
+		};
+	};
+
+	ErrorLogger1 {
+		compatible = "eswin,eic7700,register", "eswin,eic7700,noc,filter,routeid";
+		offset,length = < 0x18 32>;
+		description = "Register 1 to log errors";
+		InitFlow {
+			compatible = "eswin,eic7700,bitfield";
+			offset,length = < 14 2 >;
+			lut =
+				"gpu_mnoc/I/0",
+				"snoc_mnoc/I/0",
+				"tbu2_mnoc/I/0",
+				"vc_mnoc/I/0";
+		};
+
+		TargetFlow {
+			compatible = "eswin,eic7700,bitfield";
+			offset,length = < 12 2 >;
+			lut =
+				"mnoc_ddrt0_p3/T/0",
+				"mnoc_ddrt1_p3/T/0",
+				"mnoc_service/T/0",
+				"mnoc_snoc/T/0";
+		};
+
+		TargetSubRange {
+			compatible = "eswin,eic7700,bitfield";
+			offset,length = < 9 3 >;
+		};
+
+		SeqId {
+			compatible = "eswin,eic7700,bitfield";
+			offset,length = < 0 9 >;
+		};
+	};
+
+	ErrorLogger3 {
+		/* This register does not really include a bitfield or its bitfield is 32 bits and it provides an offset address */
+		/* To calculate the absolute address, you must use the initflow:targetflow:subrange from ErrorLogger1 register */
+		/* And use it as an index in the aperture table. Then you must add the value of this register to the value given */
+		/* by the table to get the absolute address. */
+		compatible = "eswin,eic7700,register";
+		offset,length = <0x20 32>;
+		description = "Register 3 to log errors";
+		aperture-link = <1>; /* link to ErrorLogger whose information are required to calculate real absolute address */
+		msb-link = <4>; /*indicate which ErrorLogger contains the msb addrs, -1 means no*/
+		AbsoluteAddress {
+			compatible = "eswin,eic7700,bitfield";
+			offset,length = < 9 7 >;		/* bitfield initflow:targeflow:subrange from aperture-link register */
+			aperture-size= < 55 >;			/* Number of line in the aperture table below */
+			aperture-idx,aperture-base =	/* Aperture_idx is concatenation of initflow:targetflow:subrange bitfield from ErrorLogger1 */
+					/bits/ 64  <0x0  0x0 0x0           0x80000000       >,
+					/bits/ 64  <0x0  0x0 0x1           0x100000000      >,
+					/bits/ 64  <0x0  0x0 0x2           0x200000000      >,
+					/bits/ 64  <0x0  0x0 0x3           0x400000000      >,
+					/bits/ 64  <0x0  0x0 0x4           0x800000000      >,
+					/bits/ 64  <0x0  0x0 0x5           0x2000000000     >,
+					/bits/ 64  <0x0  0x0 0x6           0x4000000000     >,
+					/bits/ 64  <0x0  0x0 0x7           0x4000000100     >,
+					/bits/ 64  <0x0  0x1 0x0           0x80000080       >,
+					/bits/ 64  <0x0  0x1 0x1           0x100000080      >,
+					/bits/ 64  <0x0  0x1 0x2           0x200000080      >,
+					/bits/ 64  <0x0  0x1 0x3           0x400000080      >,
+					/bits/ 64  <0x0  0x1 0x4           0x800000080      >,
+					/bits/ 64  <0x0  0x1 0x5           0x2000000080     >,
+					/bits/ 64  <0x0  0x1 0x6           0x4000000080     >,
+					/bits/ 64  <0x0  0x1 0x7           0x4000000180     >,
+					/bits/ 64  <0x0  0x3 0x0           0x0              >,
+					/bits/ 64  <0x1 0x2  0x0           0x52020000       >,
+					/bits/ 64  <0x1 0x2  0x1           0x72020000       >,
+					/bits/ 64  <0x1 0x2  0x2           0x0              >,
+					/bits/ 64  <0x1 0x2  0x3           0x0              >,
+					/bits/ 64  <0x2 0x0 0x0           0x80000000       >,
+					/bits/ 64  <0x2 0x0 0x1           0x100000000      >,
+					/bits/ 64  <0x2 0x0 0x2           0x200000000      >,
+					/bits/ 64  <0x2 0x0 0x3           0x400000000      >,
+					/bits/ 64  <0x2 0x0 0x4           0x800000000      >,
+					/bits/ 64  <0x2 0x0 0x5           0x2000000000     >,
+					/bits/ 64  <0x2 0x0 0x6           0x4000000000     >,
+					/bits/ 64  <0x2 0x0 0x7           0x4000000100     >,
+					/bits/ 64  <0x2 0x1 0x0           0x80000080       >,
+					/bits/ 64  <0x2 0x1 0x1           0x100000080      >,
+					/bits/ 64  <0x2 0x1 0x2           0x200000080      >,
+					/bits/ 64  <0x2 0x1 0x3           0x400000080      >,
+					/bits/ 64  <0x2 0x1 0x4           0x800000080      >,
+					/bits/ 64  <0x2 0x1 0x5           0x2000000080     >,
+					/bits/ 64  <0x2 0x1 0x6           0x4000000080     >,
+					/bits/ 64  <0x2 0x1 0x7           0x4000000180     >,
+					/bits/ 64  <0x2 0x3   0x0           0x0              >,
+					/bits/ 64  <0x3   0x0 0x0           0x80000000       >,
+					/bits/ 64  <0x3   0x0 0x1           0x100000000      >,
+					/bits/ 64  <0x3   0x0 0x2           0x200000000      >,
+					/bits/ 64  <0x3   0x0 0x3           0x400000000      >,
+					/bits/ 64  <0x3   0x0 0x4           0x800000000      >,
+					/bits/ 64  <0x3   0x0 0x5           0x2000000000     >,
+					/bits/ 64  <0x3   0x0 0x6           0x4000000000     >,
+					/bits/ 64  <0x3   0x0 0x7           0x4000000100     >,
+					/bits/ 64  <0x3   0x1 0x0           0x80000080       >,
+					/bits/ 64  <0x3   0x1 0x1           0x100000080      >,
+					/bits/ 64  <0x3   0x1 0x2           0x200000080      >,
+					/bits/ 64  <0x3   0x1 0x3           0x400000080      >,
+					/bits/ 64  <0x3   0x1 0x4           0x800000080      >,
+					/bits/ 64  <0x3   0x1 0x5           0x2000000080     >,
+					/bits/ 64  <0x3   0x1 0x6           0x4000000080     >,
+					/bits/ 64  <0x3   0x1 0x7           0x4000000180     >,
+					/bits/ 64  <0x3   0x3 0x0           0x0              >;
+		};
+	};
+
+	ErrorLogger4 {
+		compatible = "eswin,eic7700,register";
+		offset,length = < 0x24 32>;
+		description = "Register 4 to log errors";
+		addr_msb {
+			compatible = "eswin,eic7700,bitfield";
+			description = "Stores NTTP packet header field Addr (MSBs) of the logged error";
+			offset,length = < 0 9 >;
+		};
+	};
+
+	ErrorLogger5 {
+		compatible = "eswin,eic7700,register";
+		offset,length = < 0x28 32 >;
+		description = "Register 5 to log errors";
+
+		User_flag {
+			compatible = "eswin,eic7700,bitfield";
+			offset,length = < 0x0 18 >;
+			lut =
+				"Cache_0",
+				"Cache_1",
+				"Cache_2",
+				"Cache_3",
+				"Prot_0 ",
+				"Prot_1 ",
+				"Prot_2 ",
+				"User_0 ",
+				"User_1 ",
+				"User_2 ",
+				"User_3 ",
+				"User_4 ",
+				"User_5 ",
+				"User_6 ",
+				"qos0",
+				"qos1",
+				"qos2",
+				"qos3";
+		};
+	};
+};
+
+d0_realtime_noc:d0_realtime_noc@52041400 {
+	compatible = "eswin,eic7700-noc";
+	#address-cells = <2>;
+	#size-cells = <2>;
+	ranges;
+	reg = <0 0x52041400 0 0x4000>;
+	interrupts = <448>;
+	interrupt-names = "error";
+	interrupt-parent = <&plic0>;
+	errlogger,idx = <0 1 3 4 5>;
+	eswin,qos-configs = "TBU0", "VO";
+	eswin,TBU0-qos-base = <0x52041480>;
+	eswin,TBU0-qos-settings = <
+		0x8 0x4        /* prio */
+		0xC 0x2        /* mode */
+		0x10 0x1E0    /* bandwidth */
+		0x14 0x1     /* saturation */
+		0x18 0x1>;   /* QoSEn */
+
+	eswin,VO-qos-base = <0x52041500>;
+	eswin,VO-qos-settings = <
+		0x8 0x4      /* prio */
+		0xC 0x2      /* mode */
+		0x10 0x18    /* bandwidth */
+		0x14 0x10    /* saturation */
+		0x18 0x1>;   /* QoSEn */
+	sideband_manager@52042000 {
+		compatible = "eswin,win2xxx-noc-sideband-manager";
+		reg = <0 0x52042000 0 0x10>;
+		SenseIn0 =
+			<SBM_RNOC_TBU0 	OFFSET0>,
+			<SBM_RNOC_VO 	OFFSET1>,
+			<SBM_RNOC_DDRT0_P4 	OFFSET2>,
+			<SBM_RNOC_DDRT1_P4 	OFFSET3>;
+		bf-name =
+			"SBM_RNOC_TBU0",
+			"SBM_RNOC_VO",
+			"SBM_RNOC_DDRT0_P4",
+			"SBM_RNOC_DDRT1_P4";
+	};
+
+	rnoc_packet_ddr0_p4_req_probe@52040000 {
+		compatible = "eswin,win2xxx-noc-packet-probe";
+		reg = <0 0x52040000 0 0x4000>;
+		clocks = <&d0_clock EIC7700_CLK_DDRT0_P4_ACLK>;
+		clock-names = "clk";
+		interrupts = <452>;
+		interrupt-names = "stat";
+		interrupt-parent = <&plic0>;
+		filter,nr = <1>;
+		counter,nr = <2>;
+		portsel = "ddr0_p4_req";
+	};
+	rnoc_packet_ddr1_p4_req_probe@52040800 {
+		compatible = "eswin,win2xxx-noc-packet-probe";
+		reg = <0 0x52040800 0 0x4000>;
+		clocks =<&d0_clock EIC7700_CLK_DDRT1_P4_ACLK>;
+		clock-names = "clk";
+		interrupts = <450>;
+		interrupt-names = "stat";
+		interrupt-parent = <&plic0>;
+		filter,nr = <1>;
+		counter,nr = <2>;
+		portsel = "ddr1_p4_req";
+	};
+	rnoc_trans_probe@52041000 {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+		compatible = "eswin,win2xxx-noc-trans-probe";
+		reg = <0 0x52041000 0 0x4000>;
+		clocks =<&d0_clock EIC7700_CLK_NOC_NSP_CLK>;
+		clock-names = "clk";
+		interrupts = <447>;
+		interrupt-names = "stat";
+		interrupt-parent = <&plic0>;
+		filter,nr = <2>;
+		counter,nr = <8>;
+		profiler,nr = <1>;
+		portsel = "tbu0", "vo";
+		rnoc_trans_tbu0_filter@52041580 {	/*vi subsys*/
+			status = "disabled";
+			compatible = "eswin,win2xxx-noc-trans-filter";
+			reg = <0 0x52041580 0 0x80>;
+		};
+		rnoc_trans_vo_filter@52041600 {
+			status = "disabled";
+			compatible = "eswin,win2xxx-noc-trans-filter";
+			reg = <0 0x52041600 0 0x80>;
+		};
+		rnoc_trans_profiler@52041680 {
+			compatible = "eswin,win2xxx-noc-trans-profiler";
+			reg = <0 0x52041680 0 0x80>;
+		};
+	};
+	ErrorLogger0 {
+		compatible = "eswin,eic7700,register";
+		offset,length = < 0x14 32 >;
+		description = "Register 0 to log errors";
+		lock {
+			compatible = "eswin,eic7700,bitfield";
+			offset,length = < 0 1 >;
+			lut = "Not Locked", "Locked";
+		};
+		OpCode {
+			compatible = "eswin,eic7700,bitfield";
+			offset,length = < 1 4 >;
+			lut = "RD: data read with incrementing address",
+				"RDW: data read with wrapping address",
+				"RDL: allocates monitor in the Target with incrementing address",
+				"RDX: exclusive read with incrementing address",
+				"WR: data write with incrementing address",
+				"WRW: data write with wrapping address",
+				"WRC: conditional write if matching monitor in Target is found",
+				"RSV: reserved",
+				"PRE: preamble packet of linked sequence (locked sequence)",
+				"URG: urgency packet used for QoS (status must be REQ)";
+		};
+		ErrCode {
+			compatible = "eswin,eic7700,bitfield";
+			offset,length = < 8 3 >;
+			lut = "SLV (error source: Target): error detected by the Slave without any information or no Error",
+				"DEC (error source: Initiator NIU): decode error",
+				"UNS (error source: Target NIU): unsupported access type",
+				"DISC (error source: Power Disconnect): disconnected Target or NoC domain",
+				"SEC (error source: Initiator NIU or Firewall): security error",
+				"HIDE (error source: Firewall): hidden security error. Will be reported as OK to the initiator",
+				"TMO (error source: Target NIU): time-out",
+				"RSV: reserved";
+
+		};
+		Len1 {
+			compatible = "eswin,eic7700,bitfield";
+			offset,length = < 16 12 >;
+		};
+		Format {
+			compatible = "eswin,eic7700,bitfield";
+			offset,length = < 31 1 >;
+			lut = "NTTP v3.0 (Invalid)", "NTTP v3.5 (Ok)";
+		};
+	};
+
+	ErrorLogger1 {
+		compatible = "eswin,eic7700,register", "eswin,eic7700,noc,filter,routeid";
+		offset,length = < 0x18 32>;
+		description = "Register 1 to log errors";
+		InitFlow {
+			compatible = "eswin,eic7700,bitfield";
+			offset,length = < 14 2 >;
+			lut =
+				"snoc_rnoc/I/0",
+				"tbu0_rnoc/I/0",
+				"vo_rnoc/I/0",
+				"RESERVED0";
+		};
+
+		TargetFlow {
+			compatible = "eswin,eic7700,bitfield";
+			offset,length = < 12 2 >;
+			lut =
+				"rnoc_ddrt0_p4/T/0",
+				"rnoc_ddrt1_p4/T/0",
+				"rnoc_service/T/0",
+				"rnoc_snoc/T/0";
+		};
+
+		TargetSubRange {
+			compatible = "eswin,eic7700,bitfield";
+			offset,length = < 9 3 >;
+		};
+
+		SeqId {
+			compatible = "eswin,eic7700,bitfield";
+			offset,length = < 0 9 >;
+		};
+	};
+
+	ErrorLogger3 {
+		/* This register does not really include a bitfield or its bitfield is 32 bits and it provides an offset address */
+		/* To calculate the absolute address, you must use the initflow:targetflow:subrange from ErrorLogger1 register */
+		/* And use it as an index in the aperture table. Then you must add the value of this register to the value given */
+		/* by the table to get the absolute address. */
+		compatible = "eswin,eic7700,register";
+		offset,length = <0x20 32>;
+		description = "Register 3 to log errors";
+		aperture-link = <1>; /* link to ErrorLogger whose information are required to calculate real absolute address */
+		msb-link = <4>; /*indicate which ErrorLogger contains the msb addrs, -1 means no*/
+		AbsoluteAddress {
+			compatible = "eswin,eic7700,bitfield";
+			offset,length = < 9 7 >;		/* bitfield initflow:targeflow:subrange from aperture-link register */
+			aperture-size= < 40 >;			/* Number of line in the aperture table below */
+			aperture-idx,aperture-base =	/* Aperture_idx is concatenation of initflow:targetflow:subrange bitfield from ErrorLogger1 */
+					/bits/ 64  <0x0 0x2 0x0          0x52040000       >,
+					/bits/ 64  <0x0 0x2 0x1          0x72040000       >,
+					/bits/ 64  <0x0 0x2 0x2          0x0              >,
+					/bits/ 64  <0x0 0x2 0x3          0x0              >,
+					/bits/ 64  <0x1 0x0 0x0          0x80000000       >,
+					/bits/ 64  <0x1 0x0 0x1          0x100000000      >,
+					/bits/ 64  <0x1 0x0 0x2          0x200000000      >,
+					/bits/ 64  <0x1 0x0 0x3          0x400000000      >,
+					/bits/ 64  <0x1 0x0 0x4          0x800000000      >,
+					/bits/ 64  <0x1 0x0 0x5          0x2000000000     >,
+					/bits/ 64  <0x1 0x1 0x0          0x80000080       >,
+					/bits/ 64  <0x1 0x1 0x1          0x100000080      >,
+					/bits/ 64  <0x1 0x1 0x2          0x200000080      >,
+					/bits/ 64  <0x1 0x1 0x3          0x400000080      >,
+					/bits/ 64  <0x1 0x1 0x4          0x800000080      >,
+					/bits/ 64  <0x1 0x1 0x5          0x2000000080     >,
+					/bits/ 64  <0x1 0x3 0x0          0x59000000       >,
+					/bits/ 64  <0x1 0x3 0x1          0x79000000       >,
+					/bits/ 64  <0x1 0x3 0x2          0x14001000000    >,
+					/bits/ 64  <0x1 0x3 0x3          0x14009000000    >,
+					/bits/ 64  <0x1 0x3 0x4          0x0              >,
+					/bits/ 64  <0x1 0x3 0x5          0x0              >,
+					/bits/ 64  <0x2 0x0 0x0          0x80000000       >,
+					/bits/ 64  <0x2 0x0 0x1          0x100000000      >,
+					/bits/ 64  <0x2 0x0 0x2          0x200000000      >,
+					/bits/ 64  <0x2 0x0 0x3          0x400000000      >,
+					/bits/ 64  <0x2 0x0 0x4          0x800000000      >,
+					/bits/ 64  <0x2 0x0 0x5          0x2000000000     >,
+					/bits/ 64  <0x2 0x1 0x0          0x80000080       >,
+					/bits/ 64  <0x2 0x1 0x1          0x100000080      >,
+					/bits/ 64  <0x2 0x1 0x2          0x200000080      >,
+					/bits/ 64  <0x2 0x1 0x3          0x400000080      >,
+					/bits/ 64  <0x2 0x1 0x4          0x800000080      >,
+					/bits/ 64  <0x2 0x1 0x5          0x2000000080     >,
+					/bits/ 64  <0x2 0x3 0x0          0x59000000       >,
+					/bits/ 64  <0x2 0x3 0x1          0x79000000       >,
+					/bits/ 64  <0x2 0x3 0x2          0x14001000000    >,
+					/bits/ 64  <0x2 0x3 0x3          0x14009000000    >,
+					/bits/ 64  <0x2 0x3 0x4          0x0              >,
+					/bits/ 64  <0x2 0x3 0x5          0x0              >;
+		};
+	};
+
+	ErrorLogger4 {
+		compatible = "eswin,eic7700,register";
+		offset,length = < 0x24 32>;
+		description = "Register 4 to log errors";
+		addr_msb {
+			compatible = "eswin,eic7700,bitfield";
+			description = "Stores NTTP packet header field Addr (MSBs) of the logged error";
+			offset,length = < 0 9 >;
+		};
+	};
+
+	ErrorLogger5 {
+		compatible = "eswin,eic7700,register";
+		offset,length = < 0x28 32 >;
+		description = "Register 5 to log errors";
+
+		User_flag {
+			compatible = "eswin,eic7700,bitfield";
+			offset,length = < 0x0 16 >;
+			lut =
+				 "Cache_0",
+				 "Cache_1",
+				 "Cache_2",
+				 "Cache_3",
+				 "Prot_0 ",
+				 "Prot_1 ",
+				 "Prot_2 ",
+				 "User_0 ",
+				 "User_1 ",
+				 "User_2 ",
+				 "User_3 ",
+				 "User_4 ",
+				 "qos0",
+				 "qos1",
+				 "qos2",
+				 "qos3";
+		};
+	};
+};
diff --git a/arch/riscv/boot/dts/eswin/eic7700-pinctrl-common.dtsi b/arch/riscv/boot/dts/eswin/eic7700-pinctrl-common.dtsi
new file mode 100644
index 000000000000..9b0e18db1d2b
--- /dev/null
+++ b/arch/riscv/boot/dts/eswin/eic7700-pinctrl-common.dtsi
@@ -0,0 +1,1339 @@
+#include "eic7700.dtsi"
+#include <dt-bindings/interrupt-controller/irq.h>
+
+/ {
+    #address-cells = <2>;
+    #size-cells = <2>;
+    soc {
+        pinctrl: pinctrl@0x51600080 {
+			compatible = "eswin,eic7700-pinctrl", "syscon";
+			reg = <0x0 0x51600080 0x0 0x1FFF80>;
+			status = "disabled";
+            //func0
+            pinctrl_sdio0_default: sdio0-default{
+				mux {
+					groups = "sdio0_group";
+					function = "sdio0_func";
+				};
+			};
+            pinctrl_sdio1_default: sdio1-default{
+				mux {
+					groups = "sdio1_group";
+					function = "sdio1_func";
+				};
+			};
+            pinctrl_por_sel_default: por_sel-default{
+				mux {
+					groups = "por_sel_group";
+					function = "por_sel_func";
+				};
+			};
+            pinctrl_jtag0_default: jtag0-default{
+				mux {
+					groups = "jtag0_group";
+					function = "jtag0_func";
+				};
+			};
+            pinctrl_jtag1_default: jtag1-default{
+				mux {
+					groups = "jtag1_group";
+					function = "jtag1_func";
+				};
+			};
+            pinctrl_jtag2_default: jtag2-default{
+				mux {
+					groups = "jtag2_group";
+					function = "jtag2_func";
+				};
+			};
+            pinctrl_pcie_default: pcie-default{
+				mux{
+					groups = "pcie_group";
+					function = "pcie_func";
+				};
+			};
+            pinctrl_hdmi_default: hdmi-default{
+				mux{
+					groups = "hdmi_group";
+					function = "hdmi_func";
+				};
+			};
+            pinctrl_rgmii0_default: rgmii0-default{
+				mux {
+					groups = "rgmii0_group";
+					function = "rgmii0_func";
+				};
+			};
+            pinctrl_rgmii1_default: rgmii1-default{
+				mux{
+					groups = "rgmii1_group";
+					function = "rgmii1_func";
+				};
+			};
+            pinctrl_spi0_default: spi0-default{
+				mux {
+					groups = "spi0_group";
+					function = "spi0_func";
+				};
+			};
+            pinctrl_spi1_default: spi1-default{
+				mux{
+					groups = "spi1_group";
+					function = "spi1_func";
+				};
+			};
+            pinctrl_spi3_default: spi3-default{
+				mux {
+					groups = "spi3_group";
+					function = "spi3_func";
+				};
+			};
+            pinctrl_por_time_sel0_default: por_time_sel0-default{
+				mux {
+					groups = "por_time_sel0_group";
+					function = "por_time_sel0_func";
+				};
+			};
+            pinctrl_por_time_sel1_default: por_time_sel1-default{
+				mux {
+					groups = "por_time_sel1_group";
+					function = "por_time_sel1_func";
+				};
+			};
+            pinctrl_i2s0_default: i2s0-default{
+				mux {
+					groups = "i2s0_group";
+					function = "i2s0_func";
+				};
+			};
+            pinctrl_i2s1_default: i2s1-default{
+				mux {
+					groups = "i2s1_group";
+					function = "i2s1_func";
+				};
+			};
+            pinctrl_i2s2_default: i2s2-default{
+				mux {
+					groups = "i2s2_group";
+					function = "i2s2_func";
+				};
+			};
+            pinctrl_usb0_pwren_default: usb0_pwren-default{
+				mux {
+					groups = "usb0_pwren_group";
+					function = "usb0_pwren_func";
+				};
+			};
+            pinctrl_usb1_pwren_default: usb1_pwren-default{
+				mux {
+					groups = "usb1_pwren_group";
+					function = "usb1_pwren_func";
+				};
+			};
+            pinctrl_i2c0_default: i2c0-default{
+				mux {
+					groups = "i2c0_group";
+					function = "i2c0_func";
+				};
+			};
+            pinctrl_i2c1_default: i2c1-default{
+				mux {
+					groups = "i2c1_group";
+					function = "i2c1_func";
+				};
+			};
+            pinctrl_i2c2_default: i2c2-default{
+				mux {
+					groups = "i2c2_group";
+					function = "i2c2_func";
+				};
+			};
+            pinctrl_i2c3_default: i2c3-default{
+				mux {
+					groups = "i2c3_group";
+					function = "i2c3_func";
+				};
+			};
+            pinctrl_i2c4_default: i2c4-default{
+				mux {
+					groups = "i2c4_group";
+					function = "i2c4_func";
+				};
+			};
+            pinctrl_i2c5_default: i2c5-default{
+				mux {
+					groups = "i2c5_group";
+					function = "i2c5_func";
+				};
+			};
+            pinctrl_i2c8_default: i2c8-default{
+				mux {
+					groups = "i2c8_group";
+					function = "i2c8_func";
+				};
+			};
+            pinctrl_i2c10_default: i2c10-default{
+				mux {
+					groups = "i2c10_group";
+					function = "i2c10_func";
+				};
+			};
+            pinctrl_i2c11_default: i2c11-default{
+				mux {
+					groups = "i2c11_group";
+					function = "i2c11_func";
+				};
+			};
+            pinctrl_uart0_default: uart0-default{
+				mux {
+					groups = "uart0_group";
+					function = "uart0_func";
+				};
+			};
+            pinctrl_uart1_default: uart1-default{
+				mux {
+					groups = "uart1_group";
+					function = "uart1_func";
+				};
+			};
+            pinctrl_uart2_default: uart2-default{
+				mux {
+					groups = "uart2_group";
+					function = "uart2_func";
+				};
+			};
+            pinctrl_pwm0_default: pwm0-default{
+                mux {
+                    groups = "pwm0_group";
+                    function = "pwm0_func";
+                };
+            };
+            pinctrl_fan_tach_default: fan_tach-default{
+				mux {
+					groups = "fan_tach_group";
+					function = "fan_tach_func";
+				};
+			};
+            pinctrl_mipi_csi0_default: mipi_csi0-default{
+				mux {
+					groups = "mipi_csi0_group";
+					function = "mipi_csi0_func";
+				};
+			};
+            pinctrl_mipi_csi1_default: mipi_csi1-default{
+				mux {
+					groups = "mipi_csi1_group";
+					function = "mipi_csi1_func";
+				};
+			};
+            pinctrl_mipi_csi2_default: mipi_csi2-default{
+				mux {
+					groups = "mipi_csi2_group";
+					function = "mipi_csi2_func";
+				};
+			};
+            pinctrl_mipi_csi3_default: mipi_csi3-default{
+				mux {
+					groups = "mipi_csi3_group";
+					function = "mipi_csi3_func";
+				};
+			};
+            pinctrl_mipi_csi4_default: mipi_csi4-default{
+				mux {
+					groups = "mipi_csi4_group";
+					function = "mipi_csi4_func";
+				};
+			};
+            pinctrl_mipi_csi5_default: mipi_csi5-default{
+				mux {
+					groups = "mipi_csi5_group";
+					function = "mipi_csi5_func";
+				};
+			};
+            pinctrl_s_mode_default: s_mode-default{
+				mux {
+					groups = "s_mode_group";
+					function = "s_mode_func";
+				};
+			};
+            pinctrl_pinmux_ddr_refclk_sel_default: pinmux_ddr_refclk_sel-default{
+				mux {
+					groups = "pinmux_ddr_refclk_sel_group";
+					function = "pinmux_ddr_refclk_sel_func";
+				};
+			};
+            pinctrl_boot_sel_default: boot_sel-default{
+				mux {
+					groups = "boot_sel_group";
+					function = "boot_sel_func";
+				};
+			};
+            pinctrl_lpddr_ref_clk_default: lpddr_ref_clk-default{
+				mux {
+					groups = "lpddr_ref_clk_group";
+					function = "lpddr_ref_clk_func";
+				};
+			};
+
+            //func1
+            pinctrl_spi2_default: spi2-default{
+				mux1 {
+					groups = "spi2_clk_group";
+					function = "spi2_clk_func";
+				};
+				conf1 {
+					groups = "spi2_clk_group";
+					input-enable = <1>;
+					bias-pull-up = <1>;
+					bias-pull-down = <0>;
+				};
+				mux2 {
+					groups = "spi2_d0_group";
+					function = "spi2_d0_func";
+				};
+				conf2 {
+					groups = "spi2_d0_group";
+					input-enable = <1>;
+					bias-pull-up = <1>;
+					bias-pull-down = <0>;
+				};
+				mux3 {
+					groups = "spi2_d1_d2_d3_group";
+					function = "spi2_d1_d2_d3_func";
+				};
+				conf3 {
+					groups = "spi2_d1_d2_d3_group";
+					input-enable = <1>;
+					bias-pull-up = <1>;
+					bias-pull-down = <0>;
+				};
+				mux4 {
+					groups = "spi2_cs_group";
+					function = "spi2_cs_func";
+				};
+			};
+
+            pinctrl_sata_act_led_default: sata_act_led-default{
+				mux {
+					groups = "sata_act_led_group";
+					function = "sata_act_led_func";
+				};
+				conf {
+					groups = "sata_act_led_group";
+					input-enable = <0>;
+					bias-pull-down = <1>;
+				};
+			};
+            pinctrl_emmc_led_control_default: emmc_led_control-default{
+				mux {
+					groups = "emmc_led_control_group";
+					function = "emmc_led_control_func";
+				};
+				conf {
+					groups = "emmc_led_control_group";
+					input-enable = <0>;
+					bias-pull-down = <1>;
+				};
+			};
+            pinctrl_sd0_led_control_default: sd0_led_control-default{
+				mux {
+					groups = "sd0_led_control_group";
+					function = "sd0_led_control_func";
+				};
+			};
+            pinctrl_sd1_led_control_default: sd1_led_control-default{
+				mux {
+					groups = "sd1_led_control_group";
+					function = "sd1_led_control_func";
+				};
+			};
+            pinctrl_i2c6_default: i2c6-default{
+				mux {
+					groups = "i2c6_group";
+					function = "i2c6_func";
+				};
+			};
+            pinctrl_i2c7_default: i2c7-default{
+				mux {
+					groups = "i2c7_group";
+					function = "i2c7_func";
+				};
+			};
+            pinctrl_i2c9_default: i2c9-default{
+				mux {
+					groups = "i2c9_group";
+					function = "i2c9_func";
+				};
+			};
+            pinctrl_pwm1_default: pwm1-default{
+				mux {
+					groups = "pwm1_group";
+					function = "pwm1_func";
+				};
+			};
+            pinctrl_pwm2_default: pwm2-default{
+				mux {
+					groups = "pwm2_group";
+					function = "pwm2_func";
+				};
+			};
+            pinctrl_mipi_csi_xtrig_default: mipi_csi_xtrig-default{
+				mux {
+					groups = "mipi_csi_xtrig_group";
+					function = "mipi_csi_xtrig_func";
+				};
+			};
+
+            //func3
+            pinctrl_uart3_default: uart3-default{
+				mux {
+					groups = "uart3_group";
+					function = "uart3_func";
+				};
+			};
+            pinctrl_uart4_default: uart4-default{
+				mux {
+					groups = "uart4_group";
+					function = "uart4_func";
+				};
+			};
+
+            //gpio
+            pinctrl_gpio0_default: gpio0-default{
+				mux {
+					groups = "gpio0_group";
+					function = "gpio0_func";
+				};
+				conf {
+					groups = "gpio0_group";
+					input-enable = <1>;
+					bias-pull-up = <1>;
+				};
+			};
+            pinctrl_gpio1_default: gpio1-default{
+				mux {
+					groups = "gpio1_group";
+					function = "gpio1_func";
+				};
+			};
+            pinctrl_gpio2_default: gpio2-default{
+				mux {
+					groups = "gpio2_group";
+					function = "gpio2_func";
+				};
+			};
+            pinctrl_gpio3_default: gpio3-default{
+				mux {
+					groups = "gpio3_group";
+					function = "gpio3_func";
+				};
+			};
+            pinctrl_gpio4_default: gpio4-default{
+				mux {
+					groups = "gpio4_group";
+					function = "gpio4_func";
+				};
+			};
+            pinctrl_gpio5_default: gpio5-default{
+				mux {
+					groups = "gpio5_group";
+					function = "gpio5_func";
+				};
+				conf {
+					groups = "gpio5_group";
+					input-enable = <1>;
+					bias-pull-up = <1>;
+				};
+			};
+            pinctrl_gpio6_default: gpio6-default{
+				mux {
+					groups = "gpio6_group";
+					function = "gpio6_func";
+				};
+				conf {
+					groups = "gpio6_group";
+					input-enable = <1>;
+					bias-pull-down = <1>;
+				};
+			};
+            pinctrl_gpio7_default: gpio7-default{
+				mux {
+					groups = "gpio7_group";
+					function = "gpio7_func";
+				};
+				conf {
+					groups = "gpio7_group";
+					input-enable = <1>;
+					bias-pull-down = <1>;
+				};
+			};
+            pinctrl_gpio8_default: gpio8-default{
+				mux {
+					groups = "gpio8_group";
+					function = "gpio8_func";
+				};
+				conf {
+					groups = "gpio8_group";
+					input-enable = <1>;
+					bias-pull-up = <1>;
+				};
+			};
+            pinctrl_gpio9_default: gpio9-default{
+				mux {
+					groups = "gpio9_group";
+					function = "gpio9_func";
+				};
+				conf {
+					groups = "gpio9_group";
+					input-enable = <1>;
+					bias-pull-up = <1>;
+				};
+			};
+            pinctrl_gpio10_default: gpio10-default{
+				mux {
+					groups = "gpio10_group";
+					function = "gpio10_func";
+				};
+				conf {
+					groups = "gpio10_group";
+					input-enable = <1>;
+					bias-pull-up = <1>;
+				};
+			};
+            pinctrl_gpio11_default: gpio11-default{
+				mux {
+					groups = "gpio11_group";
+					function = "gpio11_func";
+				};
+				conf {
+					groups = "gpio11_group";
+					input-enable = <1>;
+					bias-pull-up = <1>;
+				};
+			};
+            pinctrl_gpio12_default: gpio12-default{
+				mux {
+					groups = "gpio12_group";
+					function = "gpio12_func";
+				};
+			};
+            pinctrl_gpio13_default: gpio13-default{
+				mux {
+					groups = "gpio13_group";
+					function = "gpio13_func";
+				};
+			};
+            pinctrl_gpio14_default: gpio14-default{
+				mux {
+					groups = "gpio14_group";
+					function = "gpio14_func";
+				};
+			};
+            pinctrl_gpio15_default: gpio15-default{
+				mux {
+					groups = "gpio15_group";
+					function = "gpio15_func";
+				};
+			};
+            pinctrl_gpio16_default: gpio16-default{
+				mux {
+					groups = "gpio16_group";
+					function = "gpio16_func";
+				};
+				conf {
+					groups = "gpio16_group";
+					input-enable = <0>;
+					bias-pull-down = <1>;
+				};
+			};
+            pinctrl_gpio17_default: gpio17-default{
+				mux {
+					groups = "gpio17_group";
+					function = "gpio17_func";
+				};
+				conf {
+					groups = "gpio17_group";
+					input-enable = <1>;
+					bias-pull-down = <1>;
+				};
+			};
+            pinctrl_gpio18_default: gpio18-default{
+				mux {
+					groups = "gpio18_group";
+					function = "gpio18_func";
+				};
+				conf {
+					groups = "gpio18_group";
+					input-enable = <1>;
+					bias-pull-down = <1>;
+				};
+			};
+            pinctrl_gpio19_default: gpio19-default{
+				mux {
+					groups = "gpio19_group";
+					function = "gpio19_func";
+				};
+				conf {
+					groups = "gpio19_group";
+					input-enable = <1>;
+					bias-pull-down = <1>;
+				};
+			};
+            pinctrl_gpio20_default: gpio20-default{
+				mux {
+					groups = "gpio20_group";
+					function = "gpio20_func";
+				};
+				conf {
+					groups = "gpio20_group";
+					input-enable = <1>;
+					bias-pull-down = <1>;
+				};
+			};
+            pinctrl_gpio21_default: gpio21-default{
+				mux {
+					groups = "gpio21_group";
+					function = "gpio21_func";
+				};
+				conf {
+					groups = "gpio21_group";
+					input-enable = <1>;
+					bias-pull-down = <1>;
+				};
+			};
+            pinctrl_gpio22_default: gpio22-default{
+				mux {
+					groups = "gpio22_group";
+					function = "gpio22_func";
+				};
+			};
+            pinctrl_gpio23_default: gpio23-default{
+				mux {
+					groups = "gpio23_group";
+					function = "gpio23_func";
+				};
+			};
+            pinctrl_gpio24_default: gpio24-default{
+				mux {
+					groups = "gpio24_group";
+					function = "gpio24_func";
+				};
+			};
+            pinctrl_gpio25_default: gpio25-default{
+				mux {
+					groups = "gpio25_group";
+					function = "gpio25_func";
+				};
+			};
+            pinctrl_gpio26_default: gpio26-default{
+				mux {
+					groups = "gpio26_group";
+					function = "gpio26_func";
+				};
+			};
+            pinctrl_gpio27_default: gpio27-default{
+				mux {
+					groups = "gpio27_group";
+					function = "gpio27_func";
+				};
+			};
+            pinctrl_gpio28_default: gpio28-default{
+				mux {
+					groups = "gpio28_group";
+					function = "gpio28_func";
+				};
+				conf {
+					groups = "gpio28_group";
+					input-enable = <1>;
+					bias-pull-up = <1>;
+				};
+			};
+            pinctrl_gpio29_default: gpio29-default{
+				mux {
+					groups = "gpio29_group";
+					function = "gpio29_func";
+				};
+			};
+            pinctrl_gpio30_default: gpio30-default{
+				mux {
+					groups = "gpio30_group";
+					function = "gpio30_func";
+				};
+			};
+            pinctrl_gpio31_default: gpio31-default{
+				mux {
+					groups = "gpio31_group";
+					function = "gpio31_func";
+				};
+			};
+            pinctrl_gpio32_default: gpio32-default{
+				mux {
+					groups = "gpio32_group";
+					function = "gpio32_func";
+				};
+			};
+            pinctrl_gpio33_default: gpio33-default{
+				mux {
+					groups = "gpio33_group";
+					function = "gpio33_func";
+				};
+			};
+            pinctrl_gpio34_default: gpio34-default{
+				mux {
+					groups = "gpio34_group";
+					function = "gpio34_func";
+				};
+			};
+            pinctrl_gpio35_default: gpio35-default{
+				mux {
+					groups = "gpio35_group";
+					function = "gpio35_func";
+				};
+				conf {
+					groups = "gpio35_group";
+					input-enable = <1>;
+					bias-pull-down = <1>;
+				};
+			};
+            pinctrl_gpio36_default: gpio36-default{
+				mux {
+					groups = "gpio36_group";
+					function = "gpio36_func";
+				};
+				conf {
+					groups = "gpio36_group";
+					input-enable = <1>;
+					bias-pull-down = <1>;
+				};
+			};
+            pinctrl_gpio37_default: gpio37-default{
+				mux {
+					groups = "gpio37_group";
+					function = "gpio37_func";
+				};
+				conf {
+					groups = "gpio37_group";
+					input-enable = <1>;
+					bias-pull-down = <1>;
+				};
+			};
+            pinctrl_gpio38_default: gpio38-default{
+				mux {
+					groups = "gpio38_group";
+					function = "gpio38_func";
+				};
+				conf {
+					groups = "gpio38_group";
+					input-enable = <1>;
+					bias-pull-down = <1>;
+				};
+			};
+            pinctrl_gpio39_default: gpio39-default{
+				mux {
+					groups = "gpio39_group";
+					function = "gpio39_func";
+				};
+				conf {
+					groups = "gpio39_group";
+					input-enable = <1>;
+					bias-pull-down = <1>;
+				};
+			};
+            pinctrl_gpio40_default: gpio40-default{
+				mux {
+					groups = "gpio40_group";
+					function = "gpio40_func";
+				};
+				conf {
+					groups = "gpio40_group";
+					input-enable = <1>;
+					bias-pull-down = <1>;
+				};
+			};
+            pinctrl_gpio41_default: gpio41-default{
+				mux {
+					groups = "gpio41_group";
+					function = "gpio41_func";
+				};
+			};
+            pinctrl_gpio42_default: gpio42-default{
+				mux {
+					groups = "gpio42_group";
+					function = "gpio42_func";
+				};
+				conf {
+					groups = "gpio42_group";
+					input-enable = <1>;
+					bias-pull-down = <1>;
+				};
+			};
+            pinctrl_gpio43_default: gpio43-default{
+				mux {
+					groups = "gpio43_group";
+					function = "gpio43_func";
+				};
+			};
+            pinctrl_gpio44_default: gpio44-default{
+				mux {
+					groups = "gpio44_group";
+					function = "gpio44_func";
+				};
+			};
+            pinctrl_gpio45_default: gpio45-default{
+				mux {
+					groups = "gpio45_group";
+					function = "gpio45_func";
+				};
+			};
+            pinctrl_gpio46_default: gpio46-default{
+				mux {
+					groups = "gpio46_group";
+					function = "gpio46_func";
+				};
+				conf {
+					groups = "gpio46_group";
+					input-enable = <1>;
+					bias-pull-down = <1>;
+				};
+			};
+            pinctrl_gpio47_default: gpio47-default{
+				mux {
+					groups = "gpio47_group";
+					function = "gpio47_func";
+				};
+				conf {
+					groups = "gpio47_group";
+					input-enable = <1>;
+					bias-pull-down = <1>;
+				};
+			};
+            pinctrl_gpio48_default: gpio48-default{
+				mux {
+					groups = "gpio48_group";
+					function = "gpio48_func";
+				};
+			};
+            pinctrl_gpio49_default: gpio49-default{
+				mux {
+					groups = "gpio49_group";
+					function = "gpio49_func";
+				};
+			};
+            pinctrl_gpio50_default: gpio50-default{
+				mux {
+					groups = "gpio50_group";
+					function = "gpio50_func";
+				};
+			};
+            pinctrl_gpio51_default: gpio51-default{
+				mux {
+					groups = "gpio51_group";
+					function = "gpio51_func";
+				};
+			};
+            pinctrl_gpio52_default: gpio52-default{
+				mux {
+					groups = "gpio52_group";
+					function = "gpio52_func";
+				};
+				conf {
+					groups = "gpio52_group";
+					input-enable = <1>;
+					bias-pull-down = <1>;
+				};
+			};
+            pinctrl_gpio53_default: gpio53-default{
+				mux {
+					groups = "gpio53_group";
+					function = "gpio53_func";
+				};
+				conf {
+					groups = "gpio53_group";
+					input-enable = <1>;
+					bias-pull-down = <1>;
+				};
+			};
+            pinctrl_gpio54_default: gpio54-default{
+				mux {
+					groups = "gpio54_group";
+					function = "gpio54_func";
+				};
+			};
+            pinctrl_gpio55_default: gpio55-default{
+				mux {
+					groups = "gpio55_group";
+					function = "gpio55_func";
+				};
+			};
+            pinctrl_gpio56_default: gpio56-default{
+				mux {
+					groups = "gpio56_group";
+					function = "gpio56_func";
+				};
+			};
+            pinctrl_gpio57_default: gpio57-default{
+				mux {
+					groups = "gpio57_group";
+					function = "gpio57_func";
+				};
+			};
+            pinctrl_gpio58_default: gpio58-default{
+				mux {
+					groups = "gpio58_group";
+					function = "gpio58_func";
+				};
+			};
+            pinctrl_gpio59_default: gpio59-default{
+				mux {
+					groups = "gpio59_group";
+					function = "gpio59_func";
+				};
+			};
+            pinctrl_gpio60_default: gpio60-default{
+				mux {
+					groups = "gpio60_group";
+					function = "gpio60_func";
+				};
+			};
+            pinctrl_gpio61_default: gpio61-default{
+				mux {
+					groups = "gpio61_group";
+					function = "gpio61_func";
+				};
+			};
+            pinctrl_gpio62_default: gpio62-default{
+				mux {
+					groups = "gpio62_group";
+					function = "gpio62_func";
+				};
+			};
+            pinctrl_gpio63_default: gpio63-default{
+				mux {
+					groups = "gpio63_group";
+					function = "gpio63_func";
+				};
+			};
+            pinctrl_gpio64_default: gpio64-default{
+				mux {
+					groups = "gpio64_group";
+					function = "gpio64_func";
+				};
+				conf {
+					groups = "gpio64_group";
+					input-enable = <1>;
+					bias-pull-down = <1>;
+				};
+			};
+            pinctrl_gpio65_default: gpio65-default{
+				mux {
+					groups = "gpio65_group";
+					function = "gpio65_func";
+				};
+				conf {
+					groups = "gpio65_group";
+					input-enable = <1>;
+					bias-pull-down = <1>;
+				};
+			};
+            pinctrl_gpio66_default: gpio66-default{
+				mux {
+					groups = "gpio66_group";
+					function = "gpio66_func";
+				};
+				conf {
+					groups = "gpio66_group";
+					input-enable = <1>;
+					bias-pull-down = <1>;
+				};
+			};
+            pinctrl_gpio67_default: gpio67-default{
+				mux {
+					groups = "gpio67_group";
+					function = "gpio67_func";
+				};
+				conf {
+					groups = "gpio67_group";
+					input-enable = <1>;
+					bias-pull-down = <1>;
+				};
+			};
+            pinctrl_gpio68_default: gpio68-default{
+				mux {
+					groups = "gpio68_group";
+					function = "gpio68_func";
+				};
+			};
+            pinctrl_gpio69_default: gpio69-default{
+				mux {
+					groups = "gpio69_group";
+					function = "gpio69_func";
+				};
+			};
+            pinctrl_gpio70_default: gpio70-default{
+				mux {
+					groups = "gpio70_group";
+					function = "gpio70_func";
+				};
+			};
+            pinctrl_gpio71_default: gpio71-default{
+				mux {
+					groups = "gpio71_group";
+					function = "gpio71_func";
+				};
+			};
+            pinctrl_gpio72_default: gpio72-default{
+				mux {
+					groups = "gpio72_group";
+					function = "gpio72_func";
+				};
+			};
+            pinctrl_gpio73_default: gpio73-default{
+				mux {
+					groups = "gpio73_group";
+					function = "gpio73_func";
+				};
+			};
+            pinctrl_gpio74_default: gpio74-default{
+				mux {
+					groups = "gpio74_group";
+					function = "gpio74_func";
+				};
+			};
+            pinctrl_gpio75_default: gpio75-default{
+				mux {
+					groups = "gpio75_group";
+					function = "gpio75_func";
+				};
+			};
+            pinctrl_gpio76_default: gpio76-default{
+				mux {
+					groups = "gpio76_group";
+					function = "gpio76_func";
+				};
+			};
+            pinctrl_gpio77_default: gpio77-default{
+				mux {
+					groups = "gpio77_group";
+					function = "gpio77_func";
+				};
+			};
+            pinctrl_gpio78_default: gpio78-default{
+				mux {
+					groups = "gpio78_group";
+					function = "gpio78_func";
+				};
+			};
+            pinctrl_gpio79_default: gpio79-default{
+				mux {
+					groups = "gpio79_group";
+					function = "gpio79_func";
+				};
+			};
+            pinctrl_gpio80_default: gpio80-default{
+				mux {
+					groups = "gpio80_group";
+					function = "gpio80_func";
+				};
+			};
+            pinctrl_gpio81_default: gpio81-default{
+				mux {
+					groups = "gpio81_group";
+					function = "gpio81_func";
+				};
+			};
+            pinctrl_gpio82_default: gpio82-default{
+				mux {
+					groups = "gpio82_group";
+					function = "gpio82_func";
+				};
+			};
+            pinctrl_gpio83_default: gpio83-default{
+				mux {
+					groups = "gpio83_group";
+					function = "gpio83_func";
+				};
+			};
+            pinctrl_gpio84_default: gpio84-default{
+				mux {
+					groups = "gpio84_group";
+					function = "gpio84_func";
+				};
+			};
+            pinctrl_gpio85_default: gpio85-default{
+				mux {
+					groups = "gpio85_group";
+					function = "gpio85_func";
+				};
+			};
+            pinctrl_gpio86_default: gpio86-default{
+				mux {
+					groups = "gpio86_group";
+					function = "gpio86_func";
+				};
+			};
+            pinctrl_gpio87_default: gpio87-default{
+				mux {
+					groups = "gpio87_group";
+					function = "gpio87_func";
+				};
+			};
+            pinctrl_gpio88_default: gpio88-default{
+				mux {
+					groups = "gpio88_group";
+					function = "gpio88_func";
+				};
+			};
+            pinctrl_gpio89_default: gpio89-default{
+				mux {
+					groups = "gpio89_group";
+					function = "gpio89_func";
+				};
+			};
+            pinctrl_gpio90_default: gpio90-default{
+				mux {
+					groups = "gpio90_group";
+					function = "gpio90_func";
+				};
+			};
+            pinctrl_gpio91_default: gpio91-default{
+				mux {
+					groups = "gpio91_group";
+					function = "gpio91_func";
+				};
+			};
+            pinctrl_gpio92_default: gpio92-default{
+				mux {
+					groups = "gpio92_group";
+					function = "gpio92_func";
+				};
+				conf {
+					groups = "gpio92_group";
+					input-enable = <1>;
+					bias-pull-down = <1>;
+				};
+			};
+            pinctrl_gpio93_default: gpio93-default{
+				mux {
+					groups = "gpio93_group";
+					function = "gpio93_func";
+				};
+				conf {
+					groups = "gpio93_group";
+					input-enable = <1>;
+					bias-pull-down = <1>;
+				};
+			};
+            pinctrl_gpio94_default: gpio94-default{
+				mux {
+					groups = "gpio94_group";
+					function = "gpio94_func";
+				};
+				conf {
+					groups = "gpio94_group";
+					input-enable = <0>;
+					bias-pull-down = <1>;
+				};
+			};
+            pinctrl_gpio95_default: gpio95-default{
+				mux {
+					groups = "gpio95_group";
+					function = "gpio95_func";
+				};
+			};
+            pinctrl_gpio96_default: gpio96-default{
+				mux {
+					groups = "gpio96_group";
+					function = "gpio96_func";
+				};
+			};
+            pinctrl_gpio97_default: gpio97-default{
+				mux {
+					groups = "gpio97_group";
+					function = "gpio97_func";
+				};
+			};
+            pinctrl_gpio98_default: gpio98-default{
+				mux {
+					groups = "gpio98_group";
+					function = "gpio98_func";
+				};
+			};
+            pinctrl_gpio99_default: gpio99-default{
+				mux {
+					groups = "gpio99_group";
+					function = "gpio99_func";
+				};
+			};
+            pinctrl_gpio100_default: gpio100-default{
+				mux {
+					groups = "gpio100_group";
+					function = "gpio100_func";
+				};
+			};
+            pinctrl_gpio101_default: gpio101-default{
+				mux {
+					groups = "gpio101_group";
+					function = "gpio101_func";
+				};
+			};
+            pinctrl_gpio102_default: gpio102-default{
+				mux {
+					groups = "gpio102_group";
+					function = "gpio102_func";
+				};
+			};
+            pinctrl_gpio103_default: gpio103-default{
+				mux {
+					groups = "gpio103_group";
+					function = "gpio103_func";
+				};
+			};
+            pinctrl_gpio104_default: gpio104-default{
+				mux {
+					groups = "gpio104_group";
+					function = "gpio104_func";
+				};
+			};
+            pinctrl_gpio105_default: gpio105-default{
+				mux {
+					groups = "gpio105_group";
+					function = "gpio105_func";
+				};
+			};
+            pinctrl_gpio106_default: gpio106-default{
+				mux {
+					groups = "gpio106_group";
+					function = "gpio106_func";
+				};
+				conf {
+					groups = "gpio106_group";
+					input-enable = <0>;
+					bias-pull-down = <1>;
+				};
+			};
+            pinctrl_gpio107_default: gpio107-default{
+				mux {
+					groups = "gpio107_group";
+					function = "gpio107_func";
+				};
+				conf {
+					groups = "gpio107_group";
+					input-enable = <1>;
+					bias-pull-down = <1>;
+				};
+			};
+            pinctrl_gpio108_default: gpio108-default{
+				mux {
+					groups = "gpio108_group";
+					function = "gpio108_func";
+				};
+				conf {
+					groups = "gpio108_group";
+					input-enable = <1>;
+					bias-pull-down = <1>;
+				};
+			};
+            pinctrl_gpio109_default: gpio109-default{
+				mux {
+					groups = "gpio109_group";
+					function = "gpio109_func";
+				};
+				conf {
+					groups = "gpio109_group";
+					input-enable = <1>;
+					bias-pull-down = <1>;
+				};
+			};
+            pinctrl_gpio110_default: gpio110-default{
+				mux {
+					groups = "gpio110_group";
+					function = "gpio110_func";
+				};
+				conf {
+					groups = "gpio110_group";
+					input-enable = <1>;
+					bias-pull-down = <1>;
+				};
+			};
+            pinctrl_gpio111_default: gpio111-default{
+				mux {
+					groups = "gpio111_group";
+					function = "gpio111_func";
+				};
+				conf {
+					groups = "gpio111_group";
+					input-enable = <0>;
+					bias-pull-up = <1>;
+				};
+			};
+
+            //func6
+            pinctrl_csi_mon_out_default: csi_mon_out-default{
+				mux {
+					groups = "csi_mon_out_group";
+					function = "csi_mon_out_func";
+				};
+			};
+            pinctrl_csi_ocla_clk_default: csi_ocla_clk-default{
+				mux {
+					groups = "csi_ocla_clk_group";
+					function = "csi_ocla_clk_func";
+				};
+			};
+            pinctrl_csi_mon_out_valid_default: csi_mon_out_valid-default{
+				mux {
+					groups = "csi_mon_out_valid_group";
+					function = "csi_mon_out_valid_func";
+				};
+			};
+            pinctrl_csi_parity_error_default: csi_parity_error-default{
+				mux {
+					groups = "csi_parity_error_group";
+					function = "csi_parity_error_func";
+				};
+			};
+            pinctrl_csi_dtb_out_default: csi_dtb_out-default{
+				mux {
+					groups = "csi_dtb_out_group";
+					function = "csi_dtb_out_func";
+				};
+			};
+            pinctrl_csi_phy_sel_default: csi_phy_sel-default{
+				mux {
+					groups = "csi_phy_sel_group";
+					function = "csi_phy_sel_func";
+				};
+			};
+            pinctrl_vc_g2d0_debug_out_default: vc_g2d0_debug_out-default{
+				mux {
+					groups = "vc_g2d0_debug_out_group";
+					function = "vc_g2d0_debug_out_func";
+				};
+			};
+            pinctrl_vc_g2d1_debug_out_default: vc_g2d1_debug_out-default{
+				mux {
+					groups = "vc_g2d1_debug_out_group";
+					function = "vc_g2d1_debug_out_func";
+				};
+			};
+            pinctrl_sata_mpll_clk_default: sata_mpll_clk-default{
+				mux {
+					groups = "sata_mpll_clk_group";
+					function = "sata_mpll_clk_func";
+				};
+			};
+            pinctrl_sata_ref_repeat_clk_m_default: sata_ref_repeat_clk_m-default{
+				mux {
+					groups = "sata_ref_repeat_clk_m_group";
+					function = "sata_ref_repeat_clk_m_func";
+				};
+			};
+            pinctrl_sata_ref_repeat_clk_p_default: sata_ref_repeat_clk_p-default{
+				mux {
+					groups = "sata_ref_repeat_clk_p_group";
+					function = "sata_ref_repeat_clk_p_func";
+				};
+			};
+		};
+    };
+};
diff --git a/arch/riscv/boot/dts/eswin/eic7700-pine64-starpro64.dts b/arch/riscv/boot/dts/eswin/eic7700-pine64-starpro64.dts
new file mode 100644
index 000000000000..f1e623896631
--- /dev/null
+++ b/arch/riscv/boot/dts/eswin/eic7700-pine64-starpro64.dts
@@ -0,0 +1,874 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2024, Beijing ESWIN Computing Technology Co., Ltd.. All rights reserved.
+ * Copyright 2024 Icenowy Zheng <uwu@icenowy.me>
+ */
+
+/dts-v1/;
+
+#define RTCCLK_FREQ		1000000
+#define LSPCLK_FREQ		200000000
+
+/* If wanna enable ECC capability of DDR, should reserve highest zone of 1/8 all space for it */
+#define MEMORY_SIZE_H		0x4
+#define MEMORY_SIZE_L		0x0
+#define CMA_SIZE		0x20000000
+
+#include "eic7700.dtsi"
+#include "eic7700-pinctrl-common.dtsi"
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/leds/common.h>
+
+/* Clock frequency (in Hz) of the PCB crystal for rtcclk */
+
+/ {
+	#address-cells = <2>;
+	#size-cells = <2>;
+	model = "Pine64 StarPro64";
+	compatible = "sifive,hifive-unmatched-a00", "sifive,fu740-c000",
+		     "sifive,fu740", "eswin,eic7700";
+
+	aliases {
+		serial0 = &d0_uart0;
+		ethernet0 = &d0_gmac0;
+		ethernet1 = &d0_gmac1;
+		rtc0 = &die0_rtc;
+		rtc1 = &pcf_rtc;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+		opensbi_domain_config: domain-config {
+			compatible = "opensbi,domain,config";
+			system-suspend-test;
+		};
+	};
+
+	cpus {
+		timebase-frequency = <RTCCLK_FREQ>;
+	};
+
+	memory@80000000 {
+		device_type = "memory";
+		reg = <0x0 0x80000000 MEMORY_SIZE_H MEMORY_SIZE_L>;
+		numa-node-id = <0>;
+	};
+
+	memory@59000000 {
+		device_type = "memory";
+		reg = <0x0 0x59000000 0x0 0x400000>;
+		numa-node-id = <0>;
+	};
+
+	reserved-memory {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		linux,cma {
+			compatible = "shared-dma-pool";
+			reusable;
+			size = <0x0 CMA_SIZE>;
+			alignment = <0x0 0x1000>;
+			alloc-ranges = <0x0 0x80000000 MEMORY_SIZE_H MEMORY_SIZE_L>;
+			linux,cma-default;
+		};
+
+		npu0_reserved: sprammemory@59000000 {
+			no-map;
+			reg = <0x0 0x59000000 0x0 0x400000>;
+		};
+
+		lpcpu0_reserved: lpcpu@a0000000 {
+			no-map;
+			reg = <0x0 0xa0000000 0x0 0x100000>;
+		};
+
+		g2d_4GB_boundary_reserved_4k {
+			no-map;
+			reg = <0x0 0xfffff000 0x0 0x1000>;
+		};
+
+		g2d_8GB_boundary_reserved_4k {
+			no-map;
+			reg = <0x1 0xfffff000 0x0 0x1000>;
+		};
+
+		g2d_12GB_boundary_reserved_4k {
+			no-map;
+			reg = <0x2 0xfffff000 0x0 0x1000>;
+		};
+
+		mmz_nid_0_part_0 {
+			compatible = "eswin-reserve-memory";
+			reg = <0x3 0x0 0x1 0x80000000>;
+			no-map;
+		};
+	};
+
+	leds {
+		compatible = "gpio-leds";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_gpio27_default &pinctrl_gpio62_default>;
+
+		power {
+			gpios = <&portb 30 GPIO_ACTIVE_HIGH>;
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_WHITE>;
+			linux,default-trigger = "default-on";
+		};
+
+		status {
+			gpios = <&porta 27 GPIO_ACTIVE_HIGH>;
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_RED>;
+			linux,default-trigger = "heartbeat";
+		};
+	};
+};
+
+&d0_clock {
+	status = "okay";
+};
+
+&d0_reset {
+	status = "okay";
+};
+
+&d0_pmu {
+	status = "okay";
+};
+
+&ddr0 {
+	status = "okay";
+};
+
+&ddr1 {
+	status = "okay";
+};
+
+&d0_cfg_noc {
+	status = "okay";
+};
+
+&d0_llc_noc {
+	status = "okay";
+	stat,0 = "TracePort:ddr0_p0_req";
+	stat,1 = "TracePort:ddr1_p0_req";
+	//latency,0 = "TracePort:llcnoc_trans_probe";
+	//pending,0 = "TracePort:llcnoc_trans_probe";
+};
+
+&d0_sys_noc {
+	status = "okay";
+
+	//eswin,DSPT-qos-owner;
+	//eswin,NPU-qos-owner;
+	//eswin,SPISLV_TBU3-qos-owner;
+
+	stat,0 = "TracePort:ddr0_p1_req",
+		 "InitFlow:mcput_snoc_mp/I/0";
+
+	stat,1 = "TracePort:ddr0_p2_req",
+		 "InitFlow:dspt_snoc/I/0",
+		 "AddrBase:0x81000000", "AddrSize:0x30",
+		 "Opcode:RdWrLockUrg", "Status:ReqRsp", "Length:0x8000", "Urgency:0x0";
+
+	stat,2 = "TracePort:ddr1_p1_req",
+		 "Status:Req", "AddrSize:0x28";
+
+	stat,3 = "TracePort:ddr1_p2_req";
+
+	latency,0 = "TracePort:sysnoc_trans_probe_0", "AddrSize:0x0";
+	latency,1 = "TracePort:sysnoc_trans_probe_1","Mode:latency","AddrBase:0x82000000","AddrSize:0x28","Opcode:RdWr";
+	//latency,2 = "TracePort:sysnoc_trans_probe_2";
+
+	//pending,0 = "TracePort:sysnoc_trans_probe_0";
+	//pending,1 = "TracePort:sysnoc_trans_probe_1","Mode:latency","AddrBase:0x82000000","AddrSize:0x0","Opcode:RdWr";
+	pending,0 = "TracePort:sysnoc_trans_probe_2", "AddrSize:0x3";
+};
+
+&d0_media_noc {
+	status = "okay";
+
+	//eswin,GPU-qos-owner;
+	//eswin,TBU2-qos-owner;
+	//eswin,VC-qos-owner;
+
+	stat,0 = "TracePort:ddr0_p3_req";
+	stat,1 = "TracePort:ddr1_p3_req";
+	//latency,0 = "TracePort:mnoc_trans_probe";
+	//pending,0 = "TracePort:mnoc_trans_probe";
+};
+
+&d0_realtime_noc {
+	status = "okay";
+
+	//eswin,TBU0-qos-owner;
+	//eswin,VO-qos-owner;
+
+	stat,0 = "TracePort:ddr0_p4_req";
+	stat,1 = "TracePort:ddr1_p4_req";
+	//latency,0 = "TracePort:rnoc_trans_probe";
+	//pending,0 = "TracePort:rnoc_trans_probe";
+};
+
+&d0_noc_wdt {
+	status = "okay";
+};
+
+&d0_ipc_scpu {
+	status = "okay";
+};
+
+&d0_lpcpu {
+	status = "okay";
+};
+
+&pcie {
+	status = "okay";
+};
+
+&d0_npu{
+	status = "okay";
+	npu-supply=<&npu_vcc1>;
+};
+
+&d0_dsp_subsys {
+	status = "okay";
+};
+
+&d0_dsp0 {
+	status = "okay";
+};
+
+&d0_dsp1 {
+	status = "okay";
+};
+
+&d0_dsp2 {
+	status = "okay";
+};
+
+&d0_dsp3 {
+	status = "okay";
+};
+
+&gpu0 {
+	status = "okay";
+};
+
+&gc820 {
+	status = "okay";
+};
+
+&vdec0 {
+	status = "okay";
+};
+
+&venc0 {
+	status = "okay";
+};
+
+&video_output {
+	status = "okay";
+};
+
+&dc {
+	status = "okay";
+	dc_out: port {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		dc_out_dsi: endpoint@0 {
+			reg = <0>;
+			remote-endpoint = <&dsi_input>;
+		};
+		dc_out_dpi1: endpoint@1 {
+			reg = <1>;
+			remote-endpoint = <&vd_input>;
+		};
+		dc_out_hdmi: endpoint@2 {
+			reg = <2>;
+			remote-endpoint = <&hdmi_in_dc>;
+		};
+	};
+};
+
+&dc_test {
+	status = "disabled";
+};
+
+&virtual_display {
+	status = "okay";
+	port {
+		vd_input: endpoint {
+			remote-endpoint = <&dc_out_dpi1>;
+		};
+	};
+};
+
+&dsi_output {
+    status = "okay";
+};
+
+&dsi_controller {
+	status = "okay";
+	ports {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		port@0 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0>;
+			dsi_input: endpoint {
+				remote-endpoint = <&dc_out_dsi>;
+			};
+		};
+		port@1 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <1>;
+			mipi_dsi_out: endpoint {
+				remote-endpoint = <&panel_in>;
+			};
+		};
+	};
+	dsi_panel:dsi_panel@0 {
+		compatible = "eswin,generic-panel";
+		reg = <0>;
+		dsi,format = <0>; //RGB888:0, RGB666:1, RGB565:3
+		dsi,lanes = <4>;
+		port {
+			panel_in: endpoint {
+				remote-endpoint = <&mipi_dsi_out>;
+			};
+		};
+	};
+};
+
+&dsi_panel {
+	status = "disabled";
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_gpio5_default &pinctrl_gpio111_default>;
+	backlight0-gpios = <&porta 5 GPIO_ACTIVE_HIGH>;
+	rst-gpios = <&portd 15 GPIO_ACTIVE_HIGH>;
+};
+
+&dw_hdmi {
+	status = "okay";
+	ports {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		port@0 {
+			reg = <0>;
+			hdmi_in_dc: endpoint@0 {
+				remote-endpoint = <&dc_out_hdmi>;
+			};
+		};
+		port@2 {
+			reg = <2>;
+			hdmi_in_i2s: endpoint@1 {
+				system-clock-frequency = <12288000>;
+				remote-endpoint = <&d0_i2s0_endpoint>;
+			};
+		};
+	};
+};
+
+&dw_hdmi_hdcp2 {
+    status = "okay";
+};
+
+&d0_i2s0 {
+	status = "okay";
+	d0_i2s0_port: port {
+		d0_i2s0_endpoint: endpoint {
+			remote-endpoint = <&hdmi_in_i2s>;
+			dai-format = "i2s";
+		};
+	};
+};
+
+&d0_i2s1 {
+	status = "okay";
+	d0_i2s1_port: port {
+		d0_i2s1_endpoint: endpoint {
+			remote-endpoint = <&d0_codec0_endpoint>;
+			dai-format = "i2s";
+		};
+	};
+};
+
+&d0_i2s2 {
+	status = "disabled";
+};
+
+&d0_graphcard0 {
+	status = "okay";
+	label = "Analog Audio-0";
+	dais = <&d0_i2s1_port>;
+};
+
+&d0_graphcard1 {
+	status = "okay";
+	label = "HDMI Audio";
+	dais = <&d0_i2s0_port>;
+};
+
+&d0_graphcard2 {
+        status = "disabled";
+};
+
+&isp_0 {
+	status = "okay";
+};
+
+&isp_1 {
+	status = "okay";
+};
+
+&dewarp {
+	status = "okay";
+};
+
+&mipi_dphy_rx {
+	status = "okay";
+};
+
+&csi_dma0 {
+	status = "okay";
+};
+
+&csi_dma1 {
+	status = "disabled";
+};
+
+&csi2_0 {
+	status = "okay";
+};
+
+&csi2_1 {
+	status = "disabled";
+};
+
+&sdhci_emmc {
+	/* emmc */
+	status = "okay";
+	/delete-property/ mmc-hs400-1_8v;
+	no-mmc-hs400;
+	delay_code = <0x37>;
+	drive-impedance-ohm = <50>;
+	enable-cmd-pullup;
+	enable-data-pullup;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_emmc_led_control_default>;
+	no-sdio;
+	no-sd;
+};
+
+&sdio0 {
+	/* sd card */
+	status = "okay";
+	delay_code = <0x70>;
+	drive-impedance-ohm = <33>;
+	enable-cmd-pullup;
+	enable-data-pullup;
+	no-sdio;
+	no-mmc;
+	disable-wp;
+};
+
+&sdio1 {
+	/* wifi module */
+	status = "okay";
+	delay_code = <0x29>;
+	drive-impedance-ohm = <33>;
+	enable-cmd-pullup;
+	enable-data-pullup;
+	keep-power-in-suspend;
+	non-removable;
+	no-sd;
+	no-mmc;
+};
+
+&d0_gmac0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_gpio94_default>;
+	rst-gpios = <&portc 30 GPIO_ACTIVE_LOW>;
+	eswin,rgmiisel = <&pinctrl 0x290 0x3>;
+	eswin,led-cfgs = <0x6100 0xa40 0x420>;
+	dly-param-1000m = <0x23232323 0x800c8023 0x0c0c0c0c>;
+	dly-param-100m = <0x50505050 0x803f8050 0x3f3f3f3f>;
+	dly-param-10m = <0 0 0>;
+	status = "okay";
+};
+
+&d0_gmac1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_gpio16_default>;
+	rst-gpios = <&porta 16 GPIO_ACTIVE_LOW>;
+	eswin,rgmiisel = <&pinctrl 0x294 0x3>;
+	eswin,led-cfgs = <0x6100 0xa40 0x420>;
+	dly-param-1000m = <0x23232323 0x800c8023 0x0c0c0c0c>;
+	dly-param-100m = <0x50505050 0x803f8050 0x3f3f3f3f>;
+	dly-param-10m = <0 0 0>;
+	status = "okay";
+};
+
+&d0_sata {
+	status = "disabled";
+};
+
+&d0_usbdrd3_0 {
+	status = "okay";
+};
+
+&d0_usbdrd_dwc3_0 {
+	status = "okay";
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_usb0_pwren_default>;
+	dr_mode = "host";
+	maximum-speed = "super-speed";
+};
+
+&d0_usbdrd3_1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_gpio43_default>;
+	status = "okay";
+	hub-rst-gpios = <&portb 11 GPIO_ACTIVE_HIGH>;
+};
+
+&d0_usbdrd_dwc3_1 {
+	status = "okay";
+	dr_mode = "host";
+	maximum-speed = "super-speed";
+};
+
+&d0_dmac0 {
+	status = "okay";
+};
+
+&d0_aon_dmac {
+	status = "okay";
+};
+
+&d0_uart0 {
+	/* debug */
+	status = "okay";
+};
+
+&d0_uart1 {
+	/* BT M.2 KEY-E */
+	status = "okay";
+};
+
+&d0_uart2 {
+	/* RS232 DB9 */
+	status = "okay";
+};
+
+&d0_uart3 {
+	/* unused */
+	status = "disabled";
+};
+
+&d0_uart4 {
+	/* unused */
+	status = "disabled";
+};
+
+&ssi0 {
+	/* spi flash */
+	status = "okay";
+	num-cs = <2>;
+	spi-flash@0 {
+		compatible = "winbond,w25q128fw",
+					"jedec,spi-nor";
+		reg = <0>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		spi-max-frequency = <4800000>;
+		rx-sample-delay-ns = <10>;
+	};
+	spi-flash@1 {
+		compatible = "winbond,w25q128fw",
+					"jedec,spi-nor";
+		reg = <1>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		spi-max-frequency = <4800000>;
+		rx-sample-delay-ns = <10>;
+	};
+};
+
+&ssi1 {
+	/* spi flash */
+	status = "disabled";
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_spi2_default>;
+	num-cs = <2>;
+	spi-flash@0 {
+		compatible = "winbond,w25q128fw",
+					"jedec,spi-nor";
+		reg = <0>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		spi-max-frequency = <4800000>;
+		rx-sample-delay-ns = <10>;
+	};
+	spi-flash@1 {
+		compatible = "winbond,w25q128fw",
+					"jedec,spi-nor";
+		reg = <1>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		spi-max-frequency = <4800000>;
+		rx-sample-delay-ns = <10>;
+	};
+};
+
+&bootspi {
+	/* spi flash */
+	status = "okay";
+	num-cs = <1>;
+	cs-gpios = <&portd 0 GPIO_ACTIVE_LOW>;
+	wp-gpios = <&portd 4 GPIO_ACTIVE_LOW>;
+	spi-flash@0 {
+		compatible = "winbond,w25q128jw",
+					"jedec,spi-nor";
+		reg = <0>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		spi-max-frequency = <4800000>;
+		rx-sample-delay-ns = <10>;
+	};
+};
+
+&d0_mbox0 {
+	status = "okay";
+};
+
+&d0_mbox1 {
+	status = "okay";
+};
+
+&d0_mbox2 {
+	status = "okay";
+};
+
+&d0_mbox3 {
+	status = "okay";
+};
+
+&d0_mbox4 {
+	status = "okay";
+};
+
+&d0_mbox5 {
+	status = "okay";
+};
+
+&d0_mbox6 {
+	status = "okay";
+};
+
+&d0_mbox7 {
+	status = "okay";
+};
+
+&fan_control {
+	status = "okay";
+	eswin,pwm_inverted;
+};
+
+&d0_i2c0 {
+	/* codec es8388 */
+	status = "okay";
+	d0_es8388_0: es8388-0@10 {
+		compatible = "eswin,es8388";
+		reg = <0x10>;
+		#sound-dai-cells = <0>;
+		port {
+			d0_codec0_endpoint: endpoint {
+				system-clock-frequency = <12288000>;
+				remote-endpoint = <&d0_i2s1_endpoint>;
+			};
+		};
+	};
+};
+
+&d0_i2c1 {
+	/* mpq8785 */
+	status = "okay";
+	mpq8785@10 {
+		compatible = "mps,mpq8785";
+		reg = <0x10>;
+		eswin,regulator_default-microvolt=<1000000>;
+		eswin,regulator_label = "supply vdd1", "npu vdd1", "npu current1", "npu temperature1";
+		label = "npu_vdd";
+		regulators{
+			npu_vcc1:npu_svcc{
+				regulator-name="NPU_SVCC";
+				regulator-min-microvolt=<700000>;
+				regulator-max-microvolt=<1100000>;
+				regulator-min-microamp=<20000000>;
+				regulator-max-microamp=<40000000>;
+				regulator-ov-protection-microvolt=<1100000>;
+				regulator-always-on;
+			};
+		};
+	};
+};
+
+&d0_i2c2 {
+	/* mipi dsi */
+	status = "disabled";
+};
+
+&d0_i2c3 {
+	/* mipi csi0/csi1 */
+	status = "okay";
+};
+
+&d0_i2c4 {
+	/* mipi csi2/csi3 */
+	status = "disabled";
+};
+
+&d0_i2c5 {
+	/* mipi csi4/csi5 */
+	status = "disabled";
+};
+
+&d0_i2c6 {
+	/* unused */
+	status = "disabled";
+};
+
+&d0_i2c7 {
+	/* unused */
+	status = "disabled";
+};
+
+&d0_i2c8 {
+	/* unused */
+	status = "disabled";
+};
+
+&d0_i2c9 {
+	/* unused */
+	status = "disabled";
+};
+
+&d0_aon_i2c0 {
+	/* temp sensor & rtc */
+	status = "okay";
+	eswin,syscfg = <&d0_sys_con 0x3C0 16>;
+	pcf_rtc:rtc@51 {
+		compatible = "nxp,pcf8563";
+		reg = <0x51>;
+	};
+};
+
+&pwm0 {
+	/* fan */
+	status = "okay";
+};
+
+&pvt0 {
+	status = "okay";
+};
+
+&pvt1 {
+	status = "okay";
+};
+
+&wdt0 {
+	status = "disabled";
+};
+
+&wdt1 {
+	status = "disabled";
+};
+
+&wdt2 {
+	status = "disabled";
+};
+
+&wdt3 {
+	status = "disabled";
+};
+
+&die0_rtc {
+	status = "okay";
+};
+
+&timer0 {
+	status = "okay";
+};
+
+&timer1 {
+	status = "okay";
+};
+
+&timer2 {
+	status = "okay";
+};
+
+&timer3 {
+	status = "okay";
+};
+
+&pinctrl {
+	status = "okay";
+};
+
+/* GPIO Function Description
+
+	gpio0   : pcie prstn(I)
+	gpio6   : system key(broken now)(I)
+	gpio10  : dsi touch interrupt(I)
+	gpio11  : host wake wlan(O)
+	gpio12  : tf card power on/off(O)
+	gpio14  : bt wake host(I)
+	gpio15  : wlan wake host(I)
+	gpio16  : gphy1 resetn(O)
+	gpio27  : status LED(originally SATA LED, SATA not used)(O)
+	gpio28  : head phone plug/unplug detection1(I)
+	gpio62  : power LED(O)
+	gpio94  : gphy0 resetn(O)
+	gpio106 : touch reset(O)
+*/
+
+&gpio0 {
+	status = "okay";
+};
+&dev_llc_d0{
+	/* apply_npu_1G_freq; */
+	npu-supply=<&npu_vcc1>;
+	apply_npu_high_freq;
+};
+
+&d0_cpu_opp_table {
+	opp-1500000000 {
+		opp-hz = /bits/ 64 <CLK_FREQ_1500M>;
+		opp-microvolt = <900000>;
+		clock-latency-ns = <70000>;
+	};
+	opp-1600000000 {
+		opp-hz = /bits/ 64 <CLK_FREQ_1600M>;
+		opp-microvolt = <900000>;
+		clock-latency-ns = <70000>;
+	};
+	opp-1700000000 {
+		opp-hz = /bits/ 64 <CLK_FREQ_1700M>;
+		opp-microvolt = <900000>;
+		clock-latency-ns = <70000>;
+	};
+	opp-1800000000 {
+		opp-hz = /bits/ 64 <CLK_FREQ_1800M>;
+		opp-microvolt = <900000>;
+		clock-latency-ns = <70000>;
+	};
+};
diff --git a/arch/riscv/boot/dts/eswin/eic7700.dtsi b/arch/riscv/boot/dts/eswin/eic7700.dtsi
new file mode 100644
index 000000000000..5832adc1aaa2
--- /dev/null
+++ b/arch/riscv/boot/dts/eswin/eic7700.dtsi
@@ -0,0 +1,2081 @@
+﻿// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Include file for Die0 System peripherals of Eswin EIC770x family SoC.
+ *
+ * Copyright 2024, Beijing ESWIN Computing Technology Co., Ltd.. All rights reserved.
+ * SPDX-License-Identifier: GPL-2.0
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, version 2.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <https://www.gnu.org/licenses/>.
+ */
+
+#include "eic7700-arch.dtsi"
+#include <dt-bindings/memory/eic7700-sid.h>
+#include <dt-bindings/mailbox/eswin-mailbox.h>
+#include <dt-bindings/reset/eic7700-syscrg.h>
+#include <dt-bindings/clock/eic7700-clock.h>
+#include <dt-bindings/interconnect/eic7700.h>
+#include <dt-bindings/riscv/physical-memory.h>
+
+/ {
+	riscv,physical-memory-regions =
+		<0x000 0x00000000 0x200 0x00000000 (PMA_RW | PMA_IO) 0x0>,
+		<0x000 0x80000000 0x00f 0x80000000 (PMA_RWXA | PMA_NONCOHERENT_MEMORY) 0x0>,
+		<0x0c0 0x00000000 0x010 0x00000000 (PMA_RWX | PMA_NONCACHEABLE_MEMORY | PMR_ALIAS(1)) 0x0>;
+
+    compatible = "eswin,eic7700";
+	d0_cpu_opp_table: opp-table0 {
+		compatible = "operating-points-v2";
+		opp-shared;
+
+		opp-24000000 {
+			opp-hz = /bits/ 64 <CLK_FREQ_24M>;
+			opp-microvolt = <800000>;
+			clock-latency-ns = <70000>;
+		};
+		opp-100000000 {
+			opp-hz = /bits/ 64 <CLK_FREQ_100M>;
+			opp-microvolt = <800000>;
+			clock-latency-ns = <70000>;
+		};
+		opp-200000000 {
+			opp-hz = /bits/ 64 <CLK_FREQ_200M>;
+			opp-microvolt = <800000>;
+			clock-latency-ns = <70000>;
+		};
+		opp-400000000 {
+			opp-hz = /bits/ 64 <CLK_FREQ_400M>;
+			opp-microvolt = <800000>;
+			clock-latency-ns = <70000>;
+		};
+		opp-500000000 {
+			opp-hz = /bits/ 64 <CLK_FREQ_500M>;
+			opp-microvolt = <800000>;
+			clock-latency-ns = <70000>;
+		};
+		opp-600000000 {
+			opp-hz = /bits/ 64 <CLK_FREQ_600M>;
+			opp-microvolt = <800000>;
+			clock-latency-ns = <70000>;
+		};
+		opp-700000000 {
+			opp-hz = /bits/ 64 <CLK_FREQ_700M>;
+			opp-microvolt = <800000>;
+			clock-latency-ns = <70000>;
+		};
+		opp-800000000 {
+			opp-hz = /bits/ 64 <CLK_FREQ_800M>;
+			opp-microvolt = <800000>;
+			clock-latency-ns = <70000>;
+		};
+		opp-900000000 {
+			opp-hz = /bits/ 64 <CLK_FREQ_900M>;
+			opp-microvolt = <800000>;
+			clock-latency-ns = <70000>;
+		};
+		opp-1000000000 {
+			opp-hz = /bits/ 64 <CLK_FREQ_1000M>;
+			opp-microvolt = <800000>;
+			clock-latency-ns = <70000>;
+		};
+		opp-1200000000 {
+			opp-hz = /bits/ 64 <CLK_FREQ_1200M>;
+			opp-microvolt = <800000>;
+			clock-latency-ns = <70000>;
+		};
+		opp-1300000000 {
+			opp-hz = /bits/ 64 <CLK_FREQ_1300M>;
+			opp-microvolt = <800000>;
+			clock-latency-ns = <70000>;
+		};
+		opp-1400000000 {
+			opp-hz = /bits/ 64 <CLK_FREQ_1400M>;
+			opp-microvolt = <800000>;
+			clock-latency-ns = <70000>;
+		};
+	};
+};
+
+&SOC {
+		dma-noncoherent;
+
+		d0_uart0: serial@0x50900000 {
+			compatible = "snps,dw-apb-uart";
+			reg = <0x0 0x50900000 0x0 0x10000>;
+			clock-frequency = <LSPCLK_FREQ>;
+			interrupt-parent = <&plic0>;
+			interrupts = <UART0_INT>;
+			reg-shift = <2>;
+			reg-io-width = <4>;
+			numa-node-id = <0>;
+		};
+
+		d0_uart1: serial@0x50910000 {
+			compatible = "snps,dw-apb-uart";
+			reg = <0x0 0x50910000 0x0 0x10000>;
+			clock-frequency = <LSPCLK_FREQ>;
+			interrupt-parent = <&plic0>;
+			interrupts = <UART1_INT>;
+			reg-shift = <2>;
+			reg-io-width = <4>;
+			numa-node-id = <0>;
+		};
+
+		d0_uart2: serial@0x50920000 {
+			compatible = "snps,dw-apb-uart";
+			reg = <0x0 0x50920000 0x0 0x10000>;
+			clock-frequency = <LSPCLK_FREQ>;
+			interrupt-parent = <&plic0>;
+			interrupts = <UART2_INT>;
+			reg-shift = <2>;
+			reg-io-width = <4>;
+			numa-node-id = <0>;
+			status = "disabled";
+		};
+
+		d0_uart3: serial@0x50930000 {
+			compatible = "snps,dw-apb-uart";
+			reg = <0x0 0x50930000 0x0 0x10000>;
+			clock-frequency = <LSPCLK_FREQ>;
+			interrupt-parent = <&plic0>;
+			interrupts = <UART3_INT>;
+			reg-shift = <2>;
+			reg-io-width = <4>;
+			numa-node-id = <0>;
+			status = "disabled";
+		};
+
+		d0_uart4: serial@0x50940000 {
+			compatible = "snps,dw-apb-uart";
+			reg = <0x0 0x50940000 0x0 0x10000>;
+			clock-frequency = <LSPCLK_FREQ>;
+			interrupt-parent = <&plic0>;
+			interrupts = <UART4_INT>;
+			reg-shift = <2>;
+			reg-io-width = <4>;
+			numa-node-id = <0>;
+			status = "disabled";
+		};
+
+		d0_sys_con: scu_sys_con@0x51810000 {
+			compatible = "eswin,eic7700-scu-sys-con", "syscon", "simple-mfd";
+			#syscon-cells = <2>;
+			#size-cells = <2>;
+			reg = <0x0 0x51810000 0x0 0x8000>;
+			numa-node-id = <0>;
+			d0_noc_wdt:noc@51810324 {
+				compatible = "eswin,eic7700-noc-wdt";
+				interrupt-parent = <&plic0>;
+				interrupts = <392>, <393>, <394>, <395>,
+						<396>, <397>, <398>, <399>, <400>,
+						<401>, <402>, <403>, <404>, <405>,
+						<406>, <407>, <408>, <409>, <410>,
+						<411>, <412>, <413>, <414>, <415>,
+						<416>, <417>, <418>, <419>, <420>,
+						<421>, <422>, <423>, <424>, <425>,
+						<426>;
+				eswin,syscrg_csr = <&d0_sys_crg 0x100 0xffff>; //timeout paramerter
+				status = "disabled";
+			};
+		};
+
+		d0_sys_crg: sys-crg@51828000 {
+			compatible = "eswin,eic7700-sys-crg", "syscon", "simple-mfd";
+			reg = <0x000000 0x51828000 0x000000 0x80000>;
+			numa-node-id = <0>;
+			d0_reset: reset-controller {
+				compatible = "eswin,eic7700-reset";
+				#reset-cells = <2>;
+			};
+			d0_clock: clock-controller {
+				compatible = "eswin,eic7700-clock";
+				#clock-cells = <1>;
+			};
+		};
+
+		hfclk: hfclk {
+			#clock-cells = <0>;
+			compatible = "fixed-clock";
+			clock-frequency = <LSPCLK_FREQ>;
+			clock-output-names = "hfclk";
+		};
+
+		d0_hsp_sp_csr: hsp_sp_top_csr@0x50440000 {
+			compatible = "eswin,eic7700-hsp-sp-csr", "syscon";
+			#size-cells = <2>;
+			reg = <0x0 0x50440000 0x0 0x2000>;
+		};
+
+		d0_pmu: power-controller@51808000 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "eswin,eic7700-pmu-controller";
+			reg = <0x0 0x51808000 0x0 0x8000>;
+			numa-node-id = <0>;
+			d0_pmu_pcie: eic7700-pmu-controller-port@0 {
+				compatible = "eswin,eic7700-pmu-controller-port";
+				reg_base = <0x0>;
+				power_status = <1>;
+				power_delay = <6 6 3 3>;
+				clock_delay = <4 2 2 2>;
+				reset_delay = <2 4 2 2>;
+				clamp_delay = <3 3 2 2>;
+				label = "D0_PCIE";
+			};
+			d0_pmu_dsp1: eic7700-pmu-controller-port@40 {
+				compatible = "eswin,eic7700-pmu-controller-port";
+				reg_base = <0x40>;
+				power_status = <1>;
+				power_delay = <6 6 3 3>;
+				clock_delay = <4 2 2 2>;
+				reset_delay = <2 4 2 2>;
+				clamp_delay = <3 3 2 2>;
+				label = "D0_DSP1";
+			};
+			d0_pmu_vi: eic7700-pmu-controller-port@80 {
+				compatible = "eswin,eic7700-pmu-controller-port";
+				reg_base = <0x80>;
+				power_status = <1>;
+				power_delay = <6 6 3 3>;
+				clock_delay = <4 2 2 2>;
+				reset_delay = <2 4 2 2>;
+				clamp_delay = <3 3 2 2>;
+				label = "D0_VI";
+			};
+			d0_pmu_vo: eic7700-pmu-controller-port@c0 {
+				compatible = "eswin,eic7700-pmu-controller-port";
+				reg_base = <0xc0>;
+				power_status = <1>;
+				power_delay = <6 6 3 3>;
+				clock_delay = <4 2 2 2>;
+				reset_delay = <2 4 2 2>;
+				clamp_delay = <3 3 2 2>;
+				label = "D0_VO";
+			};
+			d0_pmu_codec: eic7700-pmu-controller-port@140 {
+				compatible = "eswin,eic7700-pmu-controller-port";
+				reg_base = <0x140>;
+				power_status = <1>;
+				power_delay = <6 6 3 3>;
+				clock_delay = <4 2 2 2>;
+				reset_delay = <2 4 2 2>;
+				clamp_delay = <3 3 2 2>;
+				label = "D0_CODEC";
+			};
+			d0_pmu_dsp2: eic7700-pmu-controller-port@200 {
+				compatible = "eswin,eic7700-pmu-controller-port";
+				reg_base = <0x200>;
+				power_status = <1>;
+				power_delay = <6 6 3 3>;
+				clock_delay = <4 2 2 2>;
+				reset_delay = <2 4 2 2>;
+				clamp_delay = <3 3 2 2>;
+				label = "D0_DSP2";
+			};
+			d0_pmu_dsp3: eic7700-pmu-controller-port@240 {
+				compatible = "eswin,eic7700-pmu-controller-port";
+				reg_base = <0x240>;
+				power_status = <1>;
+				power_delay = <6 6 3 3>;
+				clock_delay = <4 2 2 2>;
+				reset_delay = <2 4 2 2>;
+				clamp_delay = <3 3 2 2>;
+				label = "D0_DSP3";
+			};
+		};
+
+		d0_dmac0: dma-controller-hsp@0x50430000 {
+			compatible = "snps,axi-dma-1.01a";
+			reg = <0x0 0x50430000 0x0 0x10000>;
+			interrupt-parent = <&plic0>;
+			interrupts = <57>;
+			#dma-cells = <2>; // change dma-cells value <1> to <2>, to support peripheral selection dma-controller,See the parameter dmas for details;
+			clocks = <&d0_clock EIC7700_CLK_HSP_DMA0_CLK>;
+			clock-names = "core-clk";
+			resets = <&d0_reset HSPDMA_RST_CTRL SW_HSP_DMA0_RSTN>,
+				<&d0_reset HSPDMA_RST_CTRL SW_HSP_DMA_PRSTN>;
+			reset-names = "arst", "prst";
+			dma-channels = <12>;
+			snps,dma-masters = <1>;
+			snps,priority = <0 1 2 3 4 5 6 7 8 9 10 11>;
+			snps,data-width = <2>;
+			snps,block-size = <0x80000 0x80000 0x80000 0x80000 0x80000 0x80000 0x80000 0x80000 0x80000 0x80000 0x80000 0x80000>;
+			snps,axi-max-burst-len = <16>;
+			snps,max-msize = <64>;
+			eswin,hsp_sp_csr = <&d0_hsp_sp_csr 0x104c>;
+			eswin,syscfg = <&d0_sys_con DMA1_SID_REG_OFFSET 0x370>;
+			numa-node-id = <0>;
+		};
+
+		d0_aon_dmac: dma-controller-aon@0x518c0000 {
+			compatible = "snps,axi-dma-1.01a";
+			reg = <0x0 0x518c0000 0x0 0x10000>;
+			interrupt-parent = <&plic0>;
+			interrupts = <289>;
+			#dma-cells = <2>; // change dma-cells value <1> to <2>, to support peripheral selection dma-controller,See the parameter dmas for details;
+			clocks = <&d0_clock EIC7700_CLK_AONDMA_ACLK>;
+			clock-names = "core-clk";
+			resets = <&d0_reset DMA1_RST_CTRL SW_DMA1_ARSTN>,
+				<&d0_reset DMA1_RST_CTRL SW_DMA1_HRSTN>;
+			reset-names = "arst", "prst";
+			dma-channels = <16>;
+			snps,dma-masters = <2>;
+			snps,priority = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15>;
+			snps,data-width = <3>;
+			snps,block-size = <0x80000 0x80000 0x80000 0x80000 0x80000 0x80000 0x80000 0x80000 0x80000 0x80000 0x80000 0x80000 0x80000 0x80000 0x80000 0x80000>;
+			snps,axi-max-burst-len = <32>;
+			snps,max-msize = <64>;
+			#size-cells = <2>;
+			#address-cells = <2>;
+			dma-ranges = <0x0 0x80000000 0x0 0x80000000 0x100 0x0>;
+			eswin,syscfg = <&d0_sys_con DMA1_SID_REG_OFFSET 0x370>;
+			numa-node-id = <0>;
+		};
+
+		d0_gmac0: ethernet@50400000 {
+			compatible = "eswin,eic7700-qos-eth";
+			reg = <0x0 0x50400000 0x0 0x10000>;
+			interrupt-parent = <&plic0>;
+			interrupt-names = "macirq";
+			interrupts = <61>;
+			phy-mode = "rgmii-txid";
+			numa-node-id = <0>;
+			id = <0>;
+			status = "disabled";
+			clocks = <&d0_clock EIC7700_CLK_HSP_ETH_APP_CLK>,
+					 <&d0_clock EIC7700_CLK_HSP_ETH_CSR_CLK>,
+					 <&d0_clock EIC7700_CLK_HSP_ETH0_CORE_CLK>;
+			clock-names = "app", "stmmaceth","tx";
+			resets = <&d0_reset HSPDMA_RST_CTRL SW_HSP_ETH0_ARSTN>;
+			reset-names = "ethrst";
+			tbus = <EIC7700_TBUID_ETH>;
+			eswin,hsp_sp_csr = <&d0_hsp_sp_csr 0x1030 0x100 0x108>;
+			eswin,syscrg_csr = <&d0_sys_crg 0x148 0x14c>;
+			snps,axi-config = <&d0_stmmac_axi_setup>;
+			d0_stmmac_axi_setup: stmmac-axi-config {
+				snps,blen = <0 0 0 0 16 8 4>;
+				snps,rd_osr_lmt = <2>;
+				snps,wr_osr_lmt = <2>;
+				snps,lpi_en = <0>;
+			};
+		};
+
+		d0_gmac1: ethernet@50410000 {
+			compatible = "eswin,eic7700-qos-eth";
+			reg = <0x0 0x50410000 0x0 0x10000>;
+			interrupt-parent = <&plic0>;
+			interrupt-names = "macirq";
+			interrupts = <70>;
+			phy-mode = "rgmii-txid";
+			numa-node-id = <0>;
+			id = <1>;
+			status = "disabled";
+			clocks = <&d0_clock EIC7700_CLK_HSP_ETH_APP_CLK>,
+					 <&d0_clock EIC7700_CLK_HSP_ETH_CSR_CLK>,
+					 <&d0_clock EIC7700_CLK_HSP_ETH1_CORE_CLK>;
+			clock-names = "app", "stmmaceth","tx";
+			resets = <&d0_reset HSPDMA_RST_CTRL SW_HSP_ETH1_ARSTN>;
+			reset-names = "ethrst";
+			tbus = <EIC7700_TBUID_ETH>;
+			eswin,hsp_sp_csr = <&d0_hsp_sp_csr 0x1034 0x200 0x208>;
+			eswin,syscrg_csr = <&d0_sys_crg 0x148 0x14c>;
+			snps,axi-config = <&d0_stmmac_axi_setup_gmac1>;
+			d0_stmmac_axi_setup_gmac1: stmmac-axi-config {
+				snps,blen = <0 0 0 0 16 8 4>;
+				snps,rd_osr_lmt = <2>;
+				snps,wr_osr_lmt = <2>;
+				snps,lpi_en = <0>;
+			};
+		};
+		noc {
+			compatible = "eswin,noc","simple-bus";
+			#address-cells = <2>;
+			#size-cells = <2>;
+			ranges;
+			#include "eic7700-noc.dtsi"
+		};
+
+		d0_npu: eswin-npu@51c00000 {
+			compatible = "eswin,npu0";
+			reg = <0x0 0x51c00000 0x0 0x400000>;
+			interrupt-parent = <&plic0>;
+			interrupts = <387 16>;
+			/*spram-region = <&npu0_reserved>;*/
+			#size-cells = <2>;
+			dma-ranges = <0x1 0x0 0x0 0xc0000000 0x1ff 0x0>;
+			dsp-avail-num = <1>;
+			spram-size = <0x400000>;
+			npu_mbox = <&d0_mbox2>;
+			resets = <&d0_reset NPU_RST_CTRL SW_NPU_E31CORE_RSTN>;
+			reset-names = "e31_core";
+			numa-node-id = <0>;
+		};
+
+		dev_llc_d0: llc@51c00000 {
+			compatible = "eswin,llc";
+			reg = <0x0 0x51c00000 0x0 0x400000>;
+			eswin,syscfg = <&d0_sys_con 0x324>;
+			eswin,syscrg_csr = <&d0_sys_crg>;
+			clocks = <&d0_clock EIC7700_CLK_NPU_ACLK>,
+				 <&d0_clock EIC7700_CLK_NPU_CFG_CLK>,
+				 <&d0_clock EIC7700_CLK_NPU_LLC_ACLK>,
+				 <&d0_clock EIC7700_CLK_NPU_CLK>,
+				 <&d0_clock EIC7700_MUX_U_NPU_CORE_3MUX1_GFREE>,
+				 <&d0_clock EIC7700_SPLL2_FOUT2>;
+			clock-names = "aclk", "cfg_clk", "llc_clk", "core_clk",
+					"mux_u_npu_core_3mux1_gfree", "fixed_rate_clk_spll2_fout2",
+					"fixed_rate_clk_spll1_fout1";
+			resets = <&d0_reset NPU_RST_CTRL SW_NPU_AXI_RSTN>,
+				<&d0_reset NPU_RST_CTRL SW_NPU_CFG_RSTN>,
+				<&d0_reset NPU_RST_CTRL SW_NPU_CORE_RSTN>,
+				<&d0_reset NPU_RST_CTRL SW_NPU_LLC_RSTN>;
+			reset-names = "axi", "cfg", "core", "llc";
+			numa-node-id = <0>;
+			spram-region = <&npu0_reserved>;
+		};
+
+		d0_dsp_subsys:dsp_subsys@52280400 {
+			#address-cells = <2>;
+			#size-cells = <2>;
+			reg = <0x0 0x52280400 0x0 0x10000>,
+					<0x0 0x51810000 0x0 0x8000>;
+			ranges;
+			compatible = "es-dsp-subsys", "simple-bus";
+			clocks = <&d0_clock EIC7700_CLK_DSPT_CFG_CLK>;
+			clock-names = "cfg_clk";
+			resets = <&d0_reset DSP_RST_CTRL SW_DSP_AXI_RSTN>,
+					<&d0_reset DSP_RST_CTRL SW_DSP_CFG_RSTN>,
+					<&d0_reset DSP_RST_CTRL SW_DSP_DIV4_RSTN>,
+					<&d0_reset DSP_RST_CTRL SW_DSP_DIV_RSTN_0>,
+					<&d0_reset DSP_RST_CTRL SW_DSP_DIV_RSTN_1>,
+					<&d0_reset DSP_RST_CTRL SW_DSP_DIV_RSTN_2>,
+					<&d0_reset DSP_RST_CTRL SW_DSP_DIV_RSTN_3>;
+			reset-names = "axi", "cfg", "div4", "div_0", "div_1", "div_2","div_3";
+			d0_dsp0:es_dsp@0 {
+				#address-cells = <1>;
+				#size-cells = <1>;
+				compatible = "eswin-dsp", "cdns,xrp-hw-eswin";
+				ranges = <0x28000000 0 0x5b000000 0x8000
+					0x28100000 0 0x5b100000 0x20000
+					0x28120000 0 0x5b120000 0x20000>;
+				clocks = <&d0_clock EIC7700_CLK_DSP_ACLK_0>;
+				clock-names = "aclk";
+				dsp_mbox = <&d0_mbox4>;
+				device-irq = <11
+					ESWIN_MAILBOX_DSP_0_TO_U84_REG_BASE
+					ESWIN_MAILBOX_WR_LOCK_BIT_DSP_0
+					ESWIN_MAILBOX_U84_TO_DSP_0_REG_BASE
+					ESWIN_MAIBOX_U84_IRQ_BIT
+					ESWIN_MAILBOX_U84_TO_NPU_0_REG_BASE>;
+
+				device-uart = <0x50900000>;
+				device-irq-mode = <1>;
+				host-irq-mode = <1>;
+				firmware-name = "eic7700_dsp_fw";
+				process-id = <0>;
+				dma-ranges = <0x30000000 0x0 0xc0000000 0xce000000>;
+				numa-node-id = <0>;
+				aux-e31-dtim = <0x5a110000>;
+				dsp@0 {
+				};
+			};
+			d0_dsp1:es_dsp@1 {
+				#address-cells = <1>;
+				#size-cells = <1>;
+				compatible = "eswin-dsp", "cdns,xrp-hw-eswin";
+				ranges = <0x28000000 0 0x5b008000 0x8000
+					0x28100000 0 0x5b140000 0x20000
+					0x28120000 0 0x5b160000 0x20000>;
+				clocks = <&d0_clock EIC7700_CLK_DSP_ACLK_1>;
+				clock-names = "aclk";
+				dsp_mbox = <&d0_mbox5>;
+				device-irq = <13
+					ESWIN_MAILBOX_DSP_1_TO_U84_REG_BASE
+					ESWIN_MAILBOX_WR_LOCK_BIT_DSP_1
+					ESWIN_MAILBOX_U84_TO_DSP_1_REG_BASE
+					ESWIN_MAIBOX_U84_IRQ_BIT
+					ESWIN_MAILBOX_U84_TO_NPU_0_REG_BASE>;
+				device-uart = <0x50900000>;
+				device-irq-mode = <1>;
+				host-irq-mode = <1>;
+				firmware-name = "eic7700_dsp_fw";
+				process-id = <1>;
+				dma-ranges = <0x30000000 0x0 0xc0000000 0xce000000>;
+				numa-node-id = <0>;
+				aux-e31-dtim = <0x5a110000>;
+				dsp@0 {
+				};
+			};
+			d0_dsp2:es_dsp@2 {
+				#address-cells = <1>;
+				#size-cells = <1>;
+				compatible = "eswin-dsp", "cdns,xrp-hw-eswin";
+				ranges = <0x28000000 0 0x5b010000 0x8000
+					0x28100000 0 0x5b180000 0x20000
+					0x28120000 0 0x5b1a0000 0x20000>;
+				clocks = <&d0_clock EIC7700_CLK_DSP_ACLK_2>;
+				clock-names = "aclk";
+				dsp_mbox = <&d0_mbox6>;
+				device-irq = <15
+					ESWIN_MAILBOX_DSP_2_TO_U84_REG_BASE
+					ESWIN_MAILBOX_WR_LOCK_BIT_DSP_2
+					ESWIN_MAILBOX_U84_TO_DSP_2_REG_BASE
+					ESWIN_MAIBOX_U84_IRQ_BIT
+					ESWIN_MAILBOX_U84_TO_NPU_0_REG_BASE>;
+				device-uart = <0x50900000>;
+				device-irq-mode = <1>;
+				host-irq-mode = <1>;
+				firmware-name = "eic7700_dsp_fw";
+				process-id = <2>;
+				dma-ranges = <0x30000000 0x0 0xc0000000 0xce000000>;
+				numa-node-id = <0>;
+				aux-e31-dtim = <0x5a110000>;
+				dsp@0 {
+				};
+			};
+			d0_dsp3:es_dsp@3 {
+				#address-cells = <1>;
+				#size-cells = <1>;
+				compatible = "eswin-dsp", "cdns,xrp-hw-eswin";
+				ranges = <0x28000000 0 0x5b018000 0x8000
+					0x28100000 0 0x5b1c0000 0x20000
+					0x28120000 0 0x5b1e0000 0x20000>;
+				clocks = <&d0_clock EIC7700_CLK_DSP_ACLK_3>;
+				clock-names = "aclk";
+				dsp_mbox = <&d0_mbox7>;
+				device-irq = <17
+					ESWIN_MAILBOX_DSP_3_TO_U84_REG_BASE
+					ESWIN_MAILBOX_WR_LOCK_BIT_DSP_3
+					ESWIN_MAILBOX_U84_TO_DSP_3_REG_BASE
+					ESWIN_MAIBOX_U84_IRQ_BIT
+					ESWIN_MAILBOX_U84_TO_NPU_0_REG_BASE>;
+				device-uart = <0x50900000>;
+				device-irq-mode = <1>;
+				host-irq-mode = <1>;
+				firmware-name = "eic7700_dsp_fw";
+				process-id = <3>;
+				dma-ranges = <0x30000000 0x0 0xc0000000 0xce000000>;
+				numa-node-id = <0>;
+				aux-e31-dtim = <0x5a110000>;
+				dsp@0 {
+				};
+			};
+		};
+
+		gc820: g2d@50140000 {
+			compatible = "eswin,galcore_d0";
+			clocks = <&d0_clock EIC7700_CLK_VC_ACLK>,
+					<&d0_clock EIC7700_CLK_VC_CFG_CLK>,
+					<&d0_clock EIC7700_CLK_G2D_CFG_CLK>,
+					<&d0_clock EIC7700_CLK_CLK_G2D_ST2>,
+					<&d0_clock EIC7700_CLK_G2D_CLK>,
+					<&d0_clock EIC7700_CLK_G2D_ACLK>,
+					<&d0_clock EIC7700_CLK_VC_MON_PCLK>;
+			clock-names = "vc_aclk", "vc_cfg", "g2d_cfg", "g2d_st2", "g2d_clk", "g2d_aclk", "mon_pclk";
+			resets = <&d0_reset VC_RST_CTRL SW_VC_AXI_RSTN>,
+					<&d0_reset VC_RST_CTRL SW_VC_CFG_RSTN>,
+					<&d0_reset VC_RST_CTRL SW_VC_MONCFG_RSTN>,
+					<&d0_reset G2D_RST_CTRL SW_G2D_CORE_RSTN>,
+					<&d0_reset G2D_RST_CTRL SW_G2D_CFG_RSTN>,
+					<&d0_reset G2D_RST_CTRL SW_G2D_AXI_RSTN>;
+			reset-names = "axi", "cfg", "moncfg", "g2d_core", "g2d_cfg", "g2d_axi";
+			reg = <0 0x50140000 0 0x40000>, <0 0x50180000 0 0x40000>;
+			reg-names = "core_2d", "core_2d1";
+			fe-apb-offset = <0x800>;
+			interrupt-parent = <&plic0>;
+			interrupts = <49>, <50>;
+			interrupt-names = "core_2d", "core_2d1";
+			enable-mmu = <1>;
+			contiguous-size = <0xa00000>;
+			recovery = <0>;
+		};
+
+		gpu0: gpu@51400000 {
+			compatible = "img,gpu";
+			#address-cells = <2>;
+			#size-cells = <2>;
+			reg = <0x0 0x51400000 0x0 0xFFFFF>;
+			clocks = <&d0_clock EIC7700_CLK_GPU_ACLK>,
+					<&d0_clock EIC7700_CLK_GPU_GRAY_CLK>,
+					<&d0_clock EIC7700_CLK_GPU_CFG_CLK>;
+			clock-names = "aclk", "gray_clk", "cfg_clk";
+			resets =<&d0_reset GPU_RST_CTRL SW_GPU_AXI_RSTN>,
+					<&d0_reset GPU_RST_CTRL SW_GPU_CFG_RSTN>,
+					<&d0_reset GPU_RST_CTRL SW_GPU_GRAY_RSTN>,
+					<&d0_reset GPU_RST_CTRL SW_GPU_JONES_RSTN>,
+					<&d0_reset GPU_RST_CTRL SW_GPU_SPU_RSTN>;
+			reset-names = "axi", "cfg", "gray", "jones","spu";
+			interrupt-parent = <&plic0>;
+			interrupts = <15>;
+		};
+
+		d0_sata: sata@0x50420000{
+			compatible = "snps,eswin-ahci";
+			reg = <0x0 0x50420000 0x0 0x10000>;
+			interrupt-parent = <&plic0>;
+			interrupt-names = "intrq", "msi", "pme";
+			interrupts = <58>, <59>, <60>;
+			ports-implemented = <0x1>;
+			resets = <&d0_reset HSPDMA_RST_CTRL SW_SATA_ASIC0_RSTN>,
+					<&d0_reset HSPDMA_RST_CTRL SW_SATA_OOB_RSTN>,
+					<&d0_reset HSPDMA_RST_CTRL SW_SATA_PMALIVE_RSTN>,
+					<&d0_reset HSPDMA_RST_CTRL SW_SATA_RBC_RSTN>,
+					<&d0_reset HSPDMA_RST_CTRL SW_HSP_SATA_ARSTN>;
+			reset-names = "asic0", "oob", "pmalive", "rbc", "apb";
+			#size-cells = <2>;
+			dma-ranges = <0x0 0x0 0x0 0xc0000000 0x200 0x0>;
+			eswin,hsp_sp_csr = <&d0_hsp_sp_csr 0x1050>;
+			eswin,syscrg_csr = <&d0_sys_crg 0x41c>;
+			numa-node-id = <0>;
+		};
+
+		pcie: pcie@0x54000000 {
+			compatible = "eswin,eic7700-pcie";
+			clocks = <&d0_clock EIC7700_CLK_PCIET_ACLK>,
+				 <&d0_clock EIC7700_CLK_PCIET_CFG_CLK>,
+				 <&d0_clock EIC7700_CLK_PCIET_CR_CLK>,
+				 <&d0_clock EIC7700_CLK_PCIET_AUX_CLK>;
+			clock-names = "pcie_aclk", "pcie_cfg_clk", "pcie_cr_clk", "pcie_aux_clk";
+
+			reset-names = "pcie_cfg", "pcie_powerup", "pcie_pwren";
+			resets = <&d0_reset PCIE_RST_CTRL SW_PCIE_CFG_RSTN>,
+				 <&d0_reset PCIE_RST_CTRL SW_PCIE_POWERUP_RSTN>,
+				 <&d0_reset PCIE_RST_CTRL SW_PCIE_PERST_N>;
+
+			#address-cells = <3>;
+			#size-cells = <2>;
+			#interrupt-cells = <1>;
+			reg = <0x0 0x54000000 0x0 0x4000000>,	/* IP registers */
+			      <0x0 0x40000000 0x0 0x800000>,	/* Configuration space */
+			      <0x0 0x50000000 0x0 0x100000>;
+			reg-names = "dbi", "config", "mgmt";
+			device_type = "pci";
+			/* dma-coherent; */
+			bus-range = <0x0 0xff>;
+
+			ranges = <0x81000000  0x0 0x40800000  0x0 0x40800000 0x0 0x800000>,      /* I/O */
+				 <0x82000000  0x0 0x41000000  0x0 0x41000000 0x0 0xf000000>,    /* mem */
+				 <0xc3000000 0x80 0x00000000 0x80 0x00000000 0x02 0x00000000>;  /* mem prefetchable */
+
+			num-lanes = <0x4>;
+			/**********************************
+			 	msi_ctrl_io[0~31] : 188~219
+			 	msi_ctrl_int : 220
+			**********************************/
+			interrupts = <220>, <179>, <180>, <181>, <182>, <183>, <184>, <185>, <186>;
+			interrupt-names = "msi", "inta", "intb", "intc", "intd";
+			interrupt-parent = <&plic0>;
+			interrupt-map-mask = <0x0 0x0 0x0 0x7>;
+			interrupt-map = <0x0 0x0 0x0 0x1 &plic0 179>,
+							<0x0 0x0 0x0 0x2 &plic0 180>,
+							<0x0 0x0 0x0 0x3 &plic0 181>,
+							<0x0 0x0 0x0 0x4 &plic0 182>;
+			gen-x = <3>;
+			lane-x = <4>;
+			tbus = <EIC7700_TBUID_PCIE>;
+			status = "disabled";
+			numa-node-id = <0>;
+		};
+
+		ssi0: spi@50810000 {
+			compatible = "snps,eic7700-spi";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x0 0x50810000 0x0 0x4000>;
+			spi-max-frequency = <4800000>;
+			clocks = <&d0_clock EIC7700_CLK_LSP_SSI0_PCLK>;
+			clock-names = "clk";
+			interrupt-parent = <&plic0>;
+			interrupts = <91>;
+			resets = <&d0_reset SSI_RST_CTRL SW_SSI_RST_N_0>;
+			reset-names = "spi";
+			eswin,spi_dma = <&d0_aon_dmac>;
+			dmas = <&d0_aon_dmac 38 3>, <&d0_aon_dmac 39 3>;
+			dma-names = "rx", "tx";
+			numa-node-id = <0>;
+			status = "disabled";
+		};
+
+		ssi1: spi@50814000 {
+			compatible = "snps,eic7700-spi";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x0 0x50814000 0x0 0x4000>;
+			spi-max-frequency = <4800000>;
+			clocks = <&d0_clock EIC7700_CLK_LSP_SSI1_PCLK>;
+			clock-names = "clk";
+			interrupt-parent = <&plic0>;
+			interrupts = <92>;
+			resets = <&d0_reset SSI_RST_CTRL SW_SSI_RST_N_1>;
+			reset-names = "spi";
+			eswin,spi_dma = <&d0_aon_dmac>;
+			dmas = <&d0_aon_dmac 36 4>, <&d0_aon_dmac 37 4>;
+			dma-names = "rx", "tx";
+			numa-node-id = <0>;
+			status = "disabled";
+		};
+
+		bootspi: spi@51800000 {
+			compatible = "eswin,bootspi";
+			reg = <0x0 0x51800000 0x0 0x8000>,
+				<0x0 0x51828000 0x0 0x8000>,
+				<0x0 0x5c000000 0x0 0x8000>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			clocks = <&d0_clock EIC7700_CLK_CLK_BOOTSPI_CFG>,
+					<&d0_clock EIC7700_CLK_CLK_BOOTSPI>;
+			clock-names = "cfg_clk", "clk";
+			resets = <&d0_reset BOOTSPI_RST_CTRL SW_BOOTSPI_RSTN>;
+			reset-names = "rst";
+			spi-max-frequency = <4800000>;
+			reg-io-width = <4>;
+			status = "disabled";
+		};
+
+		sdhci_emmc: mmc@50450000 {
+			compatible = "eswin,emmc-sdhci-5.1";
+			reg = <0x0 0x50450000 0x0 0x10000>;
+			interrupt-parent = <&plic0>;
+			interrupts = <79>;
+			assigned-clocks = <&d0_clock EIC7700_CLK_HSP_MSHC0_CORE_CLK>;
+			assigned-clock-rates = <200000000>;
+			clocks = <&d0_clock EIC7700_CLK_HSP_MSHC0_CORE_CLK>, <&d0_clock EIC7700_CLK_HSP_CFG_CLK>;
+			clock-names = "clk_xin", "clk_ahb";
+			clock-output-names = "emmc_cardclock";
+			#clock-cells = <0>;
+
+			resets = <&d0_reset HSPDMA_RST_CTRL SW_MSHC0_TXRX_RSTN>,
+				<&d0_reset HSPDMA_RST_CTRL SW_MSHC0_PHY_RSTN>,
+				<&d0_reset HSPDMA_RST_CTRL SW_HSP_EMMC_PRSTN>,
+				<&d0_reset HSPDMA_RST_CTRL SW_HSP_EMMC_ARSTN>;
+			reset-names = "txrx_rst", "phy_rst", "prstn", "arstn";
+
+			disable-cqe-dcmd;
+			bus-width = <8>;
+			non-removable;
+			/*mmc-ddr-1_8v;*/
+			mmc-hs400-1_8v;
+			max-frequency = <200000000>;
+			/* sdhci-caps-mask =  <0x0 0x3200000>; */
+			/* sdhci-caps-mask =  <0x2 0x3000000>; */
+			/* smmu */
+			#size-cells = <2>;
+			dma-ranges = <0x0 0x00000000 0x0 0xc0000000 0x1 0x0>;
+			eswin,hsp_sp_csr = <&d0_hsp_sp_csr 0x1038>;
+			status = "disabled";
+			numa-node-id = <0>;
+		};
+
+		sdio0: mmc@0x50460000{
+			compatible = "eswin,sdhci-sdio";
+			reg = <0x0 0x50460000 0x0 0x10000>;
+			interrupt-parent = <&plic0>;
+			interrupts = <81>;
+			clocks =<&d0_clock EIC7700_CLK_HSP_MSHC1_CORE_CLK>,
+				<&d0_clock EIC7700_CLK_HSP_CFG_CLK>,
+				<&d0_clock EIC7700_SPLL2_FOUT3>,
+				<&d0_clock EIC7700_MUX_U_MSHCORE_ROOT_3MUX1_1>;
+			clock-names ="clk_xin","clk_ahb","clk_spll2_fout3","clk_mux1_1";
+			clock-output-names = "sdio0_cardclock";
+			#clock-cells = <0>;
+			resets = <&d0_reset HSPDMA_RST_CTRL SW_MSHC1_TXRX_RSTN>,
+				<&d0_reset HSPDMA_RST_CTRL SW_MSHC1_PHY_RSTN>,
+				<&d0_reset HSPDMA_RST_CTRL SW_HSP_SD0_PRSTN>,
+				<&d0_reset HSPDMA_RST_CTRL SW_HSP_SD0_ARSTN>;
+			reset-names = "txrx_rst","phy_rst","prstn","arstn";
+
+			core-clk-reg = <0x51828164>;
+			clock-frequency = <208000000>;
+			max-frequency = <208000000>;
+			#size-cells = <2>;
+			dma-ranges = <0x0 0x20000000 0x0 0xc0000000 0x0 0x40000000>;
+			eswin,hsp_sp_csr = <&d0_hsp_sp_csr 0x103c>;
+			bus-width = <4>;
+			sdio-id = <0>;
+			numa-node-id = <0>;
+			status = "disabled";
+		};
+
+		sdio1: mmc@0x50470000{
+			compatible = "eswin,sdhci-sdio";
+			reg = <0x0 0x50470000 0x0 0x10000>;
+			interrupt-parent = <&plic0>;
+			interrupts = <83>;
+			clocks =<&d0_clock EIC7700_CLK_HSP_MSHC2_CORE_CLK>,
+				<&d0_clock EIC7700_CLK_HSP_CFG_CLK>,
+				<&d0_clock EIC7700_SPLL2_FOUT3>,
+				<&d0_clock EIC7700_MUX_U_MSHCORE_ROOT_3MUX1_1>;
+			clock-names ="clk_xin","clk_ahb","clk_spll2_fout3","clk_mux1_1";
+			clock-output-names = "sdio1_cardclock";
+			#clock-cells = <0>;
+			resets = <&d0_reset HSPDMA_RST_CTRL SW_MSHC2_TXRX_RSTN>,
+				<&d0_reset HSPDMA_RST_CTRL SW_MSHC2_PHY_RSTN>,
+				<&d0_reset HSPDMA_RST_CTRL SW_HSP_SD1_PRSTN>,
+				<&d0_reset HSPDMA_RST_CTRL SW_HSP_SD1_ARSTN>;
+			reset-names = "txrx_rst","phy_rst","prstn","arstn";
+
+			core-clk-reg = <0x51828168>;
+			clock-frequency = <208000000>;
+			max-frequency = <208000000>;
+			#size-cells = <2>;
+			dma-ranges = <0x0 0x20000000 0x0 0xc0000000 0x0 0x40000000>;
+			eswin,hsp_sp_csr = <&d0_hsp_sp_csr 0x1040>;
+			bus-width = <4>;
+			sdio-id = <1>;
+			numa-node-id = <0>;
+			status = "disabled";
+		};
+
+		vdec0: video-decoder0@50100000 {
+			compatible = "eswin,video-decoder0";
+			clocks = <&d0_clock EIC7700_CLK_VC_ACLK>,
+					 <&d0_clock EIC7700_CLK_VC_CFG_CLK>,
+					 <&d0_clock EIC7700_CLK_VC_JD_CLK>,
+					 <&d0_clock EIC7700_CLK_VC_VD_CLK>,
+					 <&d0_clock EIC7700_MUX_U_VCACLK_ROOT_2MUX1_GFREE>,
+					 <&d0_clock EIC7700_SPLL0_FOUT1>,
+					 <&d0_clock EIC7700_SPLL2_FOUT1>,
+					 <&d0_clock EIC7700_CLK_VC_JD_PCLK>,
+					 <&d0_clock EIC7700_CLK_VC_VD_PCLK>,
+					 <&d0_clock EIC7700_CLK_VC_MON_PCLK>;
+			clock-names = "aclk", "cfg_clk", "jd_clk", "vd_clk", "vc_mux", "spll0_fout1", "spll2_fout1", "jd_pclk", "vd_pclk", "mon_pclk";
+			resets = <&d0_reset VC_RST_CTRL SW_VC_AXI_RSTN>,
+					 <&d0_reset VC_RST_CTRL SW_VC_CFG_RSTN>,
+					 <&d0_reset VC_RST_CTRL SW_VC_MONCFG_RSTN>,
+					 <&d0_reset JD_RST_CTRL SW_JD_CFG_RSTN>,
+					 <&d0_reset JD_RST_CTRL SW_JD_AXI_RSTN>,
+					 <&d0_reset VD_RST_CTRL SW_VD_CFG_RSTN>,
+					 <&d0_reset VD_RST_CTRL SW_VD_AXI_RSTN>;
+			reset-names = "axi", "cfg", "moncfg", "jd_cfg", "jd_axi", "vd_cfg", "vd_axi";
+			eswin,syscfg = <&d0_sys_con 0x0 0x4>;
+
+			vcmd-core = <0 0x6c>;
+			axife-core = <0x200 0x100>;
+			vdec-core = <0x800 0xc00>;
+			interrupt-parent = <&plic0>;
+			#size-cells = <2>;
+			dma-ranges = <0x0 0x0 0x0 0x80000000 0x200 0x0>;
+			vccsr-reg = <0x0 0x501c0000 0x0 0x1000>;
+			numa-node-id = <0>;
+
+			vdec_0: vdec0@50100000 {
+				core-name = "video-dec0";
+				base-addr = <0x50100000>;
+				interrupts = <236>;
+			};
+
+			jdec_0: jdec0@50120000 {
+				core-name = "jpeg-dec0";
+				base-addr = <0x50120000>;
+				interrupts = <237>;
+			};
+		};
+
+		venc0: video-encoder@50110000 {
+			compatible = "eswin,video-encoder0";
+			clocks = <&d0_clock EIC7700_CLK_VC_ACLK>,
+					 <&d0_clock EIC7700_CLK_VC_CFG_CLK>,
+					 <&d0_clock EIC7700_CLK_VC_JE_CLK>,
+					 <&d0_clock EIC7700_CLK_VC_VE_CLK>,
+					 <&d0_clock EIC7700_MUX_U_VCACLK_ROOT_2MUX1_GFREE>,
+					 <&d0_clock EIC7700_SPLL0_FOUT1>,
+					 <&d0_clock EIC7700_SPLL2_FOUT1>,
+					 <&d0_clock EIC7700_CLK_VC_JE_PCLK>,
+					 <&d0_clock EIC7700_CLK_VC_VE_PCLK>,
+					 <&d0_clock EIC7700_CLK_VC_MON_PCLK>;
+			clock-names = "aclk", "cfg_clk", "je_clk", "ve_clk", "vc_mux", "spll0_fout1", "spll2_fout1", "je_pclk", "ve_pclk", "mon_pclk";
+			resets = <&d0_reset VC_RST_CTRL SW_VC_AXI_RSTN>,
+					 <&d0_reset VC_RST_CTRL SW_VC_CFG_RSTN>,
+					 <&d0_reset VC_RST_CTRL SW_VC_MONCFG_RSTN>,
+					 <&d0_reset JE_RST_CTRL SW_JE_CFG_RSTN>,
+					 <&d0_reset JE_RST_CTRL SW_JE_AXI_RSTN>,
+					 <&d0_reset VE_RST_CTRL SW_VE_CFG_RSTN>,
+					 <&d0_reset VE_RST_CTRL SW_VE_AXI_RSTN>;
+			reset-names = "axi", "cfg", "moncfg", "je_cfg", "je_axi", "ve_cfg", "ve_axi";
+			eswin,syscfg = <&d0_sys_con 0x0 0x4>;
+
+			vcmd-core = <0 0x6c>;
+			axife-core = <0x2000 0x7d0>;
+			venc-core = <0x1000 0x87c>;
+			interrupt-parent = <&plic0>;
+			#size-cells = <2>;
+			dma-ranges = <0x0 0x0 0x0 0x80000000 0x200 0x0>;
+			vccsr-reg = <0x0 0x501c0000 0x0 0x1000>;
+			numa-node-id = <0>;
+
+			venc_0: venc0@50110000 {
+				core-name = "video-enc0";
+				base-addr = <0x50110000>;
+				interrupts = <229>;
+			};
+
+			jenc_0: jenc0@50130000 {
+				core-name = "jpeg-enc0";
+				base-addr = <0x50130000>;
+				interrupts = <232>;
+			};
+		};
+
+		/*mailbox between u84 & scpu*/
+		d0_mbox0: mbox@50a00000 {
+			compatible = "eswin,eic7700-mailbox";
+			reg = <0 ESWIN_MAILBOX_U84_TO_SCPU_REG_BASE 0 0x10000>,
+				  <0 ESWIN_MAILBOX_SCPU_TO_U84_REG_BASE 0 0x10000>;
+			interrupt-parent = <&plic0>;
+			interrupts = <117>;
+			#mbox-cells = <1>;
+			clocks = <&d0_clock EIC7700_CLK_MAILBOX_0>,
+				<&d0_clock EIC7700_CLK_MAILBOX_1>;
+			clock-names = "pclk_mailbox_host", "pclk_mailbox_device";
+			resets = <&d0_reset MBOX_RST_CTRL SW_MBOX_RST_N_0>,
+				<&d0_reset MBOX_RST_CTRL SW_MBOX_RST_N_1>;
+			reset-names = "rst", "rst_device";
+			lock-bit = <ESWIN_MAILBOX_WR_LOCK_BIT_U84>;
+			irq-bit = <ESWIN_MAIBOX_SCPU_IRQ_BIT>;
+		};
+
+		/*mailbox between u84 & lpcpu*/
+		d0_mbox1: mbox@50a20000 {
+			compatible = "eswin,eic7700-mailbox";
+			reg = <0 ESWIN_MAILBOX_U84_TO_LPCPU_REG_BASE 0 0x10000>,
+				  <0 ESWIN_MAILBOX_LPCPU_TO_U84_REG_BASE 0 0x10000>;
+			interrupt-parent = <&plic0>;
+			interrupts = <119>;
+			#mbox-cells = <1>;
+			clocks = <&d0_clock EIC7700_CLK_MAILBOX_2>,
+				<&d0_clock EIC7700_CLK_MAILBOX_3>;
+			clock-names = "pclk_mailbox_host", "pclk_mailbox_device";
+			resets = <&d0_reset MBOX_RST_CTRL SW_MBOX_RST_N_2>,
+				<&d0_reset MBOX_RST_CTRL SW_MBOX_RST_N_3>;
+			reset-names = "rst", "rst_device";
+			lock-bit = <ESWIN_MAILBOX_WR_LOCK_BIT_U84>;
+			irq-bit  = <ESWIN_MAIBOX_LPCPU_IRQ_BIT>;
+		};
+
+		/*mailbox between u84 & npu_0*/
+		d0_mbox2: mbox@50a40000 {
+			compatible = "eswin,npu0-mailbox";
+			reg = <0 ESWIN_MAILBOX_U84_TO_NPU_0_REG_BASE 0 0x10000>,
+				  <0 ESWIN_MAILBOX_NPU_0_TO_U84_REG_BASE 0 0x10000>;
+			interrupt-parent = <&plic0>;
+			interrupts = <121>;
+			#mbox-cells = <1>;
+			clocks = <&d0_clock EIC7700_CLK_MAILBOX_4>,
+				<&d0_clock EIC7700_CLK_MAILBOX_5>;
+			clock-names = "pclk_mailbox_host", "pclk_mailbox_device";
+			resets = <&d0_reset MBOX_RST_CTRL SW_MBOX_RST_N_4>,
+				<&d0_reset MBOX_RST_CTRL SW_MBOX_RST_N_5>;
+			reset-names = "rst", "rst_device";
+			lock-bit = <ESWIN_MAILBOX_WR_LOCK_BIT_U84>;
+			irq-bit  = <ESWIN_MAIBOX_NPU_0_IRQ_BIT>;
+		};
+
+		/*mailbox between u84 & npu_1*/
+		d0_mbox3: mbox@50a60000 {
+			compatible = "eswin,eic7700-mailbox";
+			reg = <0 ESWIN_MAILBOX_U84_TO_NPU_1_REG_BASE 0 0x10000>,
+				  <0 ESWIN_MAILBOX_NP1_0_TO_U84_REG_BASE 0 0x10000>;
+			interrupt-parent = <&plic0>;
+			interrupts = <123>;
+			#mbox-cells = <1>;
+			clocks = <&d0_clock EIC7700_CLK_MAILBOX_6>,
+				<&d0_clock EIC7700_CLK_MAILBOX_7>;
+			clock-names = "pclk_mailbox_host", "pclk_mailbox_device";
+			resets = <&d0_reset MBOX_RST_CTRL SW_MBOX_RST_N_6>,
+				<&d0_reset MBOX_RST_CTRL SW_MBOX_RST_N_7>;
+			reset-names = "rst", "rst_device";
+			lock-bit = <ESWIN_MAILBOX_WR_LOCK_BIT_U84>;
+			irq-bit  = <ESWIN_MAIBOX_NPU_1_IRQ_BIT>;
+		};
+
+		/*mailbox between u84 & dsp_0*/
+		d0_mbox4: mbox@50a80000 {
+			compatible = "eswin,dsp0-mailbox";
+			reg = <0 ESWIN_MAILBOX_U84_TO_DSP_0_REG_BASE 0 0x10000>,
+				  <0 ESWIN_MAILBOX_DSP_0_TO_U84_REG_BASE 0 0x10000>;
+			interrupt-parent = <&plic0>;
+			interrupts = <125>;
+			#mbox-cells = <1>;
+			clocks = <&d0_clock EIC7700_CLK_MAILBOX_8>,
+				<&d0_clock EIC7700_CLK_MAILBOX_9>;
+			clock-names = "pclk_mailbox_host", "pclk_mailbox_device";
+			resets = <&d0_reset MBOX_RST_CTRL SW_MBOX_RST_N_8>,
+				<&d0_reset MBOX_RST_CTRL SW_MBOX_RST_N_9>;
+			reset-names = "rst", "rst_device";
+			lock-bit = <ESWIN_MAILBOX_WR_LOCK_BIT_U84>;
+			irq-bit  = <ESWIN_MAIBOX_DSP_0_IRQ_BIT>;
+		};
+
+		/*mailbox between u84 & dsp_1*/
+		d0_mbox5: mbox@50aa0000 {
+			compatible = "eswin,dsp1-mailbox";
+			reg = <0 ESWIN_MAILBOX_U84_TO_DSP_1_REG_BASE 0 0x10000>,
+				  <0 ESWIN_MAILBOX_DSP_1_TO_U84_REG_BASE 0 0x10000>;
+			interrupt-parent = <&plic0>;
+			interrupts = <127>;
+			#mbox-cells = <1>;
+			clocks = <&d0_clock EIC7700_CLK_MAILBOX_10>,
+				<&d0_clock EIC7700_CLK_MAILBOX_11>;
+			clock-names = "pclk_mailbox_host", "pclk_mailbox_device";
+			resets = <&d0_reset MBOX_RST_CTRL SW_MBOX_RST_N_10>,
+				<&d0_reset MBOX_RST_CTRL SW_MBOX_RST_N_11>;
+			reset-names = "rst", "rst_device";
+			lock-bit = <ESWIN_MAILBOX_WR_LOCK_BIT_U84>;
+			irq-bit  = <ESWIN_MAIBOX_DSP_1_IRQ_BIT>;
+		};
+
+		/*mailbox between u84 & dsp_2*/
+		d0_mbox6: mbox@50ac0000 {
+			compatible = "eswin,dsp2-mailbox";
+			reg = <0 ESWIN_MAILBOX_U84_TO_DSP_2_REG_BASE 0 0x10000>,
+				  <0 ESWIN_MAILBOX_DSP_2_TO_U84_REG_BASE 0 0x10000>;
+			interrupt-parent = <&plic0>;
+			interrupts = <129>;
+			#mbox-cells = <1>;
+			clocks = <&d0_clock EIC7700_CLK_MAILBOX_12>,
+				<&d0_clock EIC7700_CLK_MAILBOX_13>;
+			clock-names = "pclk_mailbox_host", "pclk_mailbox_device";
+			resets = <&d0_reset MBOX_RST_CTRL SW_MBOX_RST_N_12>,
+				<&d0_reset MBOX_RST_CTRL SW_MBOX_RST_N_13>;
+			reset-names = "rst", "rst_device";
+			lock-bit = <ESWIN_MAILBOX_WR_LOCK_BIT_U84>;
+			irq-bit  = <ESWIN_MAIBOX_DSP_2_IRQ_BIT>;
+		};
+
+		/*mailbox between u84 & dsp_3*/
+		d0_mbox7: mbox@50ae0000 {
+			compatible = "eswin,dsp3-mailbox";
+			reg = <0 ESWIN_MAILBOX_U84_TO_DSP_3_REG_BASE 0 0x10000>,
+				  <0 ESWIN_MAILBOX_DSP_3_TO_U84_REG_BASE 0 0x10000>;
+			interrupt-parent = <&plic0>;
+			interrupts = <131>;
+			#mbox-cells = <1>;
+			clocks = <&d0_clock EIC7700_CLK_MAILBOX_14>,
+				<&d0_clock EIC7700_CLK_MAILBOX_15>;
+			clock-names = "pclk_mailbox_host", "pclk_mailbox_device";
+			resets = <&d0_reset MBOX_RST_CTRL SW_MBOX_RST_N_14>,
+				<&d0_reset MBOX_RST_CTRL SW_MBOX_RST_N_15>;
+			reset-names = "rst", "rst_device";
+			lock-bit = <ESWIN_MAILBOX_WR_LOCK_BIT_U84>;
+			irq-bit  = <ESWIN_MAIBOX_DSP_3_IRQ_BIT>;
+		};
+
+		d0_ipc_scpu:ipc@0 {
+			compatible = "eswin,eic7700-ipc";
+			#size-cells = <2>;
+			dma-ranges = <0x0 0x80000000 0x0 0xc0000000 0x0 0x80000000>;
+			eswin,syscfg = <&d0_sys_con SCPU_SID_REG_OFFSET 0>,
+			               <&d0_sys_con CRYPT_SID_REG_OFFSET 0>;
+			mboxes = <&d0_mbox0 0>;
+			mbox-names = "u84_scpu";
+			numa-node-id = <0>;
+		};
+
+		d0_lpcpu:lpcpu@0 {
+			compatible = "eswin,eic7700-lpcpu";
+			fw-region = <&lpcpu0_reserved>;
+			clocks = <&d0_clock EIC7700_CLK_CLK_LPCPU_CORE>,
+					<&d0_clock EIC7700_CLK_CLK_LPCPU_BUS>;
+			clock-names = "core_clk", "bus_clk";
+
+			reset-names = "core_rst", "bus_rst", "dbg_rst";
+			resets = <&d0_reset LPCPU_RST_CTRL SW_LPCPU_CORE_RSTN>,
+					<&d0_reset LPCPU_RST_CTRL SW_LPCPU_BUS_RSTN>,
+					<&d0_reset LPCPU_RST_CTRL SW_LPCPU_DBG_RSTN>;
+			#size-cells = <2>;
+
+			dma-ranges = <0x0 0xb0000000 0x0 0xc0000000 0x0 0x50000000>;
+			eswin,syscfg = <&d0_sys_con LCPU_SID_REG_OFFSET 0>;
+			mboxes = <&d0_mbox1 0>;
+			mbox-names = "u84_lpcpu";
+			numa-node-id = <0>;
+			status = "disabled";
+		};
+
+		pvt0: pvt@0x50b00000 {
+			compatible = "eswin,eswin-pvt";
+			clocks = <&d0_clock EIC7700_CLK_PVT_CLK_0>;
+			clock-names = "pvt_clk";
+			resets = <&d0_reset PVT_RST_CTRL SW_PVT_RST_N_0>;
+			reset-names = "pvt_rst";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x0 0x50b00000 0x0 0x10000>;
+			interrupts = <349>;
+			interrupt-parent = <&plic0>;
+			status = "disabled";
+		};
+		pvt1: pvt@0x52360000 {
+			compatible = "eswin,eswin-pvt";
+			clocks = <&d0_clock EIC7700_CLK_PVT_CLK_1>;
+			clock-names = "pvt_clk";
+			resets = <&d0_reset PVT_RST_CTRL SW_PVT_RST_N_1>;
+			reset-names = "pvt_rst";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x0 0x52360000 0x0 0x20000>;
+			interrupts = <350>;
+			interrupt-parent = <&plic0>;
+			status = "disabled";
+		};
+
+		fan_control: fan_control@50b50000 {
+			compatible = "eswin-fan-control";
+			reg = <0x0 0x50b50000 0x0 0x10000>;
+			clocks = <&d0_clock EIC7700_CLK_LSP_FAN_PCLK>;
+			clock-names = "pclk";
+			resets = <&d0_reset FAN_RST_CTRL SW_FAN_RST_N>;
+			reset-names = "fan_rst";
+			interrupt-parent = <&plic0>;
+			interrupt-names = "fanirq";
+			interrupts = <354>;
+			pulses-per-revolution = <2>;
+			pwm-minimum-period = <1000>;
+			pwms = <&pwm0 0 100000>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&pinctrl_fan_tach_default>;
+			status = "disabled";
+		};
+
+		d0_i2c0: i2c@50950000 {
+			compatible = "snps,designware-i2c";
+			clock-frequency = <100000>;
+			clocks = <&d0_clock EIC7700_CLK_LSP_I2C0_PCLK>;
+			clock-names = "pclk";
+			resets = <&d0_reset I2C_RST_CTRL SW_I2C_RST_N_0>;
+			reset-names = "rst";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x0 0x50950000 0x0 0x8000>;
+			interrupts = <105>;
+			interrupt-parent = <&plic0>;
+		};
+		d0_i2c1: i2c@50960000 {
+			compatible = "snps,designware-i2c";
+			clock-frequency = <100000>;
+			clocks = <&d0_clock EIC7700_CLK_LSP_I2C1_PCLK>;
+			clock-names = "pclk";
+			resets = <&d0_reset I2C_RST_CTRL SW_I2C_RST_N_1>;
+			reset-names = "rst";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x0 0x50960000 0x0 0x10000>;
+			interrupts = <106>;
+			interrupt-parent = <&plic0>;
+		};
+		d0_i2c2: i2c@50970000 {
+				compatible = "snps,designware-i2c";
+				clock-frequency = <100000>;
+				clocks = <&d0_clock EIC7700_CLK_LSP_I2C2_PCLK>;
+				clock-names = "pclk";
+				resets = <&d0_reset I2C_RST_CTRL SW_I2C_RST_N_2>;
+				reset-names = "rst";
+				#address-cells = <1>;
+				#size-cells = <0>;
+				reg = <0x0 0x50970000 0x0 0x8000>;
+				interrupts = <107>;
+				interrupt-parent = <&plic0>;
+		};
+		d0_i2c3: i2c@50980000 {
+				compatible = "snps,designware-i2c";
+				clock-frequency = <100000>;
+				clocks = <&d0_clock EIC7700_CLK_LSP_I2C3_PCLK>;
+				clock-names = "pclk";
+				resets = <&d0_reset I2C_RST_CTRL SW_I2C_RST_N_3>;
+				reset-names = "rst";
+				#address-cells = <1>;
+				#size-cells = <0>;
+				reg = <0x0 0x50980000 0x0 0x8000>;
+				interrupts = <108>;
+				interrupt-parent = <&plic0>;
+		};
+		d0_i2c4: i2c@50990000 {
+				compatible = "snps,designware-i2c";
+				clock-frequency = <100000>;
+				clocks = <&d0_clock EIC7700_CLK_LSP_I2C4_PCLK>;
+				clock-names = "pclk";
+				resets = <&d0_reset I2C_RST_CTRL SW_I2C_RST_N_4>;
+				reset-names = "rst";
+				#address-cells = <1>;
+				#size-cells = <0>;
+				reg = <0x0 0x50990000 0x0 0x8000>;
+				interrupts = <109>;
+				interrupt-parent = <&plic0>;
+		};
+		d0_i2c5: i2c@509a0000 {
+				compatible = "snps,designware-i2c";
+				clock-frequency = <100000>;
+				clocks = <&d0_clock EIC7700_CLK_LSP_I2C5_PCLK>;
+				clock-names = "pclk";
+				resets = <&d0_reset I2C_RST_CTRL SW_I2C_RST_N_5>;
+				reset-names = "rst";
+				#address-cells = <1>;
+				#size-cells = <0>;
+				reg = <0x0 0x509a0000 0x0 0x8000>;
+				interrupts = <110>;
+				interrupt-parent = <&plic0>;
+		};
+		d0_i2c6: i2c@509b0000 {
+				compatible = "snps,designware-i2c";
+				clock-frequency = <100000>;
+				clocks = <&d0_clock EIC7700_CLK_LSP_I2C6_PCLK>;
+				clock-names = "pclk";
+				resets = <&d0_reset I2C_RST_CTRL SW_I2C_RST_N_6>;
+				reset-names = "rst";
+				#address-cells = <1>;
+				#size-cells = <0>;
+				reg = <0x0 0x509b0000 0x0 0x8000>;
+				interrupts = <111>;
+				interrupt-parent = <&plic0>;
+		};
+		d0_i2c7: i2c@509c0000 {
+				compatible = "snps,designware-i2c";
+				clock-frequency = <100000>;
+				clocks = <&d0_clock EIC7700_CLK_LSP_I2C7_PCLK>;
+				clock-names = "pclk";
+				resets = <&d0_reset I2C_RST_CTRL SW_I2C_RST_N_7>;
+				reset-names = "rst";
+				#address-cells = <1>;
+				#size-cells = <0>;
+				reg = <0x0 0x509c0000 0x0 0x8000>;
+				interrupts = <112>;
+				interrupt-parent = <&plic0>;
+		};
+		d0_i2c8: i2c@509d0000 {
+				compatible = "snps,designware-i2c";
+				clock-frequency = <100000>;
+				clocks = <&d0_clock EIC7700_CLK_LSP_I2C8_PCLK>;
+				clock-names = "pclk";
+				resets = <&d0_reset I2C_RST_CTRL SW_I2C_RST_N_8>;
+				reset-names = "rst";
+				#address-cells = <1>;
+				#size-cells = <0>;
+				reg = <0x0 0x509d0000 0x0 0x8000>;
+				interrupts = <113>;
+				interrupt-parent = <&plic0>;
+		};
+		d0_i2c9: i2c@509e0000 {
+				compatible = "snps,designware-i2c";
+				clock-frequency = <100000>;
+				clocks = <&d0_clock EIC7700_CLK_LSP_I2C9_PCLK>;
+				clock-names = "pclk";
+				resets = <&d0_reset I2C_RST_CTRL SW_I2C_RST_N_9>;
+				reset-names = "rst";
+				#address-cells = <1>;
+				#size-cells = <0>;
+				reg = <0x0 0x509e0000 0x0 0x8000>;
+				interrupts = <114>;
+				interrupt-parent = <&plic0>;
+		};
+		d0_aon_i2c0: i2c@51830000 {
+				compatible = "snps,designware-i2c";
+				clock-frequency = <100000>;
+				clocks = <&d0_clock EIC7700_CLK_AON_I2C0_PCLK>;
+				clock-names = "pclk";
+				resets = <&d0_reset I2C0_RST_CTRL SW_I2C0_PRSTN>;
+				reset-names = "rst";
+				#address-cells = <1>;
+				#size-cells = <0>;
+				reg = <0x0 0x51830000 0x0 0x8000>;
+				interrupts = <290>;
+				interrupt-parent = <&plic0>;
+				eswin,i2c_dma = <&d0_aon_dmac>;
+				dma-names = "rx", "tx";
+				/*
+				* dmas : DMA specifiers
+				* &d0_aon_dmac : dma controller
+				* 41 : i2c0 aon dma handshake number
+				* 0xff : no need to select to dma controller
+				*/
+				dmas = <&d0_aon_dmac 41 0xff>, <&d0_aon_dmac 42 0xff>;
+		};
+		d0_aon_i2c1: i2c@51838000 {
+				compatible = "snps,designware-i2c";
+				clock-frequency = <100000>;
+				clocks = <&d0_clock EIC7700_CLK_AON_I2C1_PCLK>;
+				clock-names = "pclk";
+				resets = <&d0_reset I2C1_RST_CTRL SW_I2C1_PRSTN>;
+				reset-names = "rst";
+				#address-cells = <1>;
+				#size-cells = <0>;
+				reg = <0x0 0x51838000 0x0 0x8000>;
+				interrupts = <291>;
+				interrupt-parent = <&plic0>;
+		};
+		pinctrl: pinctrl@0x51600080 {
+			compatible = "eswin,eic7700-pinctrl";
+			reg = <0x0 0x51600080 0x0 0x1FFF80>;
+			status = "disabled";
+		};
+
+		gpio0: gpio@51600000 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "snps,dw-apb-gpio";
+			reg = <0x0 0x51600000 0x0 0x80>;
+
+			porta: gpio-port@0 {
+				compatible = "snps,dw-apb-gpio-port";
+				gpio-controller;
+				#gpio-cells = <2>;
+				ngpios = <32>;
+				reg = <0>;
+				interrupt-parent = <&plic0>;
+				interrupts = <303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318
+								319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334>;
+			};
+
+			portb: gpio-port@1 {
+				compatible = "snps,dw-apb-gpio-port";
+				gpio-controller;
+				#gpio-cells = <2>;
+				ngpios = <32>;
+				reg = <1>;
+			};
+
+			portc: gpio-port@2 {
+				compatible = "snps,dw-apb-gpio-port";
+				gpio-controller;
+				#gpio-cells = <2>;
+				ngpios = <32>;
+				reg = <2>;
+			};
+
+			portd: gpio-port@3 {
+				compatible = "snps,dw-apb-gpio-port";
+				gpio-controller;
+				#gpio-cells = <2>;
+				ngpios = <16>;
+				reg = <3>;
+			};
+		};
+
+		pwm0: pwm@0x50818000 {
+			compatible = "eswin,pwm-eswin";
+			#pwm-cells = <2>;
+			reg = <0x0 0x50818000 0x0 0x4000>;
+			clock-names = "pwm","pclk";
+			clocks = <&d0_clock EIC7700_CLK_LSP_TIMER_PCLK>;
+			clock-frequency = <200000000>;
+			resets = <&d0_reset TIMER_RST_CTRL SW_TIMER_RST_N>;
+			reset-names = "pwmrst";
+			pinctrl-names = "default";
+			pinctrl-0 = <&pinctrl_pwm0_default>;
+			status = "disabled";
+		};
+
+		wdt0: watchdog@0x50800000 {
+			compatible = "snps,dw-wdt";
+			reg = <0x0 0x50800000 0x0 0x4000>;
+			clocks =<&d0_clock EIC7700_CLK_LSP_WDT0_PCLK>;
+			clock-names = "pclk";
+			resets = <&d0_reset WDT_RST_CTRL SW_WDT_RST_N_0>;
+			reset-names = "rst";
+			interrupts = <87>;
+			interrupt-parent = <&plic0>;
+			status = "disabled";
+		};
+
+		wdt1: watchdog@0x50804000 {
+			compatible = "snps,dw-wdt";
+			reg = <0x0 0x50804000 0x0 0x4000>;
+			clocks =<&d0_clock EIC7700_CLK_LSP_WDT1_PCLK>;
+			clock-names = "pclk";
+			resets = <&d0_reset WDT_RST_CTRL SW_WDT_RST_N_1>;
+			reset-names = "rst";
+			interrupts = <88>;
+			interrupt-parent = <&plic0>;
+			status = "disabled";
+		};
+
+		wdt2: watchdog@0x50808000 {
+			compatible = "snps,dw-wdt";
+			reg = <0x0 0x50808000 0x0 0x4000>;
+			clocks =<&d0_clock EIC7700_CLK_LSP_WDT2_PCLK>;
+			clock-names = "pclk";
+			resets = <&d0_reset WDT_RST_CTRL SW_WDT_RST_N_2>;
+			reset-names = "rst";
+			interrupts = <89>;
+			interrupt-parent = <&plic0>;
+			status = "disabled";
+		};
+
+		wdt3: watchdog@0x5080c000 {
+			compatible = "snps,dw-wdt";
+			reg = <0x0 0x5080c000 0x0 0x4000>;
+			clocks =<&d0_clock EIC7700_CLK_LSP_WDT3_PCLK>;
+			clock-names = "pclk";
+			resets = <&d0_reset WDT_RST_CTRL SW_WDT_RST_N_3>;
+			reset-names = "rst";
+			interrupts = <90>;
+			interrupt-parent = <&plic0>;
+			status = "disabled";
+		};
+
+		timer0: timer@0x51840000 {
+			compatible = "eswin,eswin-timer";
+			#address-cells = <2>;
+			#size-cells = <2>;
+			reg = <0x0 0x51840000 0x0 0x8000>;
+			perf_count = <7>;
+			interrupt-parent = <&plic0>;
+			interrupts = <345>;
+			clock-names = "pclk","timer_aclk";
+			clocks = <&d0_clock EIC7700_CLK_TIMER_PCLK_0>,
+					 <&d0_clock EIC7700_CLK_TIMER_CLK_0>;
+			resets = <&d0_reset TIMER0_RST_CTRL SW_TIMER0_RSTN_0>,
+				<&d0_reset TIMER0_RST_CTRL SW_TIMER0_RSTN_1>,
+				<&d0_reset TIMER0_RST_CTRL SW_TIMER0_RSTN_2>,
+				<&d0_reset TIMER0_RST_CTRL SW_TIMER0_RSTN_3>,
+				<&d0_reset TIMER0_RST_CTRL SW_TIMER0_RSTN_4>,
+				<&d0_reset TIMER0_RST_CTRL SW_TIMER0_RSTN_5>,
+				<&d0_reset TIMER0_RST_CTRL SW_TIMER0_RSTN_6>,
+				<&d0_reset TIMER0_RST_CTRL SW_TIMER0_RSTN_7>,
+				<&d0_reset TIMER0_RST_CTRL SW_TIMER0_PRSTN>;
+			reset-names = "trst0","trst1","trst2","trst3","trst4","trst5","trst6","trst7","prst";
+		};
+
+		timer1: timer@0x51848000 {
+			compatible = "eswin,eswin-timer";
+			#address-cells = <2>;
+			#size-cells = <2>;
+			reg = <0x0 0x51848000 0x0 0x8000>;
+			interrupt-parent = <&plic0>;
+			interrupts = <346>;
+			clock-names = "pclk","timer_aclk";
+			clocks = <&d0_clock EIC7700_CLK_TIMER_PCLK_1>,
+					 <&d0_clock EIC7700_CLK_TIMER_CLK_1>;
+			resets = <&d0_reset TIMER1_RST_CTRL SW_TIMER1_RSTN_0>,
+				<&d0_reset TIMER1_RST_CTRL SW_TIMER1_RSTN_1>,
+				<&d0_reset TIMER1_RST_CTRL SW_TIMER1_RSTN_2>,
+				<&d0_reset TIMER1_RST_CTRL SW_TIMER1_RSTN_3>,
+				<&d0_reset TIMER1_RST_CTRL SW_TIMER1_RSTN_4>,
+				<&d0_reset TIMER1_RST_CTRL SW_TIMER1_RSTN_5>,
+				<&d0_reset TIMER1_RST_CTRL SW_TIMER1_RSTN_6>,
+				<&d0_reset TIMER1_RST_CTRL SW_TIMER1_RSTN_7>,
+				<&d0_reset TIMER1_RST_CTRL SW_TIMER1_PRSTN>;
+			reset-names = "trst0","trst1","trst2","trst3","trst4","trst5","trst6","trst7","prst";
+		};
+
+		timer2: timer@0x51850000 {
+			compatible = "eswin,eswin-timer";
+			#address-cells = <2>;
+			#size-cells = <2>;
+			reg = <0x0 0x51850000 0x0 0x8000>;
+			interrupt-parent = <&plic0>;
+			interrupts = <347>;
+			clock-names = "pclk","timer_aclk";
+			clocks = <&d0_clock EIC7700_CLK_TIMER_PCLK_2>,
+					 <&d0_clock EIC7700_CLK_TIMER_CLK_2>;
+			resets = <&d0_reset TIMER2_RST_CTRL SW_TIMER2_RSTN_0>,
+			   <&d0_reset TIMER2_RST_CTRL SW_TIMER2_RSTN_1>,
+			   <&d0_reset TIMER2_RST_CTRL SW_TIMER2_RSTN_2>,
+			   <&d0_reset TIMER2_RST_CTRL SW_TIMER2_RSTN_3>,
+			   <&d0_reset TIMER2_RST_CTRL SW_TIMER2_RSTN_4>,
+			   <&d0_reset TIMER2_RST_CTRL SW_TIMER2_RSTN_5>,
+			   <&d0_reset TIMER2_RST_CTRL SW_TIMER2_RSTN_6>,
+			   <&d0_reset TIMER2_RST_CTRL SW_TIMER2_RSTN_7>,
+			   <&d0_reset TIMER2_RST_CTRL SW_TIMER2_PRSTN>;
+			reset-names = "trst0","trst1","trst2","trst3","trst4","trst5","trst6","trst7","prst";
+		};
+
+		timer3: timer@0x51858000 {
+			compatible = "eswin,eswin-timer";
+			#address-cells = <2>;
+			#size-cells = <2>;
+			reg = <0x0 0x51858000 0x0 0x8000>;
+			interrupt-parent = <&plic0>;
+			interrupts = <348>;
+			clock-names = "pclk","timer_aclk","timer3_clk8";
+			clocks = <&d0_clock EIC7700_CLK_TIMER_PCLK_3>,
+					 <&d0_clock EIC7700_CLK_TIMER_CLK_3>,
+					 <&d0_clock EIC7700_CLK_TIMER3_CLK8>;
+			resets = <&d0_reset TIMER3_RST_CTRL SW_TIMER3_RSTN_0>,
+				<&d0_reset TIMER3_RST_CTRL SW_TIMER3_RSTN_1>,
+				<&d0_reset TIMER3_RST_CTRL SW_TIMER3_RSTN_2>,
+				<&d0_reset TIMER3_RST_CTRL SW_TIMER3_RSTN_3>,
+				<&d0_reset TIMER3_RST_CTRL SW_TIMER3_RSTN_4>,
+				<&d0_reset TIMER3_RST_CTRL SW_TIMER3_RSTN_5>,
+				<&d0_reset TIMER3_RST_CTRL SW_TIMER3_RSTN_6>,
+				<&d0_reset TIMER3_RST_CTRL SW_TIMER3_RSTN_7>,
+				<&d0_reset TIMER3_RST_CTRL SW_TIMER3_PRSTN>;
+			reset-names = "trst0","trst1","trst2","trst3","trst4","trst5","trst6","trst7","prst";
+		};
+
+		die0_rtc: rtc@51818000 {
+			compatible = "eswin,eic7700-rtc";
+			reg = <0x0 0x51818000 0x0 0x400>;
+			eswin,syscfg = <&d0_sys_con 0x3c0>;
+			interrupt-parent = <&plic0>;
+			interrupts = <292>;
+			clocks = <&d0_clock EIC7700_CLK_CLK_RTC>;
+			clock-names = "rtcclk";
+			clock-frequency = <15625>;
+			resets = <&d0_reset RTC_RST_CTRL SW_RTC_RSTN>;
+			reset-names = "rtcrst";
+			status = "disabled";
+		};
+
+		d0_i2s0: i2s0@50200000 {
+			compatible = "snps,i2s";
+			clocks = <&d0_clock EIC7700_CLK_VO_I2S_MCLK>;
+			clock-names = "mclk";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			#sound-dai-cells = <0x00000000>;
+			reg = <0x0 0x50200000 0x0 0x10000>;
+			dma-names = "rx", "tx";
+			dmas = <&d0_aon_dmac 4 0>, <&d0_aon_dmac 5 0>;
+			vo_mclk_sel,syscrg = <&d0_sys_crg 0x1bc>;
+			resets = <&d0_reset VO_I2SRST_CTRL SW_VO_I2S_RSTN>,
+				<&d0_reset VO_I2SRST_CTRL SW_VO_I2S_PRSTN>,
+				<&d0_reset VO_PHYRST_CTRL SW_VO_PRSTN>;
+			reset-names = "i2srst", "i2sprst", "voprst";
+		};
+
+		d0_i2s1: i2s1@50210000 {
+			compatible = "snps,i2s";
+			clocks = <&d0_clock EIC7700_CLK_VO_I2S_MCLK>;
+			clock-names = "mclk";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			#sound-dai-cells = <0x00000000>;
+			reg = <0x0 0x50210000 0x0 0x10000>;
+			dma-names = "rx", "tx";
+			dmas = <&d0_aon_dmac 2 1>, <&d0_aon_dmac 3 1>;
+			vo_mclk_sel,syscrg = <&d0_sys_crg 0x1bc>;
+			resets = <&d0_reset VO_I2SRST_CTRL SW_VO_I2S_RSTN>,
+				<&d0_reset VO_I2SRST_CTRL SW_VO_I2S_PRSTN>,
+				<&d0_reset VO_PHYRST_CTRL SW_VO_PRSTN>;
+			reset-names = "i2srst", "i2sprst", "voprst";
+		};
+
+		d0_i2s2: i2s2@50220000 {
+			compatible = "snps,i2s";
+			clocks = <&d0_clock EIC7700_CLK_VO_I2S_MCLK>;
+			clock-names = "mclk";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			#sound-dai-cells = <0x00000000>;
+			reg = <0x0 0x50220000 0x0 0x10000>;
+			dma-names = "rx", "tx";
+			dmas = <&d0_aon_dmac 0 2>, <&d0_aon_dmac 1 2>;
+			vo_mclk_sel,syscrg = <&d0_sys_crg 0x1bc>;
+			resets = <&d0_reset VO_I2SRST_CTRL SW_VO_I2S_RSTN>,
+				<&d0_reset VO_I2SRST_CTRL SW_VO_I2S_PRSTN>,
+				<&d0_reset VO_PHYRST_CTRL SW_VO_PRSTN>;
+			reset-names = "i2srst", "i2sprst", "voprst";
+		};
+
+		d0_graphcard0: graphcard0 {
+			compatible = "audio-graph-card";
+		};
+
+		d0_graphcard1: graphcard1 {
+			compatible = "audio-graph-card";
+		};
+
+		d0_graphcard2: graphcard2 {
+			compatible = "audio-graph-card";
+		};
+
+		video_output: display-subsystem {
+			compatible = "eswin,display-subsystem";
+			ports = <&dc_out>;
+		};
+
+		dvb_widgets: dvb-subsystem {
+			compatible = "amlogic,dvb_widgets";
+			status = "disabled";
+		};
+
+		dc: display_control@502c0000 {
+			compatible = "eswin,dc";
+			reg = <0x0 0x502c0000 0x0 0x100>, <0x0 0x502c0180 0x0 0x700>, <0x0 0x502c1400 0x0 0x1400>;
+			interrupt-parent = <&plic0>;
+			interrupts = <238>;
+
+			clocks = <&d0_clock EIC7700_CLK_VO_CFG_CLK>,
+			         <&d0_clock EIC7700_CLK_VO_PIXEL_CLK>,
+			         <&d0_clock EIC7700_CLK_VO_ACLK>,
+			         <&d0_clock EIC7700_SPLL0_FOUT1>,
+			         <&d0_clock EIC7700_MUX_U_VO_ACLK_ROOT_2MUX1_GFREE>;
+			clock-names = "cfg_clk", "pix_clk", "axi_clk", "spll0_fout1", "vo_mux";
+			resets = <&d0_reset VO_RST_CTRL SW_VO_AXI_RSTN>,
+					 <&d0_reset VO_RST_CTRL SW_VO_CFG_RSTN>,
+					 <&d0_reset VO_RST_CTRL SW_VO_DC_RSTN>,
+					 <&d0_reset VO_RST_CTRL SW_VO_DC_PRSTN>;
+			reset-names = "vo_arst", "vo_prst", "dc_arst", "dc_prst";
+
+			dc_out: port {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				dc_out_dsi: endpoint@0 {
+					reg = <0>;
+					remote-endpoint = <&dsi_input>;
+				};
+
+				dc_out_dpi1: endpoint@1 {
+					reg = <1>;
+					remote-endpoint = <&vd_input>;
+				};
+
+				dc_out_hdmi: endpoint@2 {
+					reg = <2>;
+					remote-endpoint = <&hdmi_in_dc>;
+				};
+			};
+		};
+
+		virtual_display: es_wb {
+			compatible = "eswin,virtual_display";
+			bpp = /bits/ 8 <8>;
+
+			port {
+				vd_input: endpoint {
+					remote-endpoint = <&dc_out_dpi1>;
+				};
+			};
+		};
+
+		dsi_output: dsi-output {
+			compatible = "eswin,dsi-encoder";
+			status = "disabled";
+		};
+
+		dsi_controller: mipi_dsi@50270000 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "eswin,dsi";
+			reg = <0x0 0x50270000 0x0 0x10000>;
+			clocks = <&d0_clock EIC7700_CLK_CLK_MIPI_TXESC>;
+			clock-names = "pclk";
+			resets = <&d0_reset VO_PHYRST_CTRL SW_VO_MIPI_PRSTN>;
+			reset-names ="phyrstn";
+			/*
+			phys = <&dphy>;
+			phy-names = "dphy";
+			*/
+
+			ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@0 {
+					#address-cells = <1>;
+					#size-cells = <0>;
+					reg = <0>;
+					dsi_input: endpoint {
+						remote-endpoint = <&dc_out_dsi>;
+					};
+				};
+
+				port@1 {
+					#address-cells = <1>;
+					#size-cells = <0>;
+					reg = <1>;
+
+					mipi_dsi_out: endpoint {
+						remote-endpoint = <&panel_in>;
+					};
+				};
+			};
+
+			dsi_panel:dsi_panel@0 {
+				compatible = "eswin,generic-panel";
+				reg = <0>;
+
+				port {
+					panel_in: endpoint {
+						remote-endpoint = <&mipi_dsi_out>;
+					};
+				};
+			};
+		};
+
+		dc_test: dctest@502c0000 {
+			compatible = "eswin,dc";
+			reg = <0x0 0x502c0000 0x0 0x10000>;
+			interrupt-parent = <&plic0>;
+			interrupts = <238>;
+		};
+
+		dw_hdmi: hdmi@502a0000 {
+			compatible = "eswin,eswin-dw-hdmi";
+			reg = <0x0 0x502a0000 0x0 0x20000>;
+			pinctrl-names = "default";
+			//pinctrl-0 = <&hdmi_i2c_xfer>;
+			interrupt-parent = <&plic0>;
+			interrupts = <274>;
+
+			clocks = <&d0_clock EIC7700_CLK_VO_CFG_CLK>, <&d0_clock EIC7700_CLK_VO_CEC_CLK>,
+				 <&d0_clock EIC7700_CLK_VO_CR_CLK>;
+			clock-names = "iahb", "cec", "isfr";
+			//power-domains = <&power EIC7700_PD_HDCP>;
+
+                        reg-io-width = <4>;
+			ddc-i2c-scl-high-time-ns = <4708>;
+			ddc-i2c-scl-low-time-ns = <4916>;
+			#sound-dai-cells = <0>;
+			resets = <&d0_reset VO_PHYRST_CTRL SW_VO_HDMI_PRSTN>,
+					 <&d0_reset VO_PHYRST_CTRL SW_HDMI_PHYCTRL_RSTN>,
+					 <&d0_reset VO_PHYRST_CTRL SW_VO_HDMI_RSTN>;
+			reset-names = "prstn", "phyrstn", "rstn";
+
+			ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				port@0 {
+					reg = <0>;
+					hdmi_in_dc: endpoint@0 {
+						remote-endpoint = <&dc_out_hdmi>;
+					};
+				};
+			};
+		};
+
+		dw_hdmi_hdcp2: hdmi-hdcp2@50290000 {
+				compatible = "eswin,dw-hdmi-hdcp2";
+				reg = <0x0 0x50290000 0x0 0x10000>;
+				interrupt-parent = <&plic0>;
+				interrupts = <275>;
+				clocks = <&d0_clock EIC7700_CLK_VO_CFG_CLK>,
+					    <&d0_clock EIC7700_CLK_VO_HDMI_IESMCLK>;
+				clock-names ="pclk_hdcp2", "hdcp2_clk_hdmi";
+				dma-noncoherent;
+		};
+
+		d0_usbdrd3_0: usb0@50480000 {
+			compatible = "eswin,eic7700-dwc3";
+			#address-cells = <2>;
+			#size-cells = <2>;
+			clocks =<&d0_clock EIC7700_GATE_HSP_USB0_SUSPEND_CLK>;
+			clock-names = "suspend";
+			eswin,hsp_sp_csr = <&d0_hsp_sp_csr 0x800 0x808 0x83c 0x840>;
+			resets = <&d0_reset HSPDMA_RST_CTRL SW_USB0_VAUX_RSTN>;
+			reset-names = "vaux";
+			ranges;
+			status = "disabled";
+			d0_usbdrd_dwc3_0: dwc3@50480000 {
+				compatible = "snps,dwc3";
+				reg = <0x0 0x50480000 0x0 0x10000>;
+				#address-cells = <2>;
+				#size-cells = <2>;
+				interrupt-parent = <&plic0>;
+				interrupts = <85>;
+				interrupt-names = "peripheral";
+				dr_mode = "peripheral";
+				phy_type = "utmi";
+				maximum-speed = "high-speed";
+				eswin,hsp_sp_csr = <&d0_hsp_sp_csr 0x1044>;
+				dma-ranges = <0x0 0x0 0x0 0xc0000000 0x200 0x0>;
+				snps,dis_enblslpm_quirk;
+				snps,dis-u2-freeclk-exists-quirk;
+				snps,dis_u2_susphy_quirk;
+				snps,dis-del-phy-power-chg-quirk;
+				snps,parkmode-disable-ss-quirk;
+				status = "disabled";
+				numa-node-id = <0>;
+				tbus = <EIC7700_TBUID_USB>;
+			};
+		};
+
+		d0_usbdrd3_1: usb1@50490000  {
+			compatible = "eswin,eic7700-dwc3";
+			#address-cells = <2>;
+			#size-cells = <2>;
+			clocks =<&d0_clock EIC7700_GATE_HSP_USB1_SUSPEND_CLK>;
+			clock-names = "suspend";
+			eswin,hsp_sp_csr = <&d0_hsp_sp_csr 0x900 0x908 0x93c 0x940>;
+			resets = <&d0_reset HSPDMA_RST_CTRL SW_USB1_VAUX_RSTN>;
+			reset-names = "vaux";
+			ranges;
+			status = "disabled";
+			d0_usbdrd_dwc3_1: dwc3@50490000 {
+				compatible = "snps,dwc3";
+				reg = <0x0 0x50490000 0x0 0x10000>;
+				#address-cells = <2>;
+				#size-cells = <2>;
+				interrupt-parent = <&plic0>;
+				interrupts = <86>;
+				interrupt-names = "host";
+				dr_mode = "host";
+				phy_type = "utmi";
+				maximum-speed = "high-speed";
+				eswin,hsp_sp_csr = <&d0_hsp_sp_csr 0x1048>;
+				dma-ranges = <0x0 0x0 0x0 0xc0000000 0x200 0x0>;
+				snps,dis_enblslpm_quirk;
+				snps,dis-u2-freeclk-exists-quirk;
+				snps,dis_u2_susphy_quirk;
+				snps,dis-del-phy-power-chg-quirk;
+				snps,parkmode-disable-ss-quirk;
+				status = "disabled";
+				numa-node-id = <0>;
+			};
+		};
+
+		vi_top_csr: vi_common_top_csr@0x51030000 {
+			compatible = "esw,vi-common-csr", "syscon";
+			clocks = <&d0_clock EIC7700_CLK_VI_ACLK>,
+			         <&d0_clock EIC7700_CLK_VI_CFG_CLK>,
+			         <&d0_clock EIC7700_CLK_VI_DIG_ISP_CLK>,
+			         <&d0_clock EIC7700_CLK_VI_DVP_CLK>,
+			         <&d0_clock EIC7700_CLK_VI_PHY_CFG>,
+			         <&d0_clock EIC7700_CLK_VI_PHY_TXCLKESC>,
+			         <&d0_clock EIC7700_CLK_VI_SHUTTER_0>,
+			         <&d0_clock EIC7700_CLK_VI_SHUTTER_1>,
+			         <&d0_clock EIC7700_CLK_VI_SHUTTER_2>,
+			         <&d0_clock EIC7700_CLK_VI_SHUTTER_3>,
+			         <&d0_clock EIC7700_CLK_VI_SHUTTER_4>,
+			         <&d0_clock EIC7700_CLK_VI_SHUTTER_5>,
+			         <&d0_clock EIC7700_MUX_U_VI_ACLK_ROOT_2MUX1_GFREE>,
+			         <&d0_clock EIC7700_MUX_U_VI_DVP_ROOT_2MUX1_GFREE>,
+			         <&d0_clock EIC7700_MUX_U_VI_DIG_ISP_ROOT_2MUX1_GFREE>,
+			         <&d0_clock EIC7700_SPLL0_FOUT1>,
+			         <&d0_clock EIC7700_VPLL_FOUT1>;
+			clock-names = "aclk", "cfg_clk", "isp_aclk", "dvp_clk", "phy_cfg",
+			              "phy_escclk", "sht0", "sht1", "sht2", "sht3", "sht4",
+			              "sht5", "aclk_mux", "dvp_mux", "isp_mux", "spll0_fout1", "vpll_fout1";
+			resets = <&d0_reset VI_RST_CTRL SW_VI_AXI_RSTN>,
+			         <&d0_reset VI_RST_CTRL SW_VI_CFG_RSTN>,
+			         <&d0_reset ISP0_RST_CTRL SW_VI_ISP0_RSTN>,
+			         <&d0_reset ISP1_RST_CTRL SW_VI_ISP1_RSTN>,
+			         <&d0_reset DVP_RST_CTRL SW_VI_DVP_RSTN>,
+			         <&d0_reset SHUTTER_RST_CTRL SW_VI_SHUTTER_RSTN_0>,
+			         <&d0_reset SHUTTER_RST_CTRL SW_VI_SHUTTER_RSTN_1>,
+			         <&d0_reset SHUTTER_RST_CTRL SW_VI_SHUTTER_RSTN_2>,
+			         <&d0_reset SHUTTER_RST_CTRL SW_VI_SHUTTER_RSTN_3>,
+			         <&d0_reset SHUTTER_RST_CTRL SW_VI_SHUTTER_RSTN_4>,
+			         <&d0_reset SHUTTER_RST_CTRL SW_VI_SHUTTER_RSTN_5>;
+			reset-names = "axi", "cfg", "isp0", "isp1", "dvp", "sht0", "sht1", "sht2", "sht3", "sht4", "sht5";
+
+			id = <0>;
+			#size-cells = <2>;
+			reg = <0x0 0x51030000 0x0 0x10000>;
+		};
+
+		isp_0: isp@0x51000000 {
+			compatible = "esw,eic7700-isp";
+
+			reg = <0x0 0x51000000 0x0 0x10000>;
+			interrupts = <21 19 20>;
+			interrupt-parent = <&plic0>;
+			id = <0>;
+			#size-cells = <2>;
+			dma-ranges = <0x0 0x20000000 0x0 0x80000000 0x0 0x40000000>;
+			eswin,vi_top_csr = <&vi_top_csr 0x1000>;
+			numa-node-id = <0>;
+		};
+
+		isp_1: isp@0x51010000 {
+			compatible = "esw,eic7700-isp";
+
+			reg = <0x0 0x51010000 0x0 0x10000>;
+			interrupts = <24 22 23>;
+			interrupt-parent = <&plic0>;
+			id = <1>;
+			#size-cells = <2>;
+			dma-ranges = <0x0 0x20000000 0x0 0x80000000 0x0 0x40000000>;
+			eswin,vi_top_csr = <&vi_top_csr 0x1004>;
+			numa-node-id = <0>;
+		};
+
+		dewarp: dewarp@51020000 {
+			compatible = "eswin,dewarp";
+			clocks = <&d0_clock EIC7700_CLK_VI_ACLK>,
+			         <&d0_clock EIC7700_CLK_VI_CFG_CLK>,
+			         <&d0_clock EIC7700_CLK_VI_DIG_DW_CLK>,
+			         <&d0_clock EIC7700_MUX_U_VI_ACLK_ROOT_2MUX1_GFREE>,
+			         <&d0_clock EIC7700_MUX_U_VI_DW_ROOT_2MUX1>,
+			         <&d0_clock EIC7700_SPLL0_FOUT1>,
+			         <&d0_clock EIC7700_VPLL_FOUT1>;
+			clock-names = "aclk", "cfg_clk", "dw_aclk", "aclk_mux", "dw_mux", "spll0_fout1", "vpll_fout1";
+			resets = <&d0_reset VI_RST_CTRL SW_VI_AXI_RSTN>,
+			         <&d0_reset VI_RST_CTRL SW_VI_CFG_RSTN>,
+			         <&d0_reset VI_RST_CTRL SW_VI_DWE_RSTN>;
+			reset-names = "axi", "cfg", "dwe";
+
+			interrupt-parent = <&plic0>;
+			interrupts = <26 25>;
+			#size-cells = <2>;
+			dma-ranges = <0x0 0x20000000 0x0 0x80000000 0x0 0x40000000>;
+			eswin,vi_top_csr = <&vi_top_csr 0x1008>;
+			reg = <0x0 0x51020000 0x0 0xc00>, <0x0 0x51020c00 0x0 0x120>;
+			numa-node-id = <0>;
+		};
+
+		mipi_dphy_rx: dphy@510c0000 {
+			compatible = "snps,dw-dphy-rx";
+			#phy-cells = <1>;
+			bus-width = <8>;
+			snps,dphy-frequency = <300000>;
+			snps,phy_type = <8>;
+			reg = <0x0 0x510c0000 0x0 0x20000>;
+			numa-node-id = <0>;
+		};
+
+		csi_dma0: csidma@0x52048000 {
+			compatible = "eswin,csi-video";
+			interrupt-parent = <&plic0>;
+			interrupts = <29>;
+			reg = <0x0 0x52048000 0x0 0x1000>;
+			numa-node-id = <0>;
+
+			port {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				csi_dmar_0: endpoint@0 {
+					reg = <0>;
+					bus-type = <4>;
+					remote-endpoint = <&csi2_dma_0_3>;
+				};
+			};
+		};
+
+		csi_dma1: csidma@0x52058000 {
+			compatible = "eswin,csi-video";
+			interrupt-parent = <&plic0>;
+			interrupts = <30>;
+			reg = <0x0 0x52058000 0x0 0x1000>;
+			numa-node-id = <0>;
+
+			port {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				csi_dmar_1: endpoint@0 {
+					reg = <0>;
+					bus-type = <4>;
+					remote-endpoint = <&csi2_dma_1_3>;
+				};
+			};
+		};
+
+		csi2_0: csi2@51050000 {
+			compatible = "snps,dw-csi";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			interrupt-parent = <&plic0>;
+			interrupts = <29>;
+			snps,output-type = <0>;
+			reg = <0x0 0x51050000 0x0 0x1000>;
+			/*phys = <&mipi_dphy_rx 1>;*/
+			numa-node-id = <0>;
+
+			/* MIPI CONFIG */
+			snps,en-ppi-width = <0>;/* 0: ppi8, 1: ppi16 */
+			snps,en-phy-mode = <0>;/* 0: D-PHY, 1: C-PHY */
+
+			ipi2_en = <0>;/* for virtual channel */
+			ipi2_vcid = <0>;/* virtual channel id */
+			ipi3_en = <0>;
+			ipi3_vcid = <0>;
+
+			#ifdef MIPI_CSI2_IMX290_ENBALE
+			port@1 {
+				reg = <1>;
+				csi2_0_1: endpoint {
+					bus-type = <4>;
+					clock-lanes = <0>;
+					#ifdef MIPI_CSI2_2LINE_ENABLE
+					data-lanes = <1 2>;
+					#else
+					data-lanes = <1 2 3 4>;
+					#endif
+					//remote-endpoint = <&imx290_csi2>;
+				};
+			};
+			#endif
+
+			port@2 {
+				reg = <2>;
+				csi2_dma_0_3: endpoint {
+					bus-type = <5>;
+					remote-endpoint = <&csi_dmar_0>;
+				};
+			};
+		};
+
+		csi2_1: csi2@51060000 {
+			compatible = "snps,dw-csi";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			interrupt-parent = <&plic0>;
+			interrupts = <30>;
+			snps,output-type = <0>;
+			reg = <0x0 0x51060000 0x0 0x1000>;
+			/*phys = <&mipi_dphy_rx 1>;*/
+			numa-node-id = <0>;
+
+			/* MIPI CONFIG */
+			snps,en-ppi-width = <0>;/* 0: ppi8, 1: ppi16 */
+			snps,en-phy-mode = <0>;/* 0: D-PHY, 1: C-PHY */
+
+			ipi2_en = <0>;/* for virtual channel */
+			ipi2_vcid = <0>;/* virtual channel id */
+			ipi3_en = <0>;
+			ipi3_vcid = <0>;
+
+			#ifdef MIPI_CSI2_IMX290_ENBALE
+			port@1 {
+				reg = <1>;
+				csi2_1_1: endpoint {
+					bus-type = <4>;
+					clock-lanes = <0>;
+					#ifdef MIPI_CSI2_2LINE_ENABLE
+					data-lanes = <1 2>;
+					#else
+					data-lanes = <1 2 3 4>;
+					#endif
+					//remote-endpoint = <&imx290_csi2>;
+				};
+			};
+			#endif
+
+			port@2 {
+				reg = <2>;
+				csi2_dma_1_3: endpoint {
+					bus-type = <5>;
+					remote-endpoint = <&csi_dmar_1>;
+				};
+			};
+		};
+
+		dc_test: dctest@502c0000 {
+			compatible = "eswin,dc";
+			reg = <0x0 0x502c0000 0x0 0x10000>;
+			interrupt-parent = <&plic0>;
+			interrupts = <238>;
+		};
+
+		ddr0: ddr-controller@0 {
+			compatible = "eswin,ddrc-1.20a";
+			interrupt-parent = <&plic0>;
+			interrupts = <10>;
+			interrupt-names = "ddr-ecc";
+			reg = <0x0 0x52300000 0x0 0x40000>;
+			ctrl-id = <0>;
+			status = "disabled";
+		};
+
+		ddr1: ddr-controller@1 {
+			compatible = "eswin,ddrc-1.20a";
+			interrupt-parent = <&plic0>;
+			interrupts = <299>;
+			interrupt-names = "ddr-ecc";
+			reg = <0x0 0x52380000 0x0 0x40000>;
+			ctrl-id = <1>;
+			status = "disabled";
+		};
+};
diff --git a/arch/riscv/configs/hifive-premier-p550_defconfig b/arch/riscv/configs/hifive-premier-p550_defconfig
new file mode 100644
index 000000000000..89cfdbe502b0
--- /dev/null
+++ b/arch/riscv/configs/hifive-premier-p550_defconfig
@@ -0,0 +1,2503 @@
+# CONFIG_LOCALVERSION_AUTO is not set
+CONFIG_SYSVIPC=y
+CONFIG_POSIX_MQUEUE=y
+CONFIG_WATCH_QUEUE=y
+CONFIG_USELIB=y
+# CONFIG_CONTEXT_TRACKING_USER_FORCE is not set
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_BPF_JIT=y
+CONFIG_BPF_JIT_ALWAYS_ON=y
+CONFIG_BPF_LSM=y
+CONFIG_PREEMPT_VOLUNTARY=y
+CONFIG_PREEMPT_DYNAMIC=y
+CONFIG_VIRT_CPU_ACCOUNTING_GEN=y
+CONFIG_BSD_PROCESS_ACCT=y
+CONFIG_BSD_PROCESS_ACCT_V3=y
+CONFIG_TASKSTATS=y
+CONFIG_TASK_DELAY_ACCT=y
+CONFIG_TASK_XACCT=y
+CONFIG_TASK_IO_ACCOUNTING=y
+CONFIG_PSI=y
+CONFIG_IKHEADERS=m
+CONFIG_LOG_BUF_SHIFT=18
+CONFIG_UCLAMP_TASK=y
+CONFIG_MEMCG=y
+CONFIG_BLK_CGROUP=y
+CONFIG_CFS_BANDWIDTH=y
+CONFIG_UCLAMP_TASK_GROUP=y
+CONFIG_CGROUP_PIDS=y
+CONFIG_CGROUP_RDMA=y
+CONFIG_CGROUP_FREEZER=y
+CONFIG_CGROUP_HUGETLB=y
+CONFIG_CPUSETS=y
+CONFIG_CGROUP_DEVICE=y
+CONFIG_CGROUP_CPUACCT=y
+CONFIG_CGROUP_PERF=y
+CONFIG_CGROUP_BPF=y
+CONFIG_CGROUP_MISC=y
+CONFIG_NAMESPACES=y
+CONFIG_USER_NS=y
+CONFIG_CHECKPOINT_RESTORE=y
+CONFIG_SCHED_AUTOGROUP=y
+CONFIG_EXPERT=y
+CONFIG_SGETMASK_SYSCALL=y
+CONFIG_PC104=y
+CONFIG_PROFILING=y
+CONFIG_KEXEC=y
+CONFIG_KEXEC_FILE=y
+CONFIG_CRASH_DUMP=y
+CONFIG_SOC_SIFIVE_EIC7700=y
+CONFIG_ARCH_SIFIVE=y
+CONFIG_SOC_VIRT=y
+CONFIG_ERRATA_THEAD=y
+CONFIG_SMP=y
+CONFIG_SCHED_MC=y
+CONFIG_NR_CPUS=32
+# CONFIG_RISCV_ISA_SVPBMT is not set
+# CONFIG_COMPAT is not set
+CONFIG_RANDOMIZE_BASE=y
+CONFIG_CMDLINE="clk_ignore_unused"
+CONFIG_CMDLINE_EXTEND=y
+CONFIG_PM_WAKELOCKS=y
+CONFIG_PM_DEBUG=y
+CONFIG_PM_ADVANCED_DEBUG=y
+CONFIG_ENERGY_MODEL=y
+CONFIG_CPU_IDLE=y
+CONFIG_CPU_IDLE_GOV_LADDER=y
+CONFIG_CPU_IDLE_GOV_MENU=y
+CONFIG_CPU_IDLE_GOV_TEO=y
+CONFIG_CPU_FREQ=y
+CONFIG_CPU_FREQ_STAT=y
+CONFIG_CPU_FREQ_GOV_POWERSAVE=y
+CONFIG_CPU_FREQ_GOV_USERSPACE=y
+CONFIG_CPU_FREQ_GOV_ONDEMAND=y
+CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
+CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y
+CONFIG_CPUFREQ_DT=y
+CONFIG_VIRTUALIZATION=y
+CONFIG_KVM=y
+CONFIG_ARCH_MMAP_RND_BITS=24
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+CONFIG_MODVERSIONS=y
+CONFIG_MODULE_SRCVERSION_ALL=y
+CONFIG_MODULE_SIG_SHA512=y
+CONFIG_MODULE_COMPRESS_ZSTD=y
+CONFIG_MODULE_DECOMPRESS=y
+CONFIG_BLK_DEV_ZONED=y
+CONFIG_BLK_DEV_THROTTLING=y
+CONFIG_BLK_WBT=y
+CONFIG_BLK_CGROUP_FC_APPID=y
+CONFIG_BLK_CGROUP_IOCOST=y
+CONFIG_BLK_CGROUP_IOPRIO=y
+CONFIG_BLK_SED_OPAL=y
+CONFIG_BLK_INLINE_ENCRYPTION=y
+CONFIG_BLK_INLINE_ENCRYPTION_FALLBACK=y
+CONFIG_PARTITION_ADVANCED=y
+CONFIG_AIX_PARTITION=y
+CONFIG_OSF_PARTITION=y
+CONFIG_AMIGA_PARTITION=y
+CONFIG_ATARI_PARTITION=y
+CONFIG_MAC_PARTITION=y
+CONFIG_BSD_DISKLABEL=y
+CONFIG_MINIX_SUBPARTITION=y
+CONFIG_SOLARIS_X86_PARTITION=y
+CONFIG_UNIXWARE_DISKLABEL=y
+CONFIG_LDM_PARTITION=y
+CONFIG_SGI_PARTITION=y
+CONFIG_ULTRIX_PARTITION=y
+CONFIG_SUN_PARTITION=y
+CONFIG_KARMA_PARTITION=y
+CONFIG_SYSV68_PARTITION=y
+CONFIG_CMDLINE_PARTITION=y
+CONFIG_MQ_IOSCHED_KYBER=m
+CONFIG_IOSCHED_BFQ=m
+CONFIG_BINFMT_MISC=m
+CONFIG_ZSWAP=y
+CONFIG_Z3FOLD=m
+CONFIG_ZSMALLOC=y
+CONFIG_SLAB_FREELIST_RANDOM=y
+CONFIG_SLAB_FREELIST_HARDENED=y
+CONFIG_RANDOM_KMALLOC_CACHES=y
+CONFIG_SHUFFLE_PAGE_ALLOCATOR=y
+# CONFIG_COMPAT_BRK is not set
+CONFIG_SPARSEMEM_MANUAL=y
+CONFIG_KSM=y
+CONFIG_DEFAULT_MMAP_MIN_ADDR=65536
+CONFIG_TRANSPARENT_HUGEPAGE=y
+CONFIG_TRANSPARENT_HUGEPAGE_MADVISE=y
+CONFIG_CMA=y
+CONFIG_CMA_SYSFS=y
+CONFIG_IDLE_PAGE_TRACKING=y
+CONFIG_ANON_VMA_NAME=y
+CONFIG_USERFAULTFD=y
+CONFIG_LRU_GEN=y
+CONFIG_LRU_GEN_ENABLED=y
+CONFIG_NET=y
+CONFIG_PACKET=y
+CONFIG_PACKET_DIAG=m
+CONFIG_UNIX_DIAG=m
+CONFIG_TLS=m
+CONFIG_TLS_DEVICE=y
+CONFIG_XFRM_USER=m
+CONFIG_XFRM_INTERFACE=m
+CONFIG_XFRM_STATISTICS=y
+CONFIG_NET_KEY=m
+CONFIG_XDP_SOCKETS=y
+CONFIG_XDP_SOCKETS_DIAG=m
+CONFIG_IP_MULTICAST=y
+CONFIG_IP_ADVANCED_ROUTER=y
+CONFIG_IP_FIB_TRIE_STATS=y
+CONFIG_IP_MULTIPLE_TABLES=y
+CONFIG_IP_ROUTE_MULTIPATH=y
+CONFIG_IP_ROUTE_VERBOSE=y
+CONFIG_NET_IPIP=m
+CONFIG_NET_IPGRE_DEMUX=m
+CONFIG_NET_IPGRE=m
+CONFIG_NET_IPGRE_BROADCAST=y
+CONFIG_IP_MROUTE=y
+CONFIG_IP_MROUTE_MULTIPLE_TABLES=y
+CONFIG_IP_PIMSM_V1=y
+CONFIG_IP_PIMSM_V2=y
+CONFIG_NET_IPVTI=m
+CONFIG_NET_FOU_IP_TUNNELS=y
+CONFIG_INET_AH=m
+CONFIG_INET_ESP=m
+CONFIG_INET_ESP_OFFLOAD=m
+CONFIG_INET_ESPINTCP=y
+CONFIG_INET_IPCOMP=m
+CONFIG_INET_DIAG=m
+CONFIG_INET_UDP_DIAG=m
+CONFIG_INET_RAW_DIAG=m
+CONFIG_INET_DIAG_DESTROY=y
+CONFIG_TCP_CONG_ADVANCED=y
+CONFIG_TCP_CONG_HSTCP=m
+CONFIG_TCP_CONG_HYBLA=m
+CONFIG_TCP_CONG_NV=m
+CONFIG_TCP_CONG_SCALABLE=m
+CONFIG_TCP_CONG_LP=m
+CONFIG_TCP_CONG_VENO=m
+CONFIG_TCP_CONG_YEAH=m
+CONFIG_TCP_CONG_ILLINOIS=m
+CONFIG_TCP_CONG_DCTCP=m
+CONFIG_TCP_CONG_CDG=m
+CONFIG_TCP_CONG_BBR=m
+CONFIG_TCP_MD5SIG=y
+CONFIG_IPV6_ROUTER_PREF=y
+CONFIG_IPV6_ROUTE_INFO=y
+CONFIG_INET6_AH=m
+CONFIG_INET6_ESP=m
+CONFIG_INET6_ESP_OFFLOAD=m
+CONFIG_INET6_ESPINTCP=y
+CONFIG_INET6_IPCOMP=m
+CONFIG_IPV6_MIP6=m
+CONFIG_IPV6_ILA=m
+CONFIG_IPV6_VTI=m
+CONFIG_IPV6_SIT=m
+CONFIG_IPV6_SIT_6RD=y
+CONFIG_IPV6_GRE=m
+CONFIG_IPV6_SUBTREES=y
+CONFIG_IPV6_MROUTE=y
+CONFIG_IPV6_MROUTE_MULTIPLE_TABLES=y
+CONFIG_IPV6_PIMSM_V2=y
+CONFIG_IPV6_SEG6_LWTUNNEL=y
+CONFIG_IPV6_SEG6_HMAC=y
+CONFIG_IPV6_IOAM6_LWTUNNEL=y
+CONFIG_MPTCP=y
+CONFIG_NETWORK_PHY_TIMESTAMPING=y
+CONFIG_NETFILTER=y
+CONFIG_BRIDGE_NETFILTER=m
+CONFIG_NETFILTER_NETLINK_HOOK=m
+CONFIG_NF_CONNTRACK=m
+CONFIG_NF_CONNTRACK_SECMARK=y
+CONFIG_NF_CONNTRACK_ZONES=y
+CONFIG_NF_CONNTRACK_EVENTS=y
+CONFIG_NF_CONNTRACK_TIMEOUT=y
+CONFIG_NF_CONNTRACK_TIMESTAMP=y
+CONFIG_NF_CONNTRACK_AMANDA=m
+CONFIG_NF_CONNTRACK_FTP=m
+CONFIG_NF_CONNTRACK_H323=m
+CONFIG_NF_CONNTRACK_IRC=m
+CONFIG_NF_CONNTRACK_NETBIOS_NS=m
+CONFIG_NF_CONNTRACK_SNMP=m
+CONFIG_NF_CONNTRACK_PPTP=m
+CONFIG_NF_CONNTRACK_SANE=m
+CONFIG_NF_CONNTRACK_SIP=m
+CONFIG_NF_CONNTRACK_TFTP=m
+CONFIG_NF_CT_NETLINK=m
+CONFIG_NF_CT_NETLINK_TIMEOUT=m
+CONFIG_NF_CT_NETLINK_HELPER=m
+CONFIG_NETFILTER_NETLINK_GLUE_CT=y
+CONFIG_NF_TABLES=m
+CONFIG_NF_TABLES_INET=y
+CONFIG_NF_TABLES_NETDEV=y
+CONFIG_NFT_NUMGEN=m
+CONFIG_NFT_CT=m
+CONFIG_NFT_FLOW_OFFLOAD=m
+CONFIG_NFT_CONNLIMIT=m
+CONFIG_NFT_LOG=m
+CONFIG_NFT_LIMIT=m
+CONFIG_NFT_MASQ=m
+CONFIG_NFT_REDIR=m
+CONFIG_NFT_NAT=m
+CONFIG_NFT_TUNNEL=m
+CONFIG_NFT_QUEUE=m
+CONFIG_NFT_QUOTA=m
+CONFIG_NFT_REJECT=m
+CONFIG_NFT_COMPAT=m
+CONFIG_NFT_HASH=m
+CONFIG_NFT_FIB_INET=m
+CONFIG_NFT_XFRM=m
+CONFIG_NFT_SOCKET=m
+CONFIG_NFT_OSF=m
+CONFIG_NFT_TPROXY=m
+CONFIG_NFT_SYNPROXY=m
+CONFIG_NFT_DUP_NETDEV=m
+CONFIG_NFT_FWD_NETDEV=m
+CONFIG_NFT_FIB_NETDEV=m
+CONFIG_NFT_REJECT_NETDEV=m
+CONFIG_NF_FLOW_TABLE_INET=m
+CONFIG_NF_FLOW_TABLE=m
+CONFIG_NETFILTER_XT_SET=m
+CONFIG_NETFILTER_XT_TARGET_AUDIT=m
+CONFIG_NETFILTER_XT_TARGET_CHECKSUM=m
+CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m
+CONFIG_NETFILTER_XT_TARGET_CONNMARK=m
+CONFIG_NETFILTER_XT_TARGET_CONNSECMARK=m
+CONFIG_NETFILTER_XT_TARGET_CT=m
+CONFIG_NETFILTER_XT_TARGET_DSCP=m
+CONFIG_NETFILTER_XT_TARGET_HMARK=m
+CONFIG_NETFILTER_XT_TARGET_IDLETIMER=m
+CONFIG_NETFILTER_XT_TARGET_LED=m
+CONFIG_NETFILTER_XT_TARGET_LOG=m
+CONFIG_NETFILTER_XT_TARGET_MARK=m
+CONFIG_NETFILTER_XT_TARGET_NFLOG=m
+CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m
+CONFIG_NETFILTER_XT_TARGET_TEE=m
+CONFIG_NETFILTER_XT_TARGET_TPROXY=m
+CONFIG_NETFILTER_XT_TARGET_TRACE=m
+CONFIG_NETFILTER_XT_TARGET_SECMARK=m
+CONFIG_NETFILTER_XT_TARGET_TCPMSS=m
+CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP=m
+CONFIG_NETFILTER_XT_MATCH_ADDRTYPE=m
+CONFIG_NETFILTER_XT_MATCH_BPF=m
+CONFIG_NETFILTER_XT_MATCH_CGROUP=m
+CONFIG_NETFILTER_XT_MATCH_CLUSTER=m
+CONFIG_NETFILTER_XT_MATCH_COMMENT=m
+CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m
+CONFIG_NETFILTER_XT_MATCH_CONNLABEL=m
+CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=m
+CONFIG_NETFILTER_XT_MATCH_CONNMARK=m
+CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m
+CONFIG_NETFILTER_XT_MATCH_CPU=m
+CONFIG_NETFILTER_XT_MATCH_DEVGROUP=m
+CONFIG_NETFILTER_XT_MATCH_DSCP=m
+CONFIG_NETFILTER_XT_MATCH_ESP=m
+CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m
+CONFIG_NETFILTER_XT_MATCH_HELPER=m
+CONFIG_NETFILTER_XT_MATCH_IPCOMP=m
+CONFIG_NETFILTER_XT_MATCH_IPRANGE=m
+CONFIG_NETFILTER_XT_MATCH_IPVS=m
+CONFIG_NETFILTER_XT_MATCH_LENGTH=m
+CONFIG_NETFILTER_XT_MATCH_LIMIT=m
+CONFIG_NETFILTER_XT_MATCH_MAC=m
+CONFIG_NETFILTER_XT_MATCH_MARK=m
+CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m
+CONFIG_NETFILTER_XT_MATCH_NFACCT=m
+CONFIG_NETFILTER_XT_MATCH_OSF=m
+CONFIG_NETFILTER_XT_MATCH_OWNER=m
+CONFIG_NETFILTER_XT_MATCH_POLICY=m
+CONFIG_NETFILTER_XT_MATCH_PHYSDEV=m
+CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m
+CONFIG_NETFILTER_XT_MATCH_QUOTA=m
+CONFIG_NETFILTER_XT_MATCH_RATEEST=m
+CONFIG_NETFILTER_XT_MATCH_REALM=m
+CONFIG_NETFILTER_XT_MATCH_RECENT=m
+CONFIG_NETFILTER_XT_MATCH_SOCKET=m
+CONFIG_NETFILTER_XT_MATCH_STATE=m
+CONFIG_NETFILTER_XT_MATCH_STATISTIC=m
+CONFIG_NETFILTER_XT_MATCH_STRING=m
+CONFIG_NETFILTER_XT_MATCH_TCPMSS=m
+CONFIG_NETFILTER_XT_MATCH_TIME=m
+CONFIG_NETFILTER_XT_MATCH_U32=m
+CONFIG_IP_SET=m
+CONFIG_IP_SET_BITMAP_IP=m
+CONFIG_IP_SET_BITMAP_IPMAC=m
+CONFIG_IP_SET_BITMAP_PORT=m
+CONFIG_IP_SET_HASH_IP=m
+CONFIG_IP_SET_HASH_IPMARK=m
+CONFIG_IP_SET_HASH_IPPORT=m
+CONFIG_IP_SET_HASH_IPPORTIP=m
+CONFIG_IP_SET_HASH_IPPORTNET=m
+CONFIG_IP_SET_HASH_IPMAC=m
+CONFIG_IP_SET_HASH_MAC=m
+CONFIG_IP_SET_HASH_NETPORTNET=m
+CONFIG_IP_SET_HASH_NET=m
+CONFIG_IP_SET_HASH_NETNET=m
+CONFIG_IP_SET_HASH_NETPORT=m
+CONFIG_IP_SET_HASH_NETIFACE=m
+CONFIG_IP_SET_LIST_SET=m
+CONFIG_IP_VS=m
+CONFIG_IP_VS_IPV6=y
+CONFIG_IP_VS_PROTO_TCP=y
+CONFIG_IP_VS_PROTO_UDP=y
+CONFIG_IP_VS_PROTO_ESP=y
+CONFIG_IP_VS_PROTO_AH=y
+CONFIG_IP_VS_PROTO_SCTP=y
+CONFIG_IP_VS_RR=m
+CONFIG_IP_VS_WRR=m
+CONFIG_IP_VS_LC=m
+CONFIG_IP_VS_WLC=m
+CONFIG_IP_VS_FO=m
+CONFIG_IP_VS_OVF=m
+CONFIG_IP_VS_LBLC=m
+CONFIG_IP_VS_LBLCR=m
+CONFIG_IP_VS_DH=m
+CONFIG_IP_VS_SH=m
+CONFIG_IP_VS_MH=m
+CONFIG_IP_VS_SED=m
+CONFIG_IP_VS_NQ=m
+CONFIG_IP_VS_TWOS=m
+CONFIG_IP_VS_FTP=m
+CONFIG_IP_VS_PE_SIP=m
+CONFIG_NFT_DUP_IPV4=m
+CONFIG_NFT_FIB_IPV4=m
+CONFIG_NF_TABLES_ARP=y
+CONFIG_NF_LOG_ARP=m
+CONFIG_NF_LOG_IPV4=m
+CONFIG_IP_NF_IPTABLES=m
+CONFIG_IP_NF_MATCH_AH=m
+CONFIG_IP_NF_MATCH_ECN=m
+CONFIG_IP_NF_MATCH_RPFILTER=m
+CONFIG_IP_NF_MATCH_TTL=m
+CONFIG_IP_NF_FILTER=m
+CONFIG_IP_NF_TARGET_REJECT=m
+CONFIG_IP_NF_TARGET_SYNPROXY=m
+CONFIG_IP_NF_NAT=m
+CONFIG_IP_NF_TARGET_MASQUERADE=m
+CONFIG_IP_NF_TARGET_NETMAP=m
+CONFIG_IP_NF_TARGET_REDIRECT=m
+CONFIG_IP_NF_MANGLE=m
+CONFIG_IP_NF_TARGET_ECN=m
+CONFIG_IP_NF_TARGET_TTL=m
+CONFIG_IP_NF_RAW=m
+CONFIG_IP_NF_SECURITY=m
+CONFIG_IP_NF_ARPTABLES=m
+CONFIG_IP_NF_ARPFILTER=m
+CONFIG_IP_NF_ARP_MANGLE=m
+CONFIG_NFT_DUP_IPV6=m
+CONFIG_NFT_FIB_IPV6=m
+CONFIG_IP6_NF_IPTABLES=m
+CONFIG_IP6_NF_MATCH_AH=m
+CONFIG_IP6_NF_MATCH_EUI64=m
+CONFIG_IP6_NF_MATCH_FRAG=m
+CONFIG_IP6_NF_MATCH_OPTS=m
+CONFIG_IP6_NF_MATCH_HL=m
+CONFIG_IP6_NF_MATCH_IPV6HEADER=m
+CONFIG_IP6_NF_MATCH_MH=m
+CONFIG_IP6_NF_MATCH_RPFILTER=m
+CONFIG_IP6_NF_MATCH_RT=m
+CONFIG_IP6_NF_MATCH_SRH=m
+CONFIG_IP6_NF_TARGET_HL=m
+CONFIG_IP6_NF_FILTER=m
+CONFIG_IP6_NF_TARGET_REJECT=m
+CONFIG_IP6_NF_TARGET_SYNPROXY=m
+CONFIG_IP6_NF_MANGLE=m
+CONFIG_IP6_NF_RAW=m
+CONFIG_IP6_NF_SECURITY=m
+CONFIG_IP6_NF_NAT=m
+CONFIG_IP6_NF_TARGET_MASQUERADE=m
+CONFIG_IP6_NF_TARGET_NPT=m
+CONFIG_NF_TABLES_BRIDGE=m
+CONFIG_NFT_BRIDGE_META=m
+CONFIG_NFT_BRIDGE_REJECT=m
+CONFIG_NF_CONNTRACK_BRIDGE=m
+CONFIG_BRIDGE_NF_EBTABLES=m
+CONFIG_BRIDGE_EBT_BROUTE=m
+CONFIG_BRIDGE_EBT_T_FILTER=m
+CONFIG_BRIDGE_EBT_T_NAT=m
+CONFIG_BRIDGE_EBT_802_3=m
+CONFIG_BRIDGE_EBT_AMONG=m
+CONFIG_BRIDGE_EBT_ARP=m
+CONFIG_BRIDGE_EBT_IP=m
+CONFIG_BRIDGE_EBT_IP6=m
+CONFIG_BRIDGE_EBT_LIMIT=m
+CONFIG_BRIDGE_EBT_MARK=m
+CONFIG_BRIDGE_EBT_PKTTYPE=m
+CONFIG_BRIDGE_EBT_STP=m
+CONFIG_BRIDGE_EBT_VLAN=m
+CONFIG_BRIDGE_EBT_ARPREPLY=m
+CONFIG_BRIDGE_EBT_DNAT=m
+CONFIG_BRIDGE_EBT_MARK_T=m
+CONFIG_BRIDGE_EBT_REDIRECT=m
+CONFIG_BRIDGE_EBT_SNAT=m
+CONFIG_BRIDGE_EBT_LOG=m
+CONFIG_BRIDGE_EBT_NFLOG=m
+CONFIG_BPFILTER=y
+CONFIG_IP_DCCP=m
+# CONFIG_IP_DCCP_CCID3 is not set
+CONFIG_SCTP_DEFAULT_COOKIE_HMAC_SHA1=y
+CONFIG_SCTP_COOKIE_HMAC_MD5=y
+CONFIG_RDS=m
+CONFIG_RDS_TCP=m
+CONFIG_TIPC=m
+CONFIG_ATM=m
+CONFIG_ATM_CLIP=m
+CONFIG_ATM_LANE=m
+CONFIG_ATM_MPOA=m
+CONFIG_ATM_BR2684=m
+CONFIG_L2TP=m
+CONFIG_L2TP_DEBUGFS=m
+CONFIG_L2TP_V3=y
+CONFIG_L2TP_IP=m
+CONFIG_L2TP_ETH=m
+CONFIG_BRIDGE=m
+CONFIG_BRIDGE_VLAN_FILTERING=y
+CONFIG_BRIDGE_MRP=y
+CONFIG_BRIDGE_CFM=y
+CONFIG_NET_DSA=m
+CONFIG_NET_DSA_TAG_RTL4_A=m
+CONFIG_NET_DSA_TAG_RTL8_4=m
+CONFIG_NET_DSA_TAG_RZN1_A5PSW=m
+CONFIG_VLAN_8021Q=m
+CONFIG_VLAN_8021Q_GVRP=y
+CONFIG_VLAN_8021Q_MVRP=y
+CONFIG_LLC2=m
+CONFIG_ATALK=m
+CONFIG_DEV_APPLETALK=m
+CONFIG_X25=m
+CONFIG_LAPB=m
+CONFIG_PHONET=m
+CONFIG_6LOWPAN=m
+CONFIG_IEEE802154=m
+CONFIG_IEEE802154_6LOWPAN=m
+CONFIG_MAC802154=m
+CONFIG_NET_SCHED=y
+CONFIG_NET_SCH_HTB=m
+CONFIG_NET_SCH_HFSC=m
+CONFIG_NET_SCH_PRIO=m
+CONFIG_NET_SCH_MULTIQ=m
+CONFIG_NET_SCH_RED=m
+CONFIG_NET_SCH_SFB=m
+CONFIG_NET_SCH_SFQ=m
+CONFIG_NET_SCH_TEQL=m
+CONFIG_NET_SCH_TBF=m
+CONFIG_NET_SCH_CBS=m
+CONFIG_NET_SCH_ETF=m
+CONFIG_NET_SCH_TAPRIO=m
+CONFIG_NET_SCH_GRED=m
+CONFIG_NET_SCH_NETEM=m
+CONFIG_NET_SCH_DRR=m
+CONFIG_NET_SCH_MQPRIO=m
+CONFIG_NET_SCH_SKBPRIO=m
+CONFIG_NET_SCH_CHOKE=m
+CONFIG_NET_SCH_QFQ=m
+CONFIG_NET_SCH_CODEL=m
+CONFIG_NET_SCH_FQ_CODEL=m
+CONFIG_NET_SCH_CAKE=m
+CONFIG_NET_SCH_FQ=m
+CONFIG_NET_SCH_HHF=m
+CONFIG_NET_SCH_PIE=m
+CONFIG_NET_SCH_FQ_PIE=m
+CONFIG_NET_SCH_INGRESS=m
+CONFIG_NET_SCH_PLUG=m
+CONFIG_NET_SCH_ETS=m
+CONFIG_NET_CLS_BASIC=m
+CONFIG_NET_CLS_ROUTE4=m
+CONFIG_NET_CLS_FW=m
+CONFIG_NET_CLS_U32=m
+CONFIG_CLS_U32_MARK=y
+CONFIG_NET_CLS_FLOW=m
+CONFIG_NET_CLS_CGROUP=m
+CONFIG_NET_CLS_BPF=m
+CONFIG_NET_CLS_FLOWER=m
+CONFIG_NET_CLS_MATCHALL=m
+CONFIG_NET_EMATCH=y
+CONFIG_NET_EMATCH_CMP=m
+CONFIG_NET_EMATCH_NBYTE=m
+CONFIG_NET_EMATCH_U32=m
+CONFIG_NET_EMATCH_META=m
+CONFIG_NET_EMATCH_TEXT=m
+CONFIG_NET_EMATCH_IPSET=m
+CONFIG_NET_EMATCH_IPT=m
+CONFIG_NET_CLS_ACT=y
+CONFIG_NET_ACT_POLICE=m
+CONFIG_NET_ACT_GACT=m
+CONFIG_GACT_PROB=y
+CONFIG_NET_ACT_MIRRED=m
+CONFIG_NET_ACT_SAMPLE=m
+CONFIG_NET_ACT_IPT=m
+CONFIG_NET_ACT_NAT=m
+CONFIG_NET_ACT_PEDIT=m
+CONFIG_NET_ACT_SIMP=m
+CONFIG_NET_ACT_SKBEDIT=m
+CONFIG_NET_ACT_CSUM=m
+CONFIG_NET_ACT_MPLS=m
+CONFIG_NET_ACT_VLAN=m
+CONFIG_NET_ACT_BPF=m
+CONFIG_NET_ACT_CONNMARK=m
+CONFIG_NET_ACT_CTINFO=m
+CONFIG_NET_ACT_SKBMOD=m
+CONFIG_NET_ACT_TUNNEL_KEY=m
+CONFIG_NET_ACT_CT=m
+CONFIG_NET_ACT_GATE=m
+CONFIG_NET_TC_SKB_EXT=y
+CONFIG_DCB=y
+CONFIG_DNS_RESOLVER=y
+CONFIG_BATMAN_ADV=m
+# CONFIG_BATMAN_ADV_BATMAN_V is not set
+CONFIG_BATMAN_ADV_NC=y
+CONFIG_OPENVSWITCH=m
+CONFIG_VSOCKETS=m
+CONFIG_VIRTIO_VSOCKETS=m
+CONFIG_NETLINK_DIAG=m
+CONFIG_MPLS_ROUTING=m
+CONFIG_MPLS_IPTUNNEL=m
+CONFIG_HSR=m
+CONFIG_QRTR_SMD=m
+CONFIG_QRTR_TUN=m
+CONFIG_NET_NCSI=y
+CONFIG_NCSI_OEM_CMD_GET_MAC=y
+CONFIG_CGROUP_NET_PRIO=y
+CONFIG_BPF_STREAM_PARSER=y
+CONFIG_NET_PKTGEN=m
+CONFIG_NET_DROP_MONITOR=y
+CONFIG_HAMRADIO=y
+CONFIG_AX25=m
+CONFIG_NETROM=m
+CONFIG_ROSE=m
+CONFIG_MKISS=m
+CONFIG_6PACK=m
+CONFIG_BPQETHER=m
+CONFIG_BAYCOM_SER_FDX=m
+CONFIG_BAYCOM_SER_HDX=m
+CONFIG_BAYCOM_PAR=m
+CONFIG_YAM=m
+CONFIG_BT=m
+CONFIG_BT_RFCOMM=m
+CONFIG_BT_RFCOMM_TTY=y
+CONFIG_BT_BNEP=m
+CONFIG_BT_BNEP_MC_FILTER=y
+CONFIG_BT_BNEP_PROTO_FILTER=y
+CONFIG_BT_CMTP=m
+CONFIG_BT_HIDP=m
+CONFIG_BT_HS=y
+CONFIG_BT_6LOWPAN=m
+CONFIG_BT_LEDS=y
+CONFIG_BT_MSFTEXT=y
+CONFIG_BT_AOSPEXT=y
+CONFIG_BT_HCIBTUSB=m
+CONFIG_BT_HCIBTUSB_AUTOSUSPEND=y
+CONFIG_BT_HCIBTUSB_MTK=y
+CONFIG_BT_HCIBTSDIO=m
+CONFIG_BT_HCIUART=m
+CONFIG_BT_HCIUART_NOKIA=m
+CONFIG_BT_HCIUART_BCSP=y
+CONFIG_BT_HCIUART_ATH3K=y
+CONFIG_BT_HCIUART_LL=y
+CONFIG_BT_HCIUART_INTEL=y
+CONFIG_BT_HCIUART_BCM=y
+CONFIG_BT_HCIUART_RTL=y
+CONFIG_BT_HCIUART_QCA=y
+CONFIG_BT_HCIUART_AG6XX=y
+CONFIG_BT_HCIUART_MRVL=y
+CONFIG_BT_HCIBCM203X=m
+CONFIG_BT_HCIBCM4377=m
+CONFIG_BT_HCIBPA10X=m
+CONFIG_BT_HCIBFUSB=m
+CONFIG_BT_HCIVHCI=m
+CONFIG_BT_MRVL=m
+CONFIG_BT_MRVL_SDIO=m
+CONFIG_BT_ATH3K=m
+CONFIG_BT_MTKSDIO=m
+CONFIG_BT_MTKUART=m
+CONFIG_BT_VIRTIO=m
+CONFIG_BT_NXPUART=m
+CONFIG_AF_RXRPC_IPV6=y
+CONFIG_RXKAD=y
+CONFIG_RXPERF=m
+CONFIG_AF_KCM=m
+CONFIG_MCTP=y
+CONFIG_CFG80211_DEBUGFS=y
+CONFIG_MAC80211=m
+CONFIG_MAC80211_MESH=y
+CONFIG_MAC80211_MESSAGE_TRACING=y
+CONFIG_RFKILL=y
+CONFIG_RFKILL_INPUT=y
+CONFIG_RFKILL_GPIO=m
+CONFIG_NET_9P=m
+CONFIG_NET_9P_VIRTIO=m
+CONFIG_CAIF=m
+CONFIG_CAIF_USB=m
+CONFIG_CEPH_LIB_USE_DNS_RESOLVER=y
+CONFIG_NET_IFE=m
+CONFIG_PAGE_POOL_STATS=y
+CONFIG_PCI=y
+CONFIG_PCIEPORTBUS=y
+CONFIG_HOTPLUG_PCI_PCIE=y
+CONFIG_PCIEAER=y
+CONFIG_PCIE_DPC=y
+CONFIG_PCIE_PTM=y
+CONFIG_PCI_REALLOC_ENABLE_AUTO=y
+CONFIG_PCI_STUB=m
+CONFIG_PCI_PF_STUB=m
+CONFIG_PCI_IOV=y
+CONFIG_PCI_PRI=y
+CONFIG_PCI_PASID=y
+CONFIG_PCI_DYNAMIC_OF_NODES=y
+CONFIG_HOTPLUG_PCI=y
+CONFIG_HOTPLUG_PCI_CPCI=y
+CONFIG_HOTPLUG_PCI_SHPC=y
+CONFIG_PCI_FTPCI100=y
+CONFIG_PCI_HOST_GENERIC=y
+CONFIG_PCIE_MICROCHIP_HOST=y
+CONFIG_PCIE_XILINX=y
+CONFIG_PCIE_CADENCE_PLAT_HOST=y
+CONFIG_PCIE_CADENCE_PLAT_EP=y
+CONFIG_PCI_J721E_HOST=y
+CONFIG_PCI_J721E_EP=y
+CONFIG_PCIE_DW_PLAT_HOST=y
+CONFIG_PCIE_DW_PLAT_EP=y
+CONFIG_PCIE_FU740=y
+CONFIG_PCIE_ESWIN=y
+CONFIG_PCI_ENDPOINT=y
+CONFIG_PCI_ENDPOINT_CONFIGFS=y
+CONFIG_PCI_EPF_NTB=m
+CONFIG_PCI_EPF_MHI=m
+CONFIG_PCI_SW_SWITCHTEC=m
+CONFIG_CXL_BUS=m
+CONFIG_UEVENT_HELPER=y
+CONFIG_DEVTMPFS=y
+CONFIG_DEVTMPFS_MOUNT=y
+CONFIG_DEVTMPFS_SAFE=y
+CONFIG_FW_LOADER_USER_HELPER=y
+CONFIG_FW_LOADER_COMPRESS=y
+CONFIG_FW_LOADER_COMPRESS_ZSTD=y
+CONFIG_MOXTET=m
+CONFIG_MHI_BUS_PCI_GENERIC=m
+CONFIG_MHI_BUS_EP=m
+CONFIG_CONNECTOR=y
+CONFIG_FIRMWARE_MEMMAP=y
+CONFIG_SYSFB_SIMPLEFB=y
+CONFIG_EFI_VARS_PSTORE=m
+CONFIG_EFI_BOOTLOADER_CONTROL=m
+CONFIG_EFI_CAPSULE_LOADER=m
+CONFIG_EFI_TEST=m
+CONFIG_RESET_ATTACK_MITIGATION=y
+CONFIG_EFI_COCO_SECRET=y
+CONFIG_GNSS=m
+CONFIG_GNSS_MTK_SERIAL=m
+CONFIG_GNSS_SIRF_SERIAL=m
+CONFIG_GNSS_UBX_SERIAL=m
+CONFIG_GNSS_USB=m
+CONFIG_MTD=m
+CONFIG_MTD_AR7_PARTS=m
+CONFIG_MTD_CMDLINE_PARTS=m
+CONFIG_MTD_REDBOOT_PARTS=m
+CONFIG_MTD_BLOCK=m
+CONFIG_MTD_BLOCK_RO=m
+CONFIG_FTL=m
+CONFIG_NFTL=m
+CONFIG_NFTL_RW=y
+CONFIG_INFTL=m
+CONFIG_RFD_FTL=m
+CONFIG_SSFDC=m
+CONFIG_SM_FTL=m
+CONFIG_MTD_OOPS=m
+CONFIG_MTD_PSTORE=m
+CONFIG_MTD_SWAP=m
+CONFIG_MTD_JEDECPROBE=m
+CONFIG_MTD_CFI_INTELEXT=m
+CONFIG_MTD_CFI_STAA=m
+CONFIG_MTD_ROM=m
+CONFIG_MTD_ABSENT=m
+CONFIG_MTD_PHYSMAP=m
+CONFIG_MTD_PHYSMAP_OF=y
+CONFIG_MTD_PHYSMAP_GPIO_ADDR=y
+CONFIG_MTD_PCI=m
+CONFIG_MTD_INTEL_VR_NOR=m
+CONFIG_MTD_PLATRAM=m
+CONFIG_MTD_PMC551=m
+CONFIG_MTD_DATAFLASH=m
+CONFIG_MTD_DATAFLASH_OTP=y
+CONFIG_MTD_MCHP23K256=m
+CONFIG_MTD_MCHP48L640=m
+CONFIG_MTD_SST25L=m
+CONFIG_MTD_SLRAM=m
+CONFIG_MTD_PHRAM=m
+CONFIG_MTD_MTDRAM=m
+CONFIG_MTD_BLOCK2MTD=m
+CONFIG_MTD_ONENAND=m
+CONFIG_MTD_ONENAND_VERIFY_WRITE=y
+CONFIG_MTD_ONENAND_GENERIC=m
+CONFIG_MTD_ONENAND_2X_PROGRAM=y
+CONFIG_MTD_RAW_NAND=m
+CONFIG_MTD_NAND_DENALI_PCI=m
+CONFIG_MTD_NAND_DENALI_DT=m
+CONFIG_MTD_NAND_CAFE=m
+CONFIG_MTD_NAND_MXIC=m
+CONFIG_MTD_NAND_GPIO=m
+CONFIG_MTD_NAND_PLATFORM=m
+CONFIG_MTD_NAND_CADENCE=m
+CONFIG_MTD_NAND_ARASAN=m
+CONFIG_MTD_NAND_INTEL_LGM=m
+CONFIG_MTD_NAND_NANDSIM=m
+CONFIG_MTD_NAND_RICOH=m
+CONFIG_MTD_NAND_DISKONCHIP=m
+CONFIG_MTD_SPI_NAND=m
+CONFIG_MTD_NAND_ECC_SW_BCH=y
+CONFIG_MTD_NAND_ECC_MXIC=y
+CONFIG_MTD_LPDDR=m
+CONFIG_MTD_SPI_NOR=m
+CONFIG_MTD_UBI=m
+CONFIG_MTD_UBI_FASTMAP=y
+CONFIG_MTD_UBI_GLUEBI=m
+CONFIG_MTD_UBI_BLOCK=y
+CONFIG_MTD_HYPERBUS=m
+CONFIG_OF_OVERLAY=y
+CONFIG_PARPORT=m
+CONFIG_PARPORT_PC=m
+CONFIG_PARPORT_PC_FIFO=y
+CONFIG_PARPORT_1284=y
+CONFIG_BLK_DEV_NULL_BLK=m
+CONFIG_BLK_DEV_PCIESSD_MTIP32XX=m
+CONFIG_ZRAM=m
+CONFIG_ZRAM_WRITEBACK=y
+CONFIG_ZRAM_MEMORY_TRACKING=y
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_BLK_DEV_DRBD=m
+CONFIG_BLK_DEV_NBD=m
+CONFIG_BLK_DEV_RAM=m
+CONFIG_BLK_DEV_RAM_SIZE=65536
+CONFIG_ATA_OVER_ETH=m
+CONFIG_VIRTIO_BLK=y
+CONFIG_BLK_DEV_RBD=m
+CONFIG_BLK_DEV_UBLK=m
+# CONFIG_BLKDEV_UBLK_LEGACY_OPCODES is not set
+CONFIG_BLK_DEV_NVME=m
+CONFIG_NVME_MULTIPATH=y
+CONFIG_NVME_HWMON=y
+CONFIG_NVME_FC=m
+CONFIG_NVME_TCP=m
+CONFIG_NVME_AUTH=y
+CONFIG_NVME_TARGET=m
+CONFIG_NVME_TARGET_PASSTHRU=y
+CONFIG_NVME_TARGET_LOOP=m
+CONFIG_NVME_TARGET_FC=m
+CONFIG_NVME_TARGET_TCP=m
+CONFIG_NVME_TARGET_AUTH=y
+CONFIG_DUMMY_IRQ=m
+CONFIG_PHANTOM=m
+CONFIG_ICS932S401=m
+CONFIG_ENCLOSURE_SERVICES=m
+CONFIG_HI6421V600_IRQ=m
+CONFIG_APDS9802ALS=m
+CONFIG_ISL29003=m
+CONFIG_ISL29020=m
+CONFIG_SENSORS_TSL2550=m
+CONFIG_SENSORS_BH1770=m
+CONFIG_SENSORS_APDS990X=m
+CONFIG_HMC6352=m
+CONFIG_DS1682=m
+CONFIG_LATTICE_ECP3_CONFIG=m
+CONFIG_SRAM=y
+CONFIG_DW_XDATA_PCIE=m
+CONFIG_XILINX_SDFEC=m
+CONFIG_OPEN_DICE=m
+CONFIG_VCPU_STALL_DETECTOR=m
+CONFIG_C2PORT=m
+CONFIG_EEPROM_AT24=m
+CONFIG_EEPROM_AT25=m
+CONFIG_EEPROM_LEGACY=m
+CONFIG_EEPROM_MAX6875=m
+CONFIG_EEPROM_93XX46=m
+CONFIG_EEPROM_IDT_89HPESX=m
+CONFIG_EEPROM_EE1004=m
+CONFIG_TI_ST=m
+CONFIG_SENSORS_LIS3_I2C=m
+CONFIG_GENWQE=m
+CONFIG_ECHO=m
+CONFIG_BCM_VK=m
+CONFIG_BCM_VK_TTY=y
+CONFIG_MISC_ALCOR_PCI=m
+CONFIG_MISC_RTSX_PCI=m
+CONFIG_MISC_RTSX_USB=m
+CONFIG_UACCE=m
+CONFIG_PVPANIC=y
+CONFIG_PVPANIC_MMIO=m
+CONFIG_PVPANIC_PCI=m
+CONFIG_GP_PCI1XXXX=m
+CONFIG_RAID_ATTRS=m
+# CONFIG_SCSI_PROC_FS is not set
+CONFIG_BLK_DEV_SD=y
+CONFIG_CHR_DEV_ST=m
+CONFIG_BLK_DEV_SR=y
+CONFIG_CHR_DEV_SG=y
+# CONFIG_BLK_DEV_BSG is not set
+CONFIG_CHR_DEV_SCH=y
+CONFIG_SCSI_FC_ATTRS=m
+CONFIG_SCSI_SAS_LIBSAS=m
+CONFIG_SCSI_SAS_ATA=y
+# CONFIG_SCSI_LOWLEVEL is not set
+CONFIG_ATA=y
+CONFIG_SATA_AHCI=m
+CONFIG_SATA_MOBILE_LPM_POLICY=3
+CONFIG_SATA_AHCI_PLATFORM=m
+CONFIG_AHCI_DWC=m
+CONFIG_AHCI_CEVA=m
+CONFIG_AHCI_ESWIN=y
+CONFIG_SATA_INIC162X=m
+CONFIG_SATA_ACARD_AHCI=m
+CONFIG_SATA_SIL24=m
+CONFIG_PDC_ADMA=m
+CONFIG_SATA_QSTOR=m
+CONFIG_SATA_SX4=m
+CONFIG_ATA_PIIX=m
+CONFIG_SATA_DWC=m
+CONFIG_SATA_DWC_OLD_DMA=y
+CONFIG_SATA_MV=m
+CONFIG_SATA_NV=m
+CONFIG_SATA_PROMISE=m
+CONFIG_SATA_SIL=m
+CONFIG_SATA_SIS=m
+CONFIG_SATA_SVW=m
+CONFIG_SATA_ULI=m
+CONFIG_SATA_VIA=m
+CONFIG_SATA_VITESSE=m
+CONFIG_ATA_GENERIC=m
+CONFIG_MD=y
+CONFIG_BCACHE=m
+CONFIG_BCACHE_ASYNC_REGISTRATION=y
+CONFIG_BLK_DEV_DM=y
+CONFIG_DM_UNSTRIPED=m
+CONFIG_DM_CRYPT=m
+CONFIG_DM_SNAPSHOT=m
+CONFIG_DM_THIN_PROVISIONING=m
+CONFIG_DM_CACHE=m
+CONFIG_DM_WRITECACHE=m
+CONFIG_DM_EBS=m
+CONFIG_DM_ERA=m
+CONFIG_DM_CLONE=m
+CONFIG_DM_MIRROR=m
+CONFIG_DM_LOG_USERSPACE=m
+CONFIG_DM_ZERO=m
+CONFIG_DM_MULTIPATH=m
+CONFIG_DM_MULTIPATH_QL=m
+CONFIG_DM_MULTIPATH_ST=m
+CONFIG_DM_MULTIPATH_HST=m
+CONFIG_DM_MULTIPATH_IOA=m
+CONFIG_DM_DELAY=m
+CONFIG_DM_INIT=y
+CONFIG_DM_UEVENT=y
+CONFIG_DM_FLAKEY=m
+CONFIG_DM_VERITY=m
+CONFIG_DM_VERITY_VERIFY_ROOTHASH_SIG=y
+CONFIG_DM_SWITCH=m
+CONFIG_DM_LOG_WRITES=m
+CONFIG_DM_ZONED=m
+CONFIG_DM_AUDIT=y
+CONFIG_TARGET_CORE=m
+CONFIG_TCM_IBLOCK=m
+CONFIG_TCM_FILEIO=m
+CONFIG_TCM_PSCSI=m
+CONFIG_TCM_USER2=m
+CONFIG_LOOPBACK_TARGET=m
+CONFIG_ISCSI_TARGET=m
+CONFIG_REMOTE_TARGET=m
+CONFIG_FUSION=y
+CONFIG_FUSION_SPI=m
+CONFIG_FUSION_FC=m
+CONFIG_FUSION_SAS=m
+CONFIG_FUSION_CTL=m
+CONFIG_FUSION_LAN=m
+CONFIG_FUSION_LOGGING=y
+CONFIG_NETDEVICES=y
+CONFIG_BONDING=m
+CONFIG_DUMMY=m
+CONFIG_WIREGUARD=m
+CONFIG_EQUALIZER=m
+CONFIG_NET_FC=y
+CONFIG_IFB=m
+CONFIG_NET_TEAM=m
+CONFIG_NET_TEAM_MODE_BROADCAST=m
+CONFIG_NET_TEAM_MODE_ROUNDROBIN=m
+CONFIG_NET_TEAM_MODE_RANDOM=m
+CONFIG_NET_TEAM_MODE_ACTIVEBACKUP=m
+CONFIG_NET_TEAM_MODE_LOADBALANCE=m
+CONFIG_MACVLAN=m
+CONFIG_MACVTAP=m
+CONFIG_IPVLAN=m
+CONFIG_IPVTAP=m
+CONFIG_VXLAN=m
+CONFIG_GENEVE=m
+CONFIG_BAREUDP=m
+CONFIG_GTP=m
+CONFIG_AMT=m
+CONFIG_MACSEC=m
+CONFIG_NETCONSOLE=m
+CONFIG_NETCONSOLE_DYNAMIC=y
+CONFIG_TUN=y
+CONFIG_VETH=m
+CONFIG_VIRTIO_NET=y
+CONFIG_NLMON=m
+CONFIG_NET_VRF=m
+CONFIG_VSOCKMON=m
+CONFIG_MHI_NET=m
+CONFIG_ARCNET=m
+CONFIG_ARCNET_1201=m
+CONFIG_ARCNET_1051=m
+CONFIG_ARCNET_RAW=m
+CONFIG_ARCNET_CAP=m
+CONFIG_ARCNET_COM90xx=m
+CONFIG_ARCNET_COM90xxIO=m
+CONFIG_ARCNET_RIM_I=m
+CONFIG_ARCNET_COM20020=m
+CONFIG_ARCNET_COM20020_PCI=m
+CONFIG_ATM_DUMMY=m
+CONFIG_ATM_TCP=m
+CONFIG_ATM_LANAI=m
+CONFIG_ATM_ENI=m
+CONFIG_ATM_NICSTAR=m
+CONFIG_ATM_IDT77252=m
+CONFIG_ATM_IA=m
+CONFIG_ATM_FORE200E=m
+CONFIG_ATM_HE=m
+CONFIG_ATM_HE_USE_SUNI=y
+CONFIG_ATM_SOLOS=m
+CONFIG_CAIF_DRIVERS=y
+CONFIG_CAIF_TTY=m
+CONFIG_CAIF_VIRTIO=m
+CONFIG_B53_SPI_DRIVER=m
+CONFIG_B53_MDIO_DRIVER=m
+CONFIG_B53_MMAP_DRIVER=m
+CONFIG_B53_SRAB_DRIVER=m
+CONFIG_B53_SERDES=m
+CONFIG_NET_DSA_BCM_SF2=m
+CONFIG_NET_DSA_HIRSCHMANN_HELLCREEK=m
+CONFIG_NET_DSA_LANTIQ_GSWIP=m
+CONFIG_NET_DSA_MT7530=m
+CONFIG_NET_DSA_MV88E6060=m
+CONFIG_NET_DSA_MICROCHIP_KSZ_COMMON=m
+CONFIG_NET_DSA_MICROCHIP_KSZ9477_I2C=m
+CONFIG_NET_DSA_MICROCHIP_KSZ_SPI=m
+CONFIG_NET_DSA_MICROCHIP_KSZ_PTP=y
+CONFIG_NET_DSA_MICROCHIP_KSZ8863_SMI=m
+CONFIG_NET_DSA_MV88E6XXX=m
+CONFIG_NET_DSA_MV88E6XXX_PTP=y
+CONFIG_NET_DSA_MSCC_OCELOT_EXT=m
+CONFIG_NET_DSA_MSCC_SEVILLE=m
+CONFIG_NET_DSA_AR9331=m
+CONFIG_NET_DSA_QCA8K=m
+CONFIG_NET_DSA_QCA8K_LEDS_SUPPORT=y
+CONFIG_NET_DSA_SJA1105=m
+CONFIG_NET_DSA_SJA1105_PTP=y
+CONFIG_NET_DSA_SJA1105_TAS=y
+CONFIG_NET_DSA_SJA1105_VL=y
+CONFIG_NET_DSA_XRS700X_I2C=m
+CONFIG_NET_DSA_XRS700X_MDIO=m
+CONFIG_NET_DSA_SMSC_LAN9303_I2C=m
+CONFIG_NET_DSA_SMSC_LAN9303_MDIO=m
+CONFIG_NET_DSA_VITESSE_VSC73XX_SPI=m
+CONFIG_NET_DSA_VITESSE_VSC73XX_PLATFORM=m
+CONFIG_VORTEX=m
+CONFIG_TYPHOON=m
+CONFIG_ADAPTEC_STARFIRE=m
+CONFIG_ET131X=m
+CONFIG_SLICOSS=m
+CONFIG_ACENIC=m
+CONFIG_ALTERA_TSE=m
+CONFIG_ENA_ETHERNET=m
+CONFIG_AMD8111_ETH=m
+CONFIG_PCNET32=m
+CONFIG_PDS_CORE=m
+CONFIG_AQTION=m
+CONFIG_SPI_AX88796C=m
+CONFIG_ATL2=m
+CONFIG_ATL1=m
+CONFIG_ATL1E=m
+CONFIG_ATL1C=m
+CONFIG_ALX=m
+CONFIG_B44=m
+CONFIG_BCMGENET=m
+CONFIG_BNX2=m
+CONFIG_TIGON3=m
+CONFIG_BNX2X=m
+CONFIG_SYSTEMPORT=m
+CONFIG_BNXT=m
+CONFIG_BNXT_DCB=y
+CONFIG_MACB=m
+CONFIG_MACB_PCI=m
+# CONFIG_NET_VENDOR_CAVIUM is not set
+# CONFIG_NET_VENDOR_CHELSIO is not set
+CONFIG_ENIC=m
+CONFIG_GEMINI_ETHERNET=m
+CONFIG_DM9051=m
+CONFIG_DNET=m
+CONFIG_NET_TULIP=y
+CONFIG_DE2104X=m
+CONFIG_TULIP=m
+CONFIG_WINBOND_840=m
+CONFIG_DM9102=m
+CONFIG_ULI526X=m
+CONFIG_DL2K=m
+CONFIG_SUNDANCE=m
+CONFIG_TSNEP=m
+CONFIG_EZCHIP_NPS_MANAGEMENT_ENET=m
+CONFIG_FUN_ETH=m
+CONFIG_E100=m
+CONFIG_E1000=m
+CONFIG_E1000E=m
+CONFIG_IGB=m
+CONFIG_IGBVF=m
+CONFIG_IXGBE=m
+CONFIG_IXGBE_DCB=y
+CONFIG_IXGBEVF=m
+CONFIG_I40E=m
+CONFIG_I40E_DCB=y
+CONFIG_I40EVF=m
+CONFIG_ICE=m
+CONFIG_FM10K=m
+CONFIG_IGC=m
+CONFIG_JME=m
+CONFIG_ADIN1110=m
+CONFIG_LITEX_LITEETH=m
+CONFIG_MVMDIO=m
+CONFIG_SKGE=m
+CONFIG_SKGE_GENESIS=y
+CONFIG_SKY2=m
+CONFIG_OCTEON_EP=m
+CONFIG_PRESTERA=m
+CONFIG_MLXSW_CORE=m
+CONFIG_KS8842=m
+CONFIG_KS8851=m
+CONFIG_KS8851_MLL=m
+CONFIG_KSZ884X_PCI=m
+CONFIG_ENC28J60=m
+CONFIG_ENCX24J600=m
+CONFIG_LAN743X=m
+CONFIG_LAN966X_SWITCH=m
+CONFIG_MSCC_OCELOT_SWITCH=m
+CONFIG_MYRI10GE=m
+CONFIG_FEALNX=m
+CONFIG_NI_XGE_MANAGEMENT_ENET=m
+CONFIG_NATSEMI=m
+CONFIG_NS83820=m
+CONFIG_S2IO=m
+CONFIG_NFP=m
+CONFIG_NE2K_PCI=m
+CONFIG_FORCEDETH=m
+CONFIG_ETHOC=m
+CONFIG_HAMACHI=m
+CONFIG_YELLOWFIN=m
+CONFIG_IONIC=m
+CONFIG_QLA3XXX=m
+CONFIG_QLCNIC=m
+CONFIG_NETXEN_NIC=m
+CONFIG_QED=m
+CONFIG_QEDE=m
+CONFIG_BNA=m
+CONFIG_QCA7000_SPI=m
+CONFIG_QCA7000_UART=m
+CONFIG_QCOM_EMAC=m
+CONFIG_RMNET=m
+CONFIG_R6040=m
+CONFIG_8139CP=m
+CONFIG_8139TOO=m
+CONFIG_8139TOO_8129=y
+CONFIG_ROCKER=m
+CONFIG_SXGBE_ETH=m
+CONFIG_SC92031=m
+CONFIG_SIS900=m
+CONFIG_SIS190=m
+CONFIG_SFC=m
+CONFIG_SFC_FALCON=m
+CONFIG_SFC_SIENA=m
+CONFIG_SFC_SIENA_SRIOV=y
+CONFIG_EPIC100=m
+CONFIG_SMSC911X=m
+CONFIG_SMSC9420=m
+CONFIG_STMMAC_ETH=m
+CONFIG_DWMAC_DWC_QOS_ETH=m
+CONFIG_DWMAC_EIC7700=m
+CONFIG_DWMAC_INTEL_PLAT=m
+CONFIG_STMMAC_PCI=m
+CONFIG_HAPPYMEAL=m
+CONFIG_SUNGEM=m
+CONFIG_CASSINI=m
+CONFIG_NIU=m
+CONFIG_DWC_XLGMAC=m
+CONFIG_DWC_XLGMAC_PCI=m
+CONFIG_TEHUTI=m
+CONFIG_TLAN=m
+CONFIG_MSE102X=m
+CONFIG_VIA_RHINE=m
+CONFIG_VIA_RHINE_MMIO=y
+CONFIG_VIA_VELOCITY=m
+CONFIG_NGBE=m
+CONFIG_TXGBE=m
+CONFIG_WIZNET_W5100=m
+CONFIG_WIZNET_W5300=m
+CONFIG_WIZNET_W5100_SPI=m
+CONFIG_XILINX_EMACLITE=m
+CONFIG_XILINX_AXI_EMAC=m
+CONFIG_XILINX_LL_TEMAC=m
+CONFIG_FDDI=y
+CONFIG_DEFXX=m
+CONFIG_SKFP=m
+CONFIG_PHYLIB=y
+CONFIG_LED_TRIGGER_PHY=y
+CONFIG_AMD_PHY=m
+CONFIG_ADIN_PHY=m
+CONFIG_ADIN1100_PHY=m
+CONFIG_AQUANTIA_PHY=m
+CONFIG_BROADCOM_PHY=m
+CONFIG_BCM54140_PHY=m
+CONFIG_BCM84881_PHY=m
+CONFIG_BCM87XX_PHY=m
+CONFIG_CICADA_PHY=m
+CONFIG_CORTINA_PHY=m
+CONFIG_DAVICOM_PHY=m
+CONFIG_ICPLUS_PHY=m
+CONFIG_LXT_PHY=m
+CONFIG_INTEL_XWAY_PHY=m
+CONFIG_LSI_ET1011C_PHY=m
+CONFIG_MARVELL_PHY=m
+CONFIG_MARVELL_88Q2XXX_PHY=m
+CONFIG_MARVELL_88X2222_PHY=m
+CONFIG_MAXLINEAR_GPHY=m
+CONFIG_MICROCHIP_T1S_PHY=m
+CONFIG_MICROCHIP_T1_PHY=m
+CONFIG_MICROSEMI_PHY=m
+CONFIG_MOTORCOMM_PHY=m
+CONFIG_NATIONAL_PHY=m
+CONFIG_NXP_CBTX_PHY=m
+CONFIG_NXP_C45_TJA11XX_PHY=m
+CONFIG_NXP_TJA11XX_PHY=m
+CONFIG_NCN26000_PHY=m
+CONFIG_AT803X_PHY=m
+CONFIG_QSEMI_PHY=m
+CONFIG_RENESAS_PHY=m
+CONFIG_ROCKCHIP_PHY=m
+CONFIG_STE10XP=m
+CONFIG_TERANETICS_PHY=m
+CONFIG_DP83822_PHY=m
+CONFIG_DP83TC811_PHY=m
+CONFIG_DP83848_PHY=m
+CONFIG_DP83867_PHY=m
+CONFIG_DP83869_PHY=m
+CONFIG_DP83TD510_PHY=m
+CONFIG_XILINX_GMII2RGMII=m
+CONFIG_MICREL_KS8995MA=m
+CONFIG_PSE_CONTROLLER=y
+CONFIG_PSE_REGULATOR=m
+CONFIG_MCTP_SERIAL=m
+CONFIG_MCTP_TRANSPORT_I2C=m
+CONFIG_MDIO_GPIO=m
+CONFIG_MDIO_HISI_FEMAC=m
+CONFIG_MDIO_MVUSB=m
+CONFIG_MDIO_OCTEON=m
+CONFIG_MDIO_IPQ4019=m
+CONFIG_MDIO_IPQ8064=m
+CONFIG_MDIO_BUS_MUX_GPIO=m
+CONFIG_MDIO_BUS_MUX_MULTIPLEXER=m
+CONFIG_MDIO_BUS_MUX_MMIOREG=m
+CONFIG_PLIP=m
+CONFIG_PPP=y
+CONFIG_PPP_BSDCOMP=m
+CONFIG_PPP_DEFLATE=m
+CONFIG_PPP_FILTER=y
+CONFIG_PPP_MPPE=m
+CONFIG_PPP_MULTILINK=y
+CONFIG_PPPOATM=m
+CONFIG_PPPOE=m
+CONFIG_PPTP=m
+CONFIG_PPPOL2TP=m
+CONFIG_PPP_ASYNC=m
+CONFIG_PPP_SYNC_TTY=m
+CONFIG_SLIP=m
+CONFIG_SLIP_COMPRESSED=y
+CONFIG_SLIP_SMART=y
+CONFIG_SLIP_MODE_SLIP6=y
+CONFIG_USB_NET_DRIVERS=m
+CONFIG_USB_CATC=m
+CONFIG_USB_KAWETH=m
+CONFIG_USB_PEGASUS=m
+CONFIG_USB_RTL8150=m
+CONFIG_USB_RTL8152=m
+CONFIG_USB_LAN78XX=m
+CONFIG_USB_NET_CDC_EEM=m
+CONFIG_USB_NET_HUAWEI_CDC_NCM=m
+CONFIG_USB_NET_CDC_MBIM=m
+CONFIG_USB_NET_DM9601=m
+CONFIG_USB_NET_SR9700=m
+CONFIG_USB_NET_SR9800=m
+CONFIG_USB_NET_SMSC75XX=m
+CONFIG_USB_NET_SMSC95XX=m
+CONFIG_USB_NET_GL620A=m
+CONFIG_USB_NET_PLUSB=m
+CONFIG_USB_NET_MCS7830=m
+CONFIG_USB_ALI_M5632=y
+CONFIG_USB_AN2720=y
+CONFIG_USB_EPSON2888=y
+CONFIG_USB_KC2190=y
+CONFIG_USB_NET_CX82310_ETH=m
+CONFIG_USB_NET_KALMIA=m
+CONFIG_USB_NET_QMI_WWAN=m
+CONFIG_USB_HSO=m
+CONFIG_USB_NET_INT51X1=m
+CONFIG_USB_CDC_PHONET=m
+CONFIG_USB_IPHETH=m
+CONFIG_USB_SIERRA_NET=m
+CONFIG_USB_VL600=m
+CONFIG_USB_NET_CH9200=m
+CONFIG_USB_NET_AQC111=m
+CONFIG_ADM8211=m
+CONFIG_ATH5K=m
+CONFIG_ATH9K=m
+CONFIG_ATH9K_AHB=y
+CONFIG_ATH9K_DEBUGFS=y
+CONFIG_ATH9K_STATION_STATISTICS=y
+CONFIG_ATH9K_WOW=y
+CONFIG_ATH9K_CHANNEL_CONTEXT=y
+CONFIG_ATH9K_PCI_NO_EEPROM=m
+CONFIG_ATH9K_HTC=m
+CONFIG_ATH9K_HTC_DEBUGFS=y
+CONFIG_ATH9K_HWRNG=y
+CONFIG_ATH9K_COMMON_SPECTRAL=y
+CONFIG_CARL9170=m
+CONFIG_CARL9170_HWRNG=y
+CONFIG_ATH6KL=m
+CONFIG_ATH6KL_SDIO=m
+CONFIG_ATH6KL_USB=m
+CONFIG_AR5523=m
+CONFIG_WIL6210=m
+CONFIG_WIL6210_TRACING=y
+CONFIG_ATH10K=m
+CONFIG_ATH10K_PCI=m
+CONFIG_ATH10K_AHB=y
+CONFIG_ATH10K_SDIO=m
+CONFIG_ATH10K_USB=m
+CONFIG_ATH10K_DEBUGFS=y
+CONFIG_ATH10K_SPECTRAL=y
+CONFIG_ATH10K_TRACING=y
+CONFIG_WCN36XX=m
+CONFIG_ATH11K=m
+CONFIG_ATH11K_PCI=m
+CONFIG_ATH11K_DEBUGFS=y
+CONFIG_ATH11K_TRACING=y
+CONFIG_ATH11K_SPECTRAL=y
+CONFIG_ATH12K=m
+CONFIG_ATH12K_TRACING=y
+CONFIG_ATMEL=m
+CONFIG_PCI_ATMEL=m
+CONFIG_AT76C50X_USB=m
+CONFIG_B43=m
+CONFIG_B43LEGACY=m
+# CONFIG_B43LEGACY_DEBUG is not set
+CONFIG_BRCMSMAC=m
+CONFIG_BRCMFMAC=m
+CONFIG_BRCMFMAC_USB=y
+CONFIG_BRCMFMAC_PCIE=y
+CONFIG_BRCM_TRACING=y
+CONFIG_AIRO=m
+CONFIG_IPW2100=m
+CONFIG_IPW2100_MONITOR=y
+CONFIG_IPW2200=m
+CONFIG_IPW2200_MONITOR=y
+CONFIG_IPW2200_PROMISCUOUS=y
+CONFIG_IPW2200_QOS=y
+CONFIG_IWL4965=m
+CONFIG_IWL3945=m
+CONFIG_IWLEGACY_DEBUGFS=y
+CONFIG_IWLWIFI=m
+CONFIG_IWLDVM=m
+CONFIG_IWLMVM=m
+CONFIG_IWLWIFI_DEBUGFS=y
+CONFIG_HOSTAP=m
+CONFIG_HOSTAP_FIRMWARE=y
+CONFIG_HOSTAP_FIRMWARE_NVRAM=y
+CONFIG_HOSTAP_PLX=m
+CONFIG_HOSTAP_PCI=m
+CONFIG_HERMES=m
+CONFIG_PLX_HERMES=m
+CONFIG_TMD_HERMES=m
+CONFIG_NORTEL_HERMES=m
+CONFIG_ORINOCO_USB=m
+CONFIG_P54_COMMON=m
+CONFIG_P54_USB=m
+CONFIG_P54_PCI=m
+CONFIG_P54_SPI=m
+CONFIG_LIBERTAS=m
+CONFIG_LIBERTAS_USB=m
+CONFIG_LIBERTAS_SDIO=m
+CONFIG_LIBERTAS_SPI=m
+CONFIG_LIBERTAS_MESH=y
+CONFIG_LIBERTAS_THINFIRM=m
+CONFIG_LIBERTAS_THINFIRM_USB=m
+CONFIG_MWIFIEX=m
+CONFIG_MWIFIEX_SDIO=m
+CONFIG_MWIFIEX_PCIE=m
+CONFIG_MWIFIEX_USB=m
+CONFIG_MWL8K=m
+CONFIG_MT7601U=m
+CONFIG_MT76x0U=m
+CONFIG_MT76x0E=m
+CONFIG_MT76x2E=m
+CONFIG_MT76x2U=m
+CONFIG_MT7603E=m
+CONFIG_MT7615E=m
+CONFIG_MT7663U=m
+CONFIG_MT7663S=m
+CONFIG_MT7915E=m
+CONFIG_MT7921E=m
+CONFIG_MT7921S=m
+CONFIG_MT7921U=m
+CONFIG_MT7996E=m
+CONFIG_WILC1000_SDIO=m
+CONFIG_WILC1000_SPI=m
+CONFIG_WILC1000_HW_OOB_INTR=y
+CONFIG_PLFXLC=m
+CONFIG_RT2X00=m
+CONFIG_RT2400PCI=m
+CONFIG_RT2500PCI=m
+CONFIG_RT61PCI=m
+CONFIG_RT2800PCI=m
+CONFIG_RT2500USB=m
+CONFIG_RT73USB=m
+CONFIG_RT2800USB=m
+CONFIG_RT2800USB_RT3573=y
+CONFIG_RT2800USB_RT53XX=y
+CONFIG_RT2800USB_RT55XX=y
+CONFIG_RT2800USB_UNKNOWN=y
+CONFIG_RTL8180=m
+CONFIG_RTL8187=m
+CONFIG_RTL8192CE=m
+CONFIG_RTL8192SE=m
+CONFIG_RTL8192DE=m
+CONFIG_RTL8723AE=m
+CONFIG_RTL8723BE=m
+CONFIG_RTL8188EE=m
+CONFIG_RTL8192EE=m
+CONFIG_RTL8821AE=m
+CONFIG_RTL8192CU=m
+# CONFIG_RTLWIFI_DEBUG is not set
+CONFIG_RTL8XXXU=m
+CONFIG_RTL8XXXU_UNTESTED=y
+CONFIG_RTW88=m
+CONFIG_RTW88_8822BE=m
+CONFIG_RTW88_8822BS=m
+CONFIG_RTW88_8822BU=m
+CONFIG_RTW88_8822CE=m
+CONFIG_RTW88_8822CS=m
+CONFIG_RTW88_8822CU=m
+CONFIG_RTW88_8723DE=m
+CONFIG_RTW88_8723DS=m
+CONFIG_RTW88_8723DU=m
+CONFIG_RTW88_8821CE=m
+CONFIG_RTW88_8821CS=m
+CONFIG_RTW88_8821CU=m
+CONFIG_RTW88_DEBUG=y
+CONFIG_RTW88_DEBUGFS=y
+CONFIG_RTW89=m
+CONFIG_RTW89_8851BE=m
+CONFIG_RTW89_8852AE=m
+CONFIG_RTW89_8852BE=m
+CONFIG_RTW89_8852CE=m
+CONFIG_RTW89_DEBUGMSG=y
+CONFIG_RTW89_DEBUGFS=y
+CONFIG_RSI_91X=m
+# CONFIG_RSI_DEBUGFS is not set
+CONFIG_WFX=m
+CONFIG_CW1200=m
+CONFIG_CW1200_WLAN_SDIO=m
+CONFIG_CW1200_WLAN_SPI=m
+CONFIG_WL1251=m
+CONFIG_WL1251_SPI=m
+CONFIG_WL1251_SDIO=m
+CONFIG_WL12XX=m
+CONFIG_WL18XX=m
+CONFIG_WLCORE_SPI=m
+CONFIG_WLCORE_SDIO=m
+CONFIG_USB_ZD1201=m
+CONFIG_ZD1211RW=m
+CONFIG_QTNFMAC_PCIE=m
+CONFIG_USB_NET_RNDIS_WLAN=m
+CONFIG_MAC80211_HWSIM=m
+CONFIG_VIRT_WIFI=m
+CONFIG_WAN=y
+CONFIG_HDLC=m
+CONFIG_HDLC_RAW=m
+CONFIG_HDLC_RAW_ETH=m
+CONFIG_HDLC_CISCO=m
+CONFIG_HDLC_FR=m
+CONFIG_HDLC_PPP=m
+CONFIG_HDLC_X25=m
+CONFIG_PCI200SYN=m
+CONFIG_WANXL=m
+CONFIG_PC300TOO=m
+CONFIG_FARSYNC=m
+CONFIG_LAPBETHER=m
+CONFIG_IEEE802154_FAKELB=m
+CONFIG_IEEE802154_AT86RF230=m
+CONFIG_IEEE802154_MRF24J40=m
+CONFIG_IEEE802154_CC2520=m
+CONFIG_IEEE802154_ATUSB=m
+CONFIG_IEEE802154_ADF7242=m
+CONFIG_IEEE802154_CA8210=m
+CONFIG_IEEE802154_CA8210_DEBUGFS=y
+CONFIG_IEEE802154_MCR20A=m
+CONFIG_IEEE802154_HWSIM=m
+CONFIG_WWAN=m
+CONFIG_WWAN_HWSIM=m
+CONFIG_MHI_WWAN_CTRL=m
+CONFIG_MHI_WWAN_MBIM=m
+CONFIG_RPMSG_WWAN_CTRL=m
+CONFIG_IOSM=m
+CONFIG_MTK_T7XX=m
+CONFIG_VMXNET3=m
+CONFIG_NETDEVSIM=m
+CONFIG_ISDN=y
+CONFIG_MISDN=m
+CONFIG_MISDN_DSP=m
+CONFIG_MISDN_L1OIP=m
+CONFIG_MISDN_HFCPCI=m
+CONFIG_MISDN_HFCMULTI=m
+CONFIG_MISDN_HFCUSB=m
+CONFIG_MISDN_AVMFRITZ=m
+CONFIG_MISDN_SPEEDFAX=m
+CONFIG_MISDN_INFINEON=m
+CONFIG_MISDN_W6692=m
+CONFIG_MISDN_NETJET=m
+CONFIG_INPUT_LEDS=m
+CONFIG_INPUT_SPARSEKMAP=m
+CONFIG_INPUT_MATRIXKMAP=m
+CONFIG_INPUT_MOUSEDEV=y
+CONFIG_INPUT_MOUSEDEV_PSAUX=y
+CONFIG_INPUT_JOYDEV=m
+CONFIG_INPUT_EVDEV=y
+CONFIG_INPUT_EVBUG=m
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+CONFIG_SERIO_SERPORT=m
+CONFIG_SERIO_PARKBD=m
+CONFIG_SERIO_PCIPS2=m
+CONFIG_SERIO_LIBPS2=y
+CONFIG_SERIO_RAW=m
+CONFIG_SERIO_ALTERA_PS2=m
+CONFIG_SERIO_PS2MULT=m
+CONFIG_SERIO_ARC_PS2=m
+CONFIG_SERIO_APBPS2=m
+CONFIG_SERIO_GPIO_PS2=m
+CONFIG_USERIO=m
+CONFIG_LEGACY_PTY_COUNT=0
+# CONFIG_LEGACY_TIOCSTI is not set
+CONFIG_SERIAL_8250=y
+# CONFIG_SERIAL_8250_DEPRECATED_OPTIONS is not set
+CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_SERIAL_8250_DW=y
+# CONFIG_SERIAL_8250_PERICOM is not set
+CONFIG_SERIAL_OF_PLATFORM=y
+CONFIG_SERIAL_EARLYCON_SEMIHOST=y
+CONFIG_SERIAL_DEV_BUS=y
+CONFIG_TTY_PRINTK=y
+CONFIG_PRINTER=m
+CONFIG_PPDEV=m
+CONFIG_VIRTIO_CONSOLE=y
+CONFIG_IPMI_HANDLER=m
+CONFIG_IPMI_DEVICE_INTERFACE=m
+CONFIG_IPMI_SSIF=m
+CONFIG_IPMI_IPMB=m
+CONFIG_IPMI_WATCHDOG=m
+CONFIG_IPMI_POWEROFF=m
+CONFIG_SSIF_IPMI_BMC=m
+CONFIG_IPMB_DEVICE_INTERFACE=m
+CONFIG_HW_RANDOM=y
+CONFIG_HW_RANDOM_TIMERIOMEM=m
+CONFIG_HW_RANDOM_BA431=m
+CONFIG_HW_RANDOM_VIRTIO=m
+CONFIG_HW_RANDOM_CCTRNG=m
+CONFIG_HW_RANDOM_XIPHERA=m
+CONFIG_APPLICOM=m
+CONFIG_TCG_TIS=y
+CONFIG_TCG_TIS_SPI=m
+CONFIG_TCG_TIS_SPI_CR50=y
+CONFIG_TCG_TIS_I2C=m
+CONFIG_TCG_TIS_I2C_CR50=m
+CONFIG_TCG_TIS_I2C_ATMEL=m
+CONFIG_TCG_TIS_I2C_INFINEON=m
+CONFIG_TCG_TIS_I2C_NUVOTON=m
+CONFIG_TCG_ATMEL=m
+CONFIG_TCG_VTPM_PROXY=m
+CONFIG_TCG_TIS_ST33ZP24_I2C=m
+CONFIG_TCG_TIS_ST33ZP24_SPI=m
+CONFIG_XILLYBUS=m
+CONFIG_XILLYBUS_PCIE=m
+CONFIG_XILLYBUS_OF=m
+CONFIG_XILLYUSB=m
+CONFIG_I2C_CHARDEV=y
+CONFIG_I2C_DESIGNWARE_PLATFORM=y
+CONFIG_I2C_DESIGNWARE_PCI=m
+CONFIG_I2C_GPIO=m
+CONFIG_I2C_SLAVE=y
+CONFIG_I2C_SLAVE_EEPROM=m
+CONFIG_SPI=y
+CONFIG_SPI_DESIGNWARE=m
+CONFIG_SPI_DW_DMA=y
+CONFIG_SPI_DW_PCI=m
+CONFIG_SPI_DW_MMIO=m
+CONFIG_SPI_ESWIN_BOOTSPI=m
+CONFIG_SPI_SIFIVE=y
+CONFIG_SPMI=m
+CONFIG_SPMI_HISI3670=m
+CONFIG_HSI=m
+CONFIG_HSI_CHAR=m
+CONFIG_PPS_CLIENT_LDISC=m
+CONFIG_PPS_CLIENT_PARPORT=m
+CONFIG_PPS_CLIENT_GPIO=m
+CONFIG_DP83640_PHY=m
+CONFIG_PTP_1588_CLOCK_INES=m
+CONFIG_PTP_1588_CLOCK_IDT82P33=m
+CONFIG_PTP_1588_CLOCK_IDTCM=m
+CONFIG_PTP_1588_CLOCK_MOCK=m
+CONFIG_PTP_1588_CLOCK_OCP=m
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_EIC7700=y
+CONFIG_GPIO_SYSFS=y
+CONFIG_GPIO_DWAPB=m
+CONFIG_POWER_RESET_GPIO=y
+CONFIG_POWER_RESET_GPIO_RESTART=y
+CONFIG_POWER_RESET_LTC2952=y
+CONFIG_POWER_RESET_REGULATOR=y
+CONFIG_POWER_RESET_RESTART=y
+CONFIG_SYSCON_REBOOT_MODE=m
+CONFIG_NVMEM_REBOOT_MODE=m
+CONFIG_SENSORS_ESWIN_FAN_CONTROL=y
+CONFIG_SENSORS_ESWIN_PVT=y
+CONFIG_SENSORS_GPIO_FAN=m
+CONFIG_SENSORS_PAC1934=m
+CONFIG_PMBUS=m
+CONFIG_SENSORS_PWM_FAN=m
+CONFIG_SENSORS_INA2XX=m
+CONFIG_SENSORS_INA238=m
+CONFIG_SENSORS_INA3221=m
+CONFIG_THERMAL=y
+CONFIG_THERMAL_NETLINK=y
+CONFIG_THERMAL_STATISTICS=y
+CONFIG_THERMAL_WRITABLE_TRIPS=y
+CONFIG_THERMAL_GOV_FAIR_SHARE=y
+CONFIG_THERMAL_GOV_BANG_BANG=y
+CONFIG_THERMAL_GOV_USER_SPACE=y
+CONFIG_THERMAL_GOV_POWER_ALLOCATOR=y
+CONFIG_CPU_THERMAL=y
+CONFIG_CPU_IDLE_THERMAL=y
+CONFIG_DEVFREQ_THERMAL=y
+CONFIG_THERMAL_EMULATION=y
+CONFIG_THERMAL_MMIO=m
+CONFIG_WATCHDOG=y
+CONFIG_WATCHDOG_CORE=y
+CONFIG_WATCHDOG_SYSFS=y
+CONFIG_WATCHDOG_PRETIMEOUT_GOV=y
+CONFIG_WATCHDOG_PRETIMEOUT_GOV_PANIC=m
+CONFIG_WATCHDOG_PRETIMEOUT_DEFAULT_GOV_NOOP=y
+CONFIG_DW_WATCHDOG=m
+CONFIG_SSB_SDIOHOST=y
+CONFIG_SSB_DRIVER_GPIO=y
+CONFIG_BCMA_HOST_SOC=y
+CONFIG_BCMA_DRIVER_GMAC_CMN=y
+CONFIG_BCMA_DRIVER_GPIO=y
+CONFIG_REGULATOR=y
+CONFIG_REGULATOR_FIXED_VOLTAGE=y
+CONFIG_REGULATOR_USERSPACE_CONSUMER=m
+CONFIG_MEDIA_CEC_SUPPORT=y
+CONFIG_CEC_CH7322=m
+CONFIG_CEC_GPIO=m
+CONFIG_USB_PULSE8_CEC=m
+CONFIG_USB_RAINSHADOW_CEC=m
+CONFIG_MEDIA_SUPPORT=m
+CONFIG_MEDIA_SUPPORT_FILTER=y
+CONFIG_MEDIA_PLATFORM_SUPPORT=y
+CONFIG_MEDIA_TEST_SUPPORT=y
+CONFIG_V4L2_FLASH_LED_CLASS=m
+CONFIG_V4L_PLATFORM_DRIVERS=y
+CONFIG_V4L_MEM2MEM_DRIVERS=y
+CONFIG_VIDEO_MEM2MEM_DEINTERLACE=m
+CONFIG_VIDEO_MUX=m
+CONFIG_V4L_TEST_DRIVERS=y
+CONFIG_VIDEO_VIM2M=m
+CONFIG_VIDEO_VICODEC=m
+CONFIG_VIDEO_VIMC=m
+CONFIG_VIDEO_VIVID=m
+CONFIG_VIDEO_VIVID_CEC=y
+CONFIG_VIDEO_VISL=m
+CONFIG_VIDEO_I2C=m
+CONFIG_IMG_ASCII_LCD=m
+CONFIG_LCD2S=m
+CONFIG_PANEL=m
+CONFIG_DRM=y
+CONFIG_DRM_DEBUG_MM=y
+CONFIG_DRM_RADEON=m
+CONFIG_DRM_RADEON_USERPTR=y
+CONFIG_DRM_AMDGPU=m
+CONFIG_DRM_AST=y
+CONFIG_DRM_DISPLAY_CONNECTOR=y
+CONFIG_DRM_SIMPLE_BRIDGE=y
+CONFIG_DRM_ESWIN=y
+CONFIG_ESWIN_VIRTUAL_DISPLAY=y
+CONFIG_ESWIN_MMU=y
+CONFIG_ESWIN_DW_HDMI=y
+CONFIG_DW_HDMI_I2S_AUDIO=y
+CONFIG_DW_HDMI_CEC=y
+CONFIG_DRM_IMG_VOLCANIC=m
+CONFIG_DRM_LEGACY=y
+CONFIG_FB=y
+CONFIG_FB_UVESA=m
+CONFIG_FB_EFI=y
+CONFIG_FB_OPENCORES=m
+CONFIG_FB_NVIDIA=m
+CONFIG_FB_NVIDIA_I2C=y
+CONFIG_FB_RIVA=m
+CONFIG_FB_RIVA_I2C=y
+CONFIG_FB_I740=m
+CONFIG_FB_MATROX=m
+CONFIG_FB_MATROX_MILLENIUM=y
+CONFIG_FB_MATROX_MYSTIQUE=y
+CONFIG_FB_MATROX_G=y
+CONFIG_FB_MATROX_I2C=m
+CONFIG_FB_MATROX_MAVEN=m
+CONFIG_FB_RADEON=m
+CONFIG_FB_ATY128=m
+CONFIG_FB_ATY=m
+CONFIG_FB_ATY_CT=y
+CONFIG_FB_ATY_GX=y
+CONFIG_FB_S3=m
+CONFIG_FB_SAVAGE=m
+CONFIG_FB_SAVAGE_I2C=y
+CONFIG_FB_SIS=m
+CONFIG_FB_SIS_300=y
+CONFIG_FB_SIS_315=y
+CONFIG_FB_NEOMAGIC=m
+CONFIG_FB_KYRO=m
+CONFIG_FB_3DFX=m
+# CONFIG_FB_3DFX_I2C is not set
+CONFIG_FB_VOODOO1=m
+CONFIG_FB_VT8623=m
+CONFIG_FB_TRIDENT=m
+CONFIG_FB_ARK=m
+CONFIG_FB_PM3=m
+CONFIG_FB_CARMINE=m
+CONFIG_FB_SMSCUFX=m
+CONFIG_FB_UDL=m
+CONFIG_FB_GOLDFISH=m
+CONFIG_FB_METRONOME=m
+CONFIG_FB_MB862XX=m
+CONFIG_FB_SIMPLE=m
+CONFIG_FB_SSD1307=m
+CONFIG_FB_SM712=m
+CONFIG_FIRMWARE_EDID=y
+CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y
+CONFIG_FRAMEBUFFER_CONSOLE_DEFERRED_TAKEOVER=y
+CONFIG_DRM_ACCEL=y
+CONFIG_DRM_ACCEL_QAIC=m
+CONFIG_SOUND=m
+# CONFIG_SOUND_OSS_CORE_PRECLAIM is not set
+CONFIG_SND=m
+CONFIG_SND_OSSEMUL=y
+CONFIG_SND_MIXER_OSS=m
+CONFIG_SND_HRTIMER=m
+# CONFIG_SND_CTL_FAST_LOOKUP is not set
+CONFIG_SND_SEQUENCER=m
+CONFIG_SND_SEQ_DUMMY=m
+CONFIG_SND_DUMMY=m
+CONFIG_SND_ALOOP=m
+CONFIG_SND_PCMTEST=m
+CONFIG_SND_VIRMIDI=m
+CONFIG_SND_MTPAV=m
+CONFIG_SND_MTS64=m
+CONFIG_SND_HDA_INTEL=m
+CONFIG_SND_HDA_HWDEP=y
+CONFIG_SND_HDA_INPUT_BEEP=y
+CONFIG_SND_HDA_INPUT_BEEP_MODE=0
+CONFIG_SND_HDA_PATCH_LOADER=y
+CONFIG_SND_HDA_CODEC_REALTEK=m
+CONFIG_SND_HDA_CODEC_ANALOG=m
+CONFIG_SND_HDA_CODEC_SIGMATEL=m
+CONFIG_SND_HDA_CODEC_VIA=m
+CONFIG_SND_HDA_CODEC_HDMI=m
+CONFIG_SND_HDA_CODEC_CIRRUS=m
+CONFIG_SND_HDA_CODEC_CS8409=m
+CONFIG_SND_HDA_CODEC_CONEXANT=m
+CONFIG_SND_HDA_CODEC_CA0110=m
+CONFIG_SND_HDA_CODEC_CA0132=m
+CONFIG_SND_HDA_CODEC_CMEDIA=m
+CONFIG_SND_HDA_CODEC_SI3054=m
+CONFIG_SND_HDA_POWER_SAVE_DEFAULT=1
+CONFIG_SND_USB_AUDIO=m
+CONFIG_SND_USB_AUDIO_MIDI_V2=y
+CONFIG_SND_USB_UA101=m
+CONFIG_SND_USB_CAIAQ=m
+CONFIG_SND_USB_CAIAQ_INPUT=y
+CONFIG_SND_USB_6FIRE=m
+CONFIG_SND_USB_HIFACE=m
+CONFIG_SND_BCD2000=m
+CONFIG_SND_USB_POD=m
+CONFIG_SND_USB_PODHD=m
+CONFIG_SND_USB_TONEPORT=m
+CONFIG_SND_USB_VARIAX=m
+CONFIG_SND_SOC=m
+CONFIG_SND_SOC_AMD_ACP=m
+CONFIG_SND_SOC_AMD_CZ_RT5645_MACH=m
+CONFIG_SND_AMD_ACP_CONFIG=m
+CONFIG_SND_DESIGNWARE_I2S=m
+CONFIG_SND_DESIGNWARE_PCM=y
+CONFIG_SND_ESWIN_DW_I2S=m
+CONFIG_SND_SOC_IMG=y
+CONFIG_SND_SOC_IMG_I2S_IN=m
+CONFIG_SND_SOC_IMG_I2S_OUT=m
+CONFIG_SND_SOC_IMG_PARALLEL_OUT=m
+CONFIG_SND_SOC_IMG_SPDIF_IN=m
+CONFIG_SND_SOC_IMG_SPDIF_OUT=m
+CONFIG_SND_SOC_IMG_PISTACHIO_INTERNAL_DAC=m
+CONFIG_SND_SOC_MTK_BTCVSD=m
+CONFIG_SND_SOC_SOF_TOPLEVEL=y
+CONFIG_SND_SOC_SOF_PCI=m
+CONFIG_SND_SOC_SOF_OF=m
+CONFIG_SND_SOC_BT_SCO=m
+CONFIG_SND_SOC_DMIC=m
+CONFIG_SND_SOC_HDA=m
+CONFIG_SND_SOC_ICS43432=m
+CONFIG_SND_SOC_SIMPLE_AMPLIFIER=m
+CONFIG_SND_SOC_SIMPLE_MUX=m
+CONFIG_SND_SOC_SPDIF=m
+CONFIG_ESWIN_SND_SOC_CODECS=m
+CONFIG_ESWIN_SND_ES8388_CODEC=m
+CONFIG_SND_SIMPLE_CARD=m
+CONFIG_SND_AUDIO_GRAPH_CARD=m
+CONFIG_SND_AUDIO_GRAPH_CARD2=m
+CONFIG_SND_AUDIO_GRAPH_CARD2_CUSTOM_SAMPLE=m
+CONFIG_SND_TEST_COMPONENT=m
+CONFIG_SND_VIRTIO=m
+CONFIG_HID=m
+CONFIG_HID_BATTERY_STRENGTH=y
+CONFIG_HIDRAW=y
+CONFIG_UHID=m
+CONFIG_HID_LOGITECH=m
+CONFIG_HID_LOGITECH_DJ=m
+CONFIG_LOGITECH_FF=y
+CONFIG_LOGIRUMBLEPAD2_FF=y
+CONFIG_LOGIG940_FF=y
+CONFIG_HID_SAMSUNG=m
+CONFIG_HID_SEMITEK=m
+CONFIG_HID_SIGMAMICRO=m
+CONFIG_HID_SPEEDLINK=m
+CONFIG_USB_HID=m
+CONFIG_HID_PID=y
+CONFIG_USB_HIDDEV=y
+CONFIG_USB_KBD=m
+CONFIG_USB_MOUSE=m
+CONFIG_I2C_HID_OF=m
+CONFIG_I2C_HID_OF_ELAN=m
+CONFIG_I2C_HID_OF_GOODIX=m
+CONFIG_USB_LED_TRIG=y
+CONFIG_USB_CONN_GPIO=m
+CONFIG_USB=y
+CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
+CONFIG_USB_DYNAMIC_MINORS=y
+CONFIG_USB_OTG=y
+CONFIG_USB_OTG_FSM=m
+CONFIG_USB_LEDS_TRIGGER_USBPORT=m
+CONFIG_USB_MON=m
+CONFIG_USB_C67X00_HCD=m
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DBGCAP=y
+CONFIG_USB_XHCI_PCI_RENESAS=m
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_FSL=m
+CONFIG_USB_OXU210HP_HCD=m
+CONFIG_USB_ISP116X_HCD=m
+CONFIG_USB_MAX3421_HCD=m
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_UHCI_HCD=y
+CONFIG_USB_SL811_HCD=m
+CONFIG_USB_SL811_HCD_ISO=y
+CONFIG_USB_R8A66597_HCD=m
+CONFIG_USB_HCD_BCMA=m
+CONFIG_USB_HCD_SSB=m
+CONFIG_USB_PRINTER=m
+CONFIG_USB_TMC=m
+CONFIG_USB_STORAGE=y
+CONFIG_USB_STORAGE_REALTEK=y
+CONFIG_USB_STORAGE_DATAFAB=y
+CONFIG_USB_STORAGE_FREECOM=y
+CONFIG_USB_STORAGE_ISD200=y
+CONFIG_USB_STORAGE_USBAT=y
+CONFIG_USB_STORAGE_SDDR09=y
+CONFIG_USB_STORAGE_SDDR55=y
+CONFIG_USB_STORAGE_JUMPSHOT=y
+CONFIG_USB_STORAGE_ALAUDA=y
+CONFIG_USB_STORAGE_ONETOUCH=y
+CONFIG_USB_STORAGE_KARMA=y
+CONFIG_USB_STORAGE_CYPRESS_ATACB=y
+CONFIG_USB_STORAGE_ENE_UB6250=y
+CONFIG_USB_UAS=y
+CONFIG_USB_MDC800=m
+CONFIG_USB_MICROTEK=m
+CONFIG_USBIP_CORE=m
+CONFIG_USBIP_VHCI_HCD=m
+CONFIG_USBIP_HOST=m
+CONFIG_USBIP_VUDC=m
+CONFIG_USB_CDNS_SUPPORT=m
+CONFIG_USB_CDNS3=m
+CONFIG_USB_CDNS3_GADGET=y
+CONFIG_USB_CDNS3_HOST=y
+CONFIG_USB_MUSB_HDRC=m
+CONFIG_MUSB_PIO_ONLY=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_HAPS=m
+# CONFIG_USB_DWC3_OF_SIMPLE is not set
+CONFIG_USB_DWC2=y
+CONFIG_USB_DWC2_PCI=m
+CONFIG_USB_CHIPIDEA=m
+CONFIG_USB_CHIPIDEA_UDC=y
+CONFIG_USB_CHIPIDEA_HOST=y
+CONFIG_USB_ISP1760=m
+CONFIG_USB_SERIAL=m
+CONFIG_USB_SERIAL_GENERIC=y
+CONFIG_USB_SERIAL_SIMPLE=m
+CONFIG_USB_SERIAL_CP210X=m
+CONFIG_USB_SERIAL_FTDI_SIO=m
+CONFIG_USB_SERIAL_PL2303=m
+CONFIG_USB_SERIAL_OTI6858=m
+CONFIG_USB_SERIAL_QUALCOMM=m
+CONFIG_USB_SERIAL_OPTION=m
+CONFIG_USB_SERIAL_DEBUG=m
+CONFIG_USB_USS720=m
+CONFIG_USB_EMI62=m
+CONFIG_USB_EMI26=m
+CONFIG_USB_ADUTUX=m
+CONFIG_USB_SEVSEG=m
+CONFIG_USB_LEGOTOWER=m
+CONFIG_USB_LCD=m
+CONFIG_USB_CYPRESS_CY7C63=m
+CONFIG_USB_CYTHERM=m
+CONFIG_USB_IDMOUSE=m
+CONFIG_USB_APPLEDISPLAY=m
+CONFIG_APPLE_MFI_FASTCHARGE=m
+CONFIG_USB_SISUSBVGA=m
+CONFIG_USB_LD=m
+CONFIG_USB_TRANCEVIBRATOR=m
+CONFIG_USB_IOWARRIOR=m
+CONFIG_USB_TEST=m
+CONFIG_USB_EHSET_TEST_FIXTURE=m
+CONFIG_USB_ISIGHTFW=m
+CONFIG_USB_YUREX=m
+CONFIG_USB_HUB_USB251XB=m
+CONFIG_USB_HSIC_USB3503=m
+CONFIG_USB_HSIC_USB4604=m
+CONFIG_USB_LINK_LAYER_TEST=m
+CONFIG_USB_CHAOSKEY=m
+CONFIG_USB_ATM=m
+CONFIG_USB_SPEEDTOUCH=m
+CONFIG_USB_CXACRU=m
+CONFIG_USB_UEAGLEATM=m
+CONFIG_USB_XUSBATM=m
+CONFIG_USB_GPIO_VBUS=m
+CONFIG_USB_ISP1301=m
+CONFIG_USB_GADGET=m
+CONFIG_U_SERIAL_CONSOLE=y
+CONFIG_USB_GR_UDC=m
+CONFIG_USB_R8A66597=m
+CONFIG_USB_PXA27X=m
+CONFIG_USB_MV_UDC=m
+CONFIG_USB_MV_U3D=m
+CONFIG_USB_SNP_UDC_PLAT=m
+CONFIG_USB_BDC_UDC=m
+CONFIG_USB_AMD5536UDC=m
+CONFIG_USB_NET2272=m
+CONFIG_USB_NET2272_DMA=y
+CONFIG_USB_NET2280=m
+CONFIG_USB_GOKU=m
+CONFIG_USB_EG20T=m
+CONFIG_USB_GADGET_XILINX=m
+CONFIG_USB_MAX3420_UDC=m
+CONFIG_USB_CONFIGFS=m
+CONFIG_USB_CONFIGFS_SERIAL=y
+CONFIG_USB_CONFIGFS_ACM=y
+CONFIG_USB_CONFIGFS_OBEX=y
+CONFIG_USB_CONFIGFS_NCM=y
+CONFIG_USB_CONFIGFS_ECM=y
+CONFIG_USB_CONFIGFS_ECM_SUBSET=y
+CONFIG_USB_CONFIGFS_RNDIS=y
+CONFIG_USB_CONFIGFS_EEM=y
+CONFIG_USB_CONFIGFS_PHONET=y
+CONFIG_USB_CONFIGFS_MASS_STORAGE=y
+CONFIG_USB_CONFIGFS_F_LB_SS=y
+CONFIG_USB_CONFIGFS_F_FS=y
+CONFIG_USB_CONFIGFS_F_UAC1=y
+CONFIG_USB_CONFIGFS_F_UAC1_LEGACY=y
+CONFIG_USB_CONFIGFS_F_UAC2=y
+CONFIG_USB_CONFIGFS_F_MIDI=y
+CONFIG_USB_CONFIGFS_F_MIDI2=y
+CONFIG_USB_CONFIGFS_F_HID=y
+CONFIG_USB_CONFIGFS_F_UVC=y
+CONFIG_USB_CONFIGFS_F_PRINTER=y
+CONFIG_USB_CONFIGFS_F_TCM=y
+CONFIG_USB_ZERO=m
+CONFIG_USB_AUDIO=m
+CONFIG_GADGET_UAC1=y
+CONFIG_USB_ETH=m
+CONFIG_USB_ETH_EEM=y
+CONFIG_USB_G_NCM=m
+CONFIG_USB_GADGETFS=m
+CONFIG_USB_FUNCTIONFS=m
+CONFIG_USB_FUNCTIONFS_ETH=y
+CONFIG_USB_FUNCTIONFS_RNDIS=y
+CONFIG_USB_FUNCTIONFS_GENERIC=y
+CONFIG_USB_MASS_STORAGE=m
+CONFIG_USB_GADGET_TARGET=m
+CONFIG_USB_G_SERIAL=m
+CONFIG_USB_MIDI_GADGET=m
+CONFIG_USB_G_PRINTER=m
+CONFIG_USB_CDC_COMPOSITE=m
+CONFIG_USB_G_NOKIA=m
+CONFIG_USB_G_ACM_MS=m
+CONFIG_USB_G_HID=m
+CONFIG_USB_G_DBGP=m
+CONFIG_USB_G_WEBCAM=m
+CONFIG_USB_RAW_GADGET=m
+CONFIG_TYPEC=m
+CONFIG_TYPEC_TCPM=m
+CONFIG_TYPEC_TCPCI=m
+CONFIG_TYPEC_FUSB302=m
+CONFIG_TYPEC_FUSB303B=m
+CONFIG_MMC=y
+CONFIG_PWRSEQ_EMMC=m
+CONFIG_PWRSEQ_SD8787=m
+CONFIG_PWRSEQ_SIMPLE=m
+CONFIG_SDIO_UART=m
+CONFIG_MMC_CRYPTO=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_PCI=m
+CONFIG_MMC_SDHCI_PLTFM=y
+CONFIG_MMC_SDHCI_OF_ESWIN=y
+CONFIG_MMC_SDHCI_OF_SDIO_ESWIN=y
+CONFIG_MMC_SDHCI_OF_DWCMSHC=m
+CONFIG_MMC_DW=m
+CONFIG_MMC_DW_PCI=m
+CONFIG_MMC_USHC=m
+CONFIG_MMC_HSQ=m
+CONFIG_MEMSTICK=m
+CONFIG_MSPRO_BLOCK=m
+CONFIG_MS_BLOCK=m
+CONFIG_MEMSTICK_TIFM_MS=m
+CONFIG_MEMSTICK_JMICRON_38X=m
+CONFIG_MEMSTICK_R592=m
+CONFIG_MEMSTICK_REALTEK_PCI=m
+CONFIG_MEMSTICK_REALTEK_USB=m
+CONFIG_LEDS_CLASS=y
+CONFIG_LEDS_CLASS_FLASH=m
+CONFIG_LEDS_CLASS_MULTICOLOR=m
+CONFIG_LEDS_BRIGHTNESS_HW_CHANGED=y
+CONFIG_LEDS_GPIO=m
+CONFIG_LEDS_PWM=m
+CONFIG_LEDS_REGULATOR=m
+CONFIG_LEDS_PWM_MULTICOLOR=m
+CONFIG_LEDS_TRIGGER_TIMER=m
+CONFIG_LEDS_TRIGGER_ONESHOT=m
+CONFIG_LEDS_TRIGGER_DISK=y
+CONFIG_LEDS_TRIGGER_MTD=y
+CONFIG_LEDS_TRIGGER_HEARTBEAT=m
+CONFIG_LEDS_TRIGGER_BACKLIGHT=m
+CONFIG_LEDS_TRIGGER_CPU=y
+CONFIG_LEDS_TRIGGER_ACTIVITY=m
+CONFIG_LEDS_TRIGGER_DEFAULT_ON=m
+CONFIG_LEDS_TRIGGER_TRANSIENT=m
+CONFIG_LEDS_TRIGGER_CAMERA=m
+CONFIG_LEDS_TRIGGER_PANIC=y
+CONFIG_LEDS_TRIGGER_NETDEV=m
+CONFIG_LEDS_TRIGGER_PATTERN=m
+CONFIG_LEDS_TRIGGER_TTY=m
+CONFIG_EDAC=y
+# CONFIG_EDAC_LEGACY_SYSFS is not set
+CONFIG_EDAC_SIFIVE=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_DRV_ESWIN=y
+CONFIG_DMADEVICES=y
+CONFIG_DW_AXI_DMAC=m
+CONFIG_SW_SYNC=y
+CONFIG_UDMABUF=y
+CONFIG_DMABUF_MOVE_NOTIFY=y
+CONFIG_DMABUF_HEAPS=y
+CONFIG_DMABUF_HEAPS_SYSTEM=y
+CONFIG_DMABUF_HEAPS_CMA=y
+CONFIG_UIO=m
+CONFIG_UIO_CIF=m
+CONFIG_UIO_PDRV_GENIRQ=m
+CONFIG_UIO_DMEM_GENIRQ=m
+CONFIG_UIO_AEC=m
+CONFIG_UIO_SERCOS3=m
+CONFIG_UIO_PCI_GENERIC=m
+CONFIG_UIO_NETX=m
+CONFIG_UIO_PRUSS=m
+CONFIG_UIO_MF624=m
+CONFIG_VIRT_DRIVERS=y
+CONFIG_VIRTIO_PCI=y
+CONFIG_VIRTIO_VDPA=m
+CONFIG_VIRTIO_PMEM=m
+CONFIG_VIRTIO_BALLOON=y
+CONFIG_VIRTIO_INPUT=m
+CONFIG_VIRTIO_MMIO=y
+CONFIG_VIRTIO_MMIO_CMDLINE_DEVICES=y
+CONFIG_VDPA=m
+CONFIG_VDPA_SIM=m
+CONFIG_VDPA_SIM_NET=m
+CONFIG_VDPA_SIM_BLOCK=m
+CONFIG_VDPA_USER=m
+CONFIG_IFCVF=m
+CONFIG_MLX5_VDPA_STEERING_DEBUG=y
+CONFIG_VP_VDPA=m
+CONFIG_SNET_VDPA=m
+CONFIG_PDS_VDPA=m
+CONFIG_VHOST_NET=m
+CONFIG_VHOST_SCSI=m
+CONFIG_VHOST_VSOCK=m
+CONFIG_VHOST_VDPA=m
+CONFIG_STAGING=y
+CONFIG_PRISM2_USB=m
+CONFIG_RTL8192U=m
+CONFIG_RTLLIB=m
+CONFIG_RTL8192E=m
+CONFIG_RTL8723BS=m
+CONFIG_R8712U=m
+CONFIG_RTS5208=m
+CONFIG_VT6655=m
+CONFIG_VT6656=m
+CONFIG_FB_SM750=m
+CONFIG_STAGING_MEDIA=y
+CONFIG_VIDEO_MAX96712=m
+CONFIG_LTE_GDM724X=m
+CONFIG_KS7010=m
+CONFIG_QLGE=m
+CONFIG_GOLDFISH_PIPE=m
+CONFIG_LMK04832=m
+CONFIG_COMMON_CLK_MAX9485=m
+CONFIG_COMMON_CLK_SI5341=m
+CONFIG_COMMON_CLK_SI5351=m
+CONFIG_COMMON_CLK_SI514=m
+CONFIG_COMMON_CLK_SI544=m
+CONFIG_COMMON_CLK_SI570=m
+CONFIG_COMMON_CLK_CDCE706=m
+CONFIG_COMMON_CLK_CDCE925=m
+CONFIG_COMMON_CLK_CS2000_CP=m
+CONFIG_COMMON_CLK_AXI_CLKGEN=m
+CONFIG_COMMON_CLK_PWM=m
+CONFIG_COMMON_CLK_RS9_PCIE=m
+CONFIG_COMMON_CLK_SI521XX=m
+CONFIG_COMMON_CLK_VC3=m
+CONFIG_COMMON_CLK_VC5=m
+CONFIG_COMMON_CLK_VC7=m
+CONFIG_COMMON_CLK_FIXED_MMIO=y
+CONFIG_COMMON_CLK_EIC7700=y
+CONFIG_XILINX_VCU=m
+CONFIG_HWSPINLOCK=y
+CONFIG_MAILBOX=y
+CONFIG_PLATFORM_MHU=m
+CONFIG_MAILBOX_TEST=m
+CONFIG_IOMMUFD=m
+CONFIG_RPMSG_CHAR=m
+CONFIG_RPMSG_CTRL=m
+CONFIG_RPMSG_VIRTIO=m
+CONFIG_SOUNDWIRE=m
+CONFIG_SOUNDWIRE_QCOM=m
+CONFIG_LITEX_SOC_CONTROLLER=m
+CONFIG_WPCM450_SOC=m
+CONFIG_QCOM_PMIC_GLINK=m
+CONFIG_SIFIVE_CCACHE=y
+CONFIG_SOC_TI=y
+CONFIG_PM_DEVFREQ=y
+CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND=y
+CONFIG_DEVFREQ_GOV_PERFORMANCE=y
+CONFIG_DEVFREQ_GOV_POWERSAVE=y
+CONFIG_DEVFREQ_GOV_USERSPACE=y
+CONFIG_DEVFREQ_GOV_PASSIVE=y
+CONFIG_PM_DEVFREQ_EVENT=y
+CONFIG_EXTCON_ADC_JACK=m
+CONFIG_EXTCON_FSA9480=m
+CONFIG_EXTCON_GPIO=m
+CONFIG_EXTCON_MAX3355=m
+CONFIG_EXTCON_PTN5150=m
+CONFIG_EXTCON_RT8973A=m
+CONFIG_EXTCON_SM5502=m
+CONFIG_EXTCON_USB_GPIO=m
+CONFIG_EXTCON_USBC_TUSB320=m
+CONFIG_MEMORY=y
+CONFIG_IIO=y
+CONFIG_PWM=y
+CONFIG_PWM_CLK=m
+CONFIG_PWM_ESWIN=y
+CONFIG_RESET_ESWIN_EIC7700=y
+CONFIG_POWERCAP=y
+CONFIG_IDLE_INJECT=y
+CONFIG_DTPM=y
+CONFIG_DTPM_CPU=y
+CONFIG_LIBNVDIMM=y
+CONFIG_BLK_DEV_PMEM=m
+CONFIG_OF_PMEM=m
+CONFIG_DAX=y
+CONFIG_DEV_DAX=m
+CONFIG_NVMEM_LAYOUT_SL28_VPD=m
+CONFIG_NVMEM_LAYOUT_ONIE_TLV=m
+CONFIG_NVMEM_RMEM=m
+CONFIG_NVMEM_SPMI_SDAM=m
+CONFIG_NVMEM_U_BOOT_ENV=m
+# CONFIG_SLIMBUS is not set
+CONFIG_INTERCONNECT=y
+CONFIG_VALIDATE_FS_PARSER=y
+CONFIG_EXT4_FS=y
+CONFIG_EXT4_FS_POSIX_ACL=y
+CONFIG_EXT4_FS_SECURITY=y
+CONFIG_REISERFS_FS=m
+CONFIG_REISERFS_FS_XATTR=y
+CONFIG_REISERFS_FS_POSIX_ACL=y
+CONFIG_REISERFS_FS_SECURITY=y
+CONFIG_JFS_FS=m
+CONFIG_JFS_POSIX_ACL=y
+CONFIG_JFS_SECURITY=y
+CONFIG_JFS_STATISTICS=y
+CONFIG_XFS_FS=m
+CONFIG_XFS_QUOTA=y
+CONFIG_XFS_POSIX_ACL=y
+CONFIG_XFS_RT=y
+CONFIG_GFS2_FS=m
+CONFIG_GFS2_FS_LOCKING_DLM=y
+CONFIG_OCFS2_FS=m
+CONFIG_BTRFS_FS=m
+CONFIG_BTRFS_FS_POSIX_ACL=y
+CONFIG_NILFS2_FS=m
+CONFIG_F2FS_FS=m
+CONFIG_F2FS_FS_SECURITY=y
+CONFIG_F2FS_FS_COMPRESSION=y
+# CONFIG_F2FS_IOSTAT is not set
+CONFIG_F2FS_UNFAIR_RWSEM=y
+CONFIG_ZONEFS_FS=m
+CONFIG_FS_ENCRYPTION=y
+CONFIG_FS_ENCRYPTION_INLINE_CRYPT=y
+CONFIG_FS_VERITY=y
+CONFIG_FS_VERITY_BUILTIN_SIGNATURES=y
+CONFIG_FANOTIFY=y
+CONFIG_FANOTIFY_ACCESS_PERMISSIONS=y
+CONFIG_QUOTA_NETLINK_INTERFACE=y
+CONFIG_QFMT_V1=m
+CONFIG_QFMT_V2=m
+CONFIG_AUTOFS_FS=y
+CONFIG_FUSE_FS=y
+CONFIG_CUSE=m
+CONFIG_VIRTIO_FS=m
+CONFIG_OVERLAY_FS=m
+CONFIG_OVERLAY_FS_XINO_AUTO=y
+CONFIG_FSCACHE=y
+CONFIG_FSCACHE_STATS=y
+CONFIG_CACHEFILES=m
+CONFIG_CACHEFILES_ERROR_INJECTION=y
+CONFIG_ISO9660_FS=m
+CONFIG_JOLIET=y
+CONFIG_ZISOFS=y
+CONFIG_UDF_FS=m
+CONFIG_MSDOS_FS=m
+CONFIG_VFAT_FS=y
+CONFIG_EXFAT_FS=m
+CONFIG_NTFS_FS=m
+CONFIG_NTFS3_FS=m
+CONFIG_NTFS3_LZX_XPRESS=y
+CONFIG_NTFS3_FS_POSIX_ACL=y
+CONFIG_PROC_KCORE=y
+CONFIG_PROC_VMCORE_DEVICE_DUMP=y
+CONFIG_TMPFS=y
+CONFIG_TMPFS_POSIX_ACL=y
+CONFIG_TMPFS_INODE64=y
+CONFIG_TMPFS_QUOTA=y
+CONFIG_HUGETLBFS=y
+CONFIG_HUGETLB_PAGE_OPTIMIZE_VMEMMAP_DEFAULT_ON=y
+CONFIG_EFIVAR_FS=y
+CONFIG_ORANGEFS_FS=m
+CONFIG_ADFS_FS=m
+CONFIG_AFFS_FS=m
+CONFIG_ECRYPT_FS=y
+CONFIG_ECRYPT_FS_MESSAGING=y
+CONFIG_HFS_FS=m
+CONFIG_HFSPLUS_FS=m
+CONFIG_BEFS_FS=m
+CONFIG_BFS_FS=m
+CONFIG_EFS_FS=m
+CONFIG_JFFS2_FS=m
+CONFIG_JFFS2_FS_XATTR=y
+CONFIG_JFFS2_COMPRESSION_OPTIONS=y
+CONFIG_JFFS2_LZO=y
+CONFIG_JFFS2_CMODE_FAVOURLZO=y
+CONFIG_UBIFS_FS=m
+CONFIG_UBIFS_FS_AUTHENTICATION=y
+CONFIG_CRAMFS=m
+CONFIG_CRAMFS_MTD=y
+CONFIG_SQUASHFS=y
+CONFIG_SQUASHFS_FILE_DIRECT=y
+CONFIG_SQUASHFS_CHOICE_DECOMP_BY_MOUNT=y
+CONFIG_SQUASHFS_XATTR=y
+CONFIG_SQUASHFS_LZ4=y
+CONFIG_SQUASHFS_LZO=y
+CONFIG_SQUASHFS_XZ=y
+CONFIG_SQUASHFS_ZSTD=y
+CONFIG_VXFS_FS=m
+CONFIG_MINIX_FS=m
+CONFIG_OMFS_FS=m
+CONFIG_HPFS_FS=m
+CONFIG_QNX4FS_FS=m
+CONFIG_QNX6FS_FS=m
+CONFIG_ROMFS_FS=m
+CONFIG_PSTORE=y
+CONFIG_PSTORE_RAM=m
+CONFIG_PSTORE_BLK=m
+CONFIG_SYSV_FS=m
+CONFIG_UFS_FS=m
+CONFIG_EROFS_FS=m
+CONFIG_EROFS_FS_ZIP_DEFLATE=y
+CONFIG_EROFS_FS_PCPU_KTHREAD=y
+# CONFIG_EROFS_FS_PCPU_KTHREAD_HIPRI is not set
+CONFIG_NFS_FS=m
+CONFIG_NFS_V3_ACL=y
+CONFIG_NFS_V4=m
+CONFIG_NFS_SWAP=y
+CONFIG_NFS_V4_1=y
+CONFIG_NFS_V4_2=y
+CONFIG_NFS_V4_1_MIGRATION=y
+CONFIG_NFS_FSCACHE=y
+# CONFIG_NFS_V4_2_READ_PLUS is not set
+CONFIG_NFSD=m
+CONFIG_NFSD_V3_ACL=y
+CONFIG_NFSD_V4=y
+CONFIG_NFSD_BLOCKLAYOUT=y
+CONFIG_NFSD_SCSILAYOUT=y
+CONFIG_NFSD_FLEXFILELAYOUT=y
+CONFIG_NFSD_V4_2_INTER_SSC=y
+CONFIG_NFSD_V4_SECURITY_LABEL=y
+CONFIG_RPCSEC_GSS_KRB5_ENCTYPES_CAMELLIA=y
+CONFIG_RPCSEC_GSS_KRB5_ENCTYPES_AES_SHA2=y
+CONFIG_SUNRPC_DEBUG=y
+CONFIG_CEPH_FS=m
+CONFIG_CEPH_FSCACHE=y
+CONFIG_CEPH_FS_POSIX_ACL=y
+CONFIG_CEPH_FS_SECURITY_LABEL=y
+CONFIG_CIFS=m
+# CONFIG_CIFS_STATS2 is not set
+CONFIG_CIFS_UPCALL=y
+CONFIG_CIFS_XATTR=y
+CONFIG_CIFS_POSIX=y
+CONFIG_CIFS_DFS_UPCALL=y
+CONFIG_CIFS_SWN_UPCALL=y
+CONFIG_CIFS_FSCACHE=y
+CONFIG_SMB_SERVER=m
+CONFIG_SMB_SERVER_KERBEROS5=y
+CONFIG_CODA_FS=m
+CONFIG_AFS_FS=m
+CONFIG_AFS_FSCACHE=y
+CONFIG_9P_FS=m
+CONFIG_9P_FSCACHE=y
+CONFIG_9P_FS_POSIX_ACL=y
+CONFIG_9P_FS_SECURITY=y
+CONFIG_NLS_DEFAULT="utf8"
+CONFIG_NLS_CODEPAGE_437=y
+CONFIG_NLS_CODEPAGE_737=m
+CONFIG_NLS_CODEPAGE_775=m
+CONFIG_NLS_CODEPAGE_850=m
+CONFIG_NLS_CODEPAGE_852=m
+CONFIG_NLS_CODEPAGE_855=m
+CONFIG_NLS_CODEPAGE_857=m
+CONFIG_NLS_CODEPAGE_860=m
+CONFIG_NLS_CODEPAGE_861=m
+CONFIG_NLS_CODEPAGE_862=m
+CONFIG_NLS_CODEPAGE_863=m
+CONFIG_NLS_CODEPAGE_864=m
+CONFIG_NLS_CODEPAGE_865=m
+CONFIG_NLS_CODEPAGE_866=m
+CONFIG_NLS_CODEPAGE_869=m
+CONFIG_NLS_CODEPAGE_936=m
+CONFIG_NLS_CODEPAGE_950=m
+CONFIG_NLS_CODEPAGE_932=m
+CONFIG_NLS_CODEPAGE_949=m
+CONFIG_NLS_CODEPAGE_874=m
+CONFIG_NLS_ISO8859_8=m
+CONFIG_NLS_CODEPAGE_1250=m
+CONFIG_NLS_CODEPAGE_1251=m
+CONFIG_NLS_ASCII=m
+CONFIG_NLS_ISO8859_1=m
+CONFIG_NLS_ISO8859_2=m
+CONFIG_NLS_ISO8859_3=m
+CONFIG_NLS_ISO8859_4=m
+CONFIG_NLS_ISO8859_5=m
+CONFIG_NLS_ISO8859_6=m
+CONFIG_NLS_ISO8859_7=m
+CONFIG_NLS_ISO8859_9=m
+CONFIG_NLS_ISO8859_13=m
+CONFIG_NLS_ISO8859_14=m
+CONFIG_NLS_ISO8859_15=m
+CONFIG_NLS_KOI8_R=m
+CONFIG_NLS_KOI8_U=m
+CONFIG_NLS_MAC_ROMAN=m
+CONFIG_NLS_MAC_CELTIC=m
+CONFIG_NLS_MAC_CENTEURO=m
+CONFIG_NLS_MAC_CROATIAN=m
+CONFIG_NLS_MAC_CYRILLIC=m
+CONFIG_NLS_MAC_GAELIC=m
+CONFIG_NLS_MAC_GREEK=m
+CONFIG_NLS_MAC_ICELAND=m
+CONFIG_NLS_MAC_INUIT=m
+CONFIG_NLS_MAC_ROMANIAN=m
+CONFIG_NLS_MAC_TURKISH=m
+CONFIG_DLM=m
+CONFIG_UNICODE=y
+CONFIG_KEYS_REQUEST_CACHE=y
+CONFIG_PERSISTENT_KEYRINGS=y
+CONFIG_TRUSTED_KEYS=y
+CONFIG_USER_DECRYPTED_DATA=y
+CONFIG_KEY_DH_OPERATIONS=y
+CONFIG_KEY_NOTIFICATIONS=y
+CONFIG_SECURITY_DMESG_RESTRICT=y
+CONFIG_SECURITY=y
+CONFIG_SECURITY_NETWORK_XFRM=y
+CONFIG_LSM_MMAP_MIN_ADDR=0
+CONFIG_HARDENED_USERCOPY=y
+CONFIG_SECURITY_SELINUX=y
+CONFIG_SECURITY_SELINUX_BOOTPARAM=y
+CONFIG_SECURITY_SMACK=y
+CONFIG_SECURITY_SMACK_NETFILTER=y
+CONFIG_SECURITY_SMACK_APPEND_SIGNALS=y
+CONFIG_SECURITY_TOMOYO=y
+CONFIG_SECURITY_APPARMOR=y
+CONFIG_SECURITY_YAMA=y
+CONFIG_SECURITY_SAFESETID=y
+CONFIG_SECURITY_LOCKDOWN_LSM=y
+CONFIG_SECURITY_LOCKDOWN_LSM_EARLY=y
+CONFIG_SECURITY_LANDLOCK=y
+CONFIG_INTEGRITY_SIGNATURE=y
+CONFIG_INTEGRITY_ASYMMETRIC_KEYS=y
+CONFIG_INTEGRITY_PLATFORM_KEYRING=y
+CONFIG_INTEGRITY_MACHINE_KEYRING=y
+CONFIG_IMA=y
+CONFIG_IMA_KEXEC=y
+CONFIG_IMA_DEFAULT_HASH_SHA256=y
+CONFIG_IMA_APPRAISE=y
+CONFIG_IMA_ARCH_POLICY=y
+CONFIG_IMA_APPRAISE_MODSIG=y
+CONFIG_EVM=y
+CONFIG_EVM_EXTRA_SMACK_XATTRS=y
+CONFIG_EVM_ADD_XATTRS=y
+CONFIG_DEFAULT_SECURITY_APPARMOR=y
+CONFIG_LSM="landlock,lockdown,yama,integrity,apparmor"
+CONFIG_ZERO_CALL_USED_REGS=y
+CONFIG_CRYPTO_USER=m
+CONFIG_CRYPTO_PCRYPT=m
+CONFIG_CRYPTO_CRYPTD=m
+CONFIG_CRYPTO_TEST=m
+CONFIG_CRYPTO_ECDSA=m
+CONFIG_CRYPTO_ECRDSA=m
+CONFIG_CRYPTO_SM2=m
+CONFIG_CRYPTO_CURVE25519=m
+CONFIG_CRYPTO_AES_TI=m
+CONFIG_CRYPTO_ARIA=m
+CONFIG_CRYPTO_BLOWFISH=m
+CONFIG_CRYPTO_CAMELLIA=m
+CONFIG_CRYPTO_CAST5=m
+CONFIG_CRYPTO_CAST6=m
+CONFIG_CRYPTO_DES=m
+CONFIG_CRYPTO_SERPENT=m
+CONFIG_CRYPTO_SM4_GENERIC=m
+CONFIG_CRYPTO_TWOFISH=m
+CONFIG_CRYPTO_ADIANTUM=m
+CONFIG_CRYPTO_CFB=m
+CONFIG_CRYPTO_HCTR2=m
+CONFIG_CRYPTO_KEYWRAP=m
+CONFIG_CRYPTO_LRW=m
+CONFIG_CRYPTO_OFB=m
+CONFIG_CRYPTO_AEGIS128=m
+CONFIG_CRYPTO_CHACHA20POLY1305=m
+CONFIG_CRYPTO_GCM=y
+CONFIG_CRYPTO_SEQIV=y
+CONFIG_CRYPTO_MD4=m
+CONFIG_CRYPTO_RMD160=m
+CONFIG_CRYPTO_SM3_GENERIC=m
+CONFIG_CRYPTO_VMAC=m
+CONFIG_CRYPTO_WP512=m
+CONFIG_CRYPTO_XCBC=m
+CONFIG_CRYPTO_DEFLATE=y
+CONFIG_CRYPTO_842=m
+CONFIG_CRYPTO_LZ4=m
+CONFIG_CRYPTO_LZ4HC=m
+CONFIG_CRYPTO_ANSI_CPRNG=m
+CONFIG_CRYPTO_DRBG_HASH=y
+CONFIG_CRYPTO_DRBG_CTR=y
+CONFIG_CRYPTO_JITTERENTROPY_TESTINTERFACE=y
+CONFIG_CRYPTO_USER_API_HASH=m
+CONFIG_CRYPTO_USER_API_SKCIPHER=m
+CONFIG_CRYPTO_USER_API_RNG=m
+CONFIG_CRYPTO_USER_API_AEAD=m
+# CONFIG_CRYPTO_USER_API_ENABLE_OBSOLETE is not set
+CONFIG_CRYPTO_STATS=y
+CONFIG_CRYPTO_DEV_VIRTIO=y
+CONFIG_PKCS8_PRIVATE_KEY_PARSER=m
+CONFIG_PKCS7_TEST_KEY=m
+CONFIG_SIGNED_PE_FILE_VERIFICATION=y
+CONFIG_SYSTEM_EXTRA_CERTIFICATE=y
+CONFIG_SECONDARY_TRUSTED_KEYRING=y
+CONFIG_SYSTEM_BLACKLIST_KEYRING=y
+CONFIG_SYSTEM_REVOCATION_LIST=y
+CONFIG_CRC_ITU_T=y
+CONFIG_CRC7=y
+CONFIG_XZ_DEC_MICROLZMA=y
+CONFIG_XZ_DEC_TEST=m
+CONFIG_DMA_CMA=y
+CONFIG_CMA_SIZE_MBYTES=32
+CONFIG_IRQ_POLL=y
+CONFIG_FONTS=y
+CONFIG_FONT_8x8=y
+CONFIG_FONT_ACORN_8x8=y
+CONFIG_FONT_6x10=y
+CONFIG_FONT_TER16x32=y
+CONFIG_PRINTK_TIME=y
+CONFIG_CONSOLE_LOGLEVEL_QUIET=3
+CONFIG_BOOT_PRINTK_DELAY=y
+CONFIG_DYNAMIC_DEBUG=y
+CONFIG_VMLINUX_MAP=y
+CONFIG_MAGIC_SYSRQ_DEFAULT_ENABLE=0x01b6
+CONFIG_KGDB=y
+CONFIG_KGDB_KDB=y
+CONFIG_KDB_KEYBOARD=y
+CONFIG_PAGE_POISONING=y
+CONFIG_DEBUG_WX=y
+CONFIG_SCHED_STACK_END_CHECK=y
+CONFIG_KFENCE=y
+CONFIG_KFENCE_SAMPLE_INTERVAL=0
+CONFIG_HARDLOCKUP_DETECTOR=y
+CONFIG_WQ_CPU_INTENSIVE_REPORT=y
+CONFIG_RCU_CPU_STALL_TIMEOUT=60
+CONFIG_RCU_CPU_STALL_CPUTIME=y
+# CONFIG_RCU_TRACE is not set
+CONFIG_LATENCYTOP=y
+CONFIG_BOOTTIME_TRACING=y
+CONFIG_SCHED_TRACER=y
+CONFIG_HWLAT_TRACER=y
+CONFIG_TIMERLAT_TRACER=y
+CONFIG_FTRACE_SYSCALLS=y
+CONFIG_BLK_DEV_IO_TRACE=y
+CONFIG_BPF_KPROBE_OVERRIDE=y
+CONFIG_SYNTH_EVENTS=y
+CONFIG_USER_EVENTS=y
+CONFIG_TRACE_EVENT_INJECT=y
+CONFIG_RV=y
+CONFIG_RV_MON_WWNR=y
+CONFIG_SAMPLES=y
+CONFIG_SAMPLE_TRACE_PRINTK=m
+CONFIG_SAMPLE_TRACE_ARRAY=m
+CONFIG_NOTIFIER_ERROR_INJECTION=m
+CONFIG_FUNCTION_ERROR_INJECTION=y
+CONFIG_TEST_BPF=m
+CONFIG_TEST_BLACKHOLE_DEV=m
+CONFIG_MEMTEST=y
diff --git a/arch/riscv/include/asm/alternative-macros.h b/arch/riscv/include/asm/alternative-macros.h
index 231d777d936c..4d8f68fa80da 100644
--- a/arch/riscv/include/asm/alternative-macros.h
+++ b/arch/riscv/include/asm/alternative-macros.h
@@ -50,8 +50,17 @@
 	ALT_NEW_CONTENT \vendor_id_2, \patch_id_2, \enable_2, "\new_c_2"
 .endm
 
+.macro ALTERNATIVE_CFG_3 old_c, new_c_1, vendor_id_1, patch_id_1, enable_1,	\
+				new_c_2, vendor_id_2, patch_id_2, enable_2,	\
+				new_c_3, vendor_id_3, patch_id_3, enable_3
+	ALTERNATIVE_CFG_2 "\old_c", "\new_c_1", \vendor_id_1, \patch_id_1, \enable_1 \
+				    "\new_c_2", \vendor_id_2, \patch_id_2, \enable_2 \
+	ALT_NEW_CONTENT \vendor_id_3, \patch_id_3, \enable_3, "\new_c_3"
+.endm
+
 #define __ALTERNATIVE_CFG(...)		ALTERNATIVE_CFG __VA_ARGS__
 #define __ALTERNATIVE_CFG_2(...)	ALTERNATIVE_CFG_2 __VA_ARGS__
+#define __ALTERNATIVE_CFG_3(...)	ALTERNATIVE_CFG_3 __VA_ARGS__
 
 #else /* !__ASSEMBLY__ */
 
@@ -98,6 +107,13 @@
 	__ALTERNATIVE_CFG(old_c, new_c_1, vendor_id_1, patch_id_1, enable_1)	\
 	ALT_NEW_CONTENT(vendor_id_2, patch_id_2, enable_2, new_c_2)
 
+#define __ALTERNATIVE_CFG_3(old_c, new_c_1, vendor_id_1, patch_id_1, enable_1,	\
+				   new_c_2, vendor_id_2, patch_id_2, enable_2,	\
+				   new_c_3, vendor_id_3, patch_id_3, enable_3)	\
+	__ALTERNATIVE_CFG_2(old_c, new_c_1, vendor_id_1, patch_id_1, enable_1,	\
+				   new_c_2, vendor_id_2, patch_id_2, enable_2)	\
+	ALT_NEW_CONTENT(vendor_id_3, patch_id_3, enable_3, new_c_3)
+
 #endif /* __ASSEMBLY__ */
 
 #define _ALTERNATIVE_CFG(old_c, new_c, vendor_id, patch_id, CONFIG_k)	\
@@ -108,6 +124,13 @@
 	__ALTERNATIVE_CFG_2(old_c, new_c_1, vendor_id_1, patch_id_1, IS_ENABLED(CONFIG_k_1),	\
 				   new_c_2, vendor_id_2, patch_id_2, IS_ENABLED(CONFIG_k_2))
 
+#define _ALTERNATIVE_CFG_3(old_c, new_c_1, vendor_id_1, patch_id_1, CONFIG_k_1,		\
+				  new_c_2, vendor_id_2, patch_id_2, CONFIG_k_2,		\
+				  new_c_3, vendor_id_3, patch_id_3, CONFIG_k_3)		\
+	__ALTERNATIVE_CFG_3(old_c, new_c_1, vendor_id_1, patch_id_1, IS_ENABLED(CONFIG_k_1),	\
+				   new_c_2, vendor_id_2, patch_id_2, IS_ENABLED(CONFIG_k_2),	\
+				   new_c_3, vendor_id_3, patch_id_3, IS_ENABLED(CONFIG_k_3))
+
 #else /* CONFIG_RISCV_ALTERNATIVE */
 #ifdef __ASSEMBLY__
 
@@ -118,11 +141,17 @@
 #define __ALTERNATIVE_CFG(old_c, ...)		ALTERNATIVE_CFG old_c
 #define __ALTERNATIVE_CFG_2(old_c, ...)		ALTERNATIVE_CFG old_c
 
+#define _ALTERNATIVE_CFG_3(old_c, ...)	\
+	ALTERNATIVE_CFG old_c
+
 #else /* !__ASSEMBLY__ */
 
 #define __ALTERNATIVE_CFG(old_c, ...)		old_c "\n"
 #define __ALTERNATIVE_CFG_2(old_c, ...)		old_c "\n"
 
+#define _ALTERNATIVE_CFG_3(old_c, ...)	\
+	__ALTERNATIVE_CFG(old_c)
+
 #endif /* __ASSEMBLY__ */
 
 #define _ALTERNATIVE_CFG(old_c, ...)		__ALTERNATIVE_CFG(old_c)
@@ -147,15 +176,21 @@
 	_ALTERNATIVE_CFG(old_content, new_content, vendor_id, patch_id, CONFIG_k)
 
 /*
- * A vendor wants to replace an old_content, but another vendor has used
- * ALTERNATIVE() to patch its customized content at the same location. In
- * this case, this vendor can create a new macro ALTERNATIVE_2() based
- * on the following sample code and then replace ALTERNATIVE() with
- * ALTERNATIVE_2() to append its customized content.
+ * Variant of ALTERNATIVE() that supports two sets of replacement content.
  */
 #define ALTERNATIVE_2(old_content, new_content_1, vendor_id_1, patch_id_1, CONFIG_k_1,		\
 				   new_content_2, vendor_id_2, patch_id_2, CONFIG_k_2)		\
 	_ALTERNATIVE_CFG_2(old_content, new_content_1, vendor_id_1, patch_id_1, CONFIG_k_1,	\
 					new_content_2, vendor_id_2, patch_id_2, CONFIG_k_2)
 
+/*
+ * Variant of ALTERNATIVE() that supports three sets of replacement content.
+ */
+#define ALTERNATIVE_3(old_content, new_content_1, vendor_id_1, patch_id_1, CONFIG_k_1,		\
+				   new_content_2, vendor_id_2, patch_id_2, CONFIG_k_2,		\
+				   new_content_3, vendor_id_3, patch_id_3, CONFIG_k_3)		\
+	_ALTERNATIVE_CFG_3(old_content, new_content_1, vendor_id_1, patch_id_1, CONFIG_k_1,	\
+					new_content_2, vendor_id_2, patch_id_2, CONFIG_k_2,	\
+					new_content_3, vendor_id_3, patch_id_3, CONFIG_k_3)
+
 #endif
diff --git a/arch/riscv/include/asm/errata_list.h b/arch/riscv/include/asm/errata_list.h
index 6e426ed7919a..d41e9cb8c84f 100644
--- a/arch/riscv/include/asm/errata_list.h
+++ b/arch/riscv/include/asm/errata_list.h
@@ -60,49 +60,32 @@ asm(ALTERNATIVE("sfence.vma %0, %1", "sfence.vma", SIFIVE_VENDOR_ID,	\
 		: : "r" (addr), "r" (asid) : "memory")
 
 /*
- * _val is marked as "will be overwritten", so need to set it to 0
- * in the default case.
+ * dcache.ipa rs1 (invalidate, physical address)
+ * | 31 - 25 | 24 - 20 | 19 - 15 | 14 - 12 | 11 - 7 | 6 - 0 |
+ *   0000001    01010      rs1       000      00000  0001011
+ * dache.iva rs1 (invalida, virtual address)
+ *   0000001    00110      rs1       000      00000  0001011
+ *
+ * dcache.cpa rs1 (clean, physical address)
+ * | 31 - 25 | 24 - 20 | 19 - 15 | 14 - 12 | 11 - 7 | 6 - 0 |
+ *   0000001    01001      rs1       000      00000  0001011
+ * dcache.cva rs1 (clean, virtual address)
+ *   0000001    00101      rs1       000      00000  0001011
+ *
+ * dcache.cipa rs1 (clean then invalidate, physical address)
+ * | 31 - 25 | 24 - 20 | 19 - 15 | 14 - 12 | 11 - 7 | 6 - 0 |
+ *   0000001    01011      rs1       000      00000  0001011
+ * dcache.civa rs1 (... virtual address)
+ *   0000001    00111      rs1       000      00000  0001011
+ *
+ * sync.s (make sure all cache operations finished)
+ * | 31 - 25 | 24 - 20 | 19 - 15 | 14 - 12 | 11 - 7 | 6 - 0 |
+ *   0000000    11001     00000      000      00000  0001011
  */
-#define ALT_SVPBMT_SHIFT 61
-#define ALT_THEAD_MAE_SHIFT 59
-#define ALT_SVPBMT(_val, prot)						\
-asm(ALTERNATIVE_2("li %0, 0\t\nnop",					\
-		  "li %0, %1\t\nslli %0,%0,%3", 0,			\
-			RISCV_ISA_EXT_SVPBMT, CONFIG_RISCV_ISA_SVPBMT,	\
-		  "li %0, %2\t\nslli %0,%0,%4", THEAD_VENDOR_ID,	\
-			ERRATA_THEAD_MAE, CONFIG_ERRATA_THEAD_MAE)	\
-		: "=r"(_val)						\
-		: "I"(prot##_SVPBMT >> ALT_SVPBMT_SHIFT),		\
-		  "I"(prot##_THEAD >> ALT_THEAD_MAE_SHIFT),		\
-		  "I"(ALT_SVPBMT_SHIFT),				\
-		  "I"(ALT_THEAD_MAE_SHIFT))
-
-#ifdef CONFIG_ERRATA_THEAD_MAE
-/*
- * IO/NOCACHE memory types are handled together with svpbmt,
- * so on T-Head chips, check if no other memory type is set,
- * and set the non-0 PMA type if applicable.
- */
-#define ALT_THEAD_PMA(_val)						\
-asm volatile(ALTERNATIVE(						\
-	__nops(7),							\
-	"li      t3, %1\n\t"						\
-	"slli    t3, t3, %3\n\t"					\
-	"and     t3, %0, t3\n\t"					\
-	"bne     t3, zero, 2f\n\t"					\
-	"li      t3, %2\n\t"						\
-	"slli    t3, t3, %3\n\t"					\
-	"or      %0, %0, t3\n\t"					\
-	"2:",  THEAD_VENDOR_ID,						\
-		ERRATA_THEAD_MAE, CONFIG_ERRATA_THEAD_MAE)		\
-	: "+r"(_val)							\
-	: "I"(_PAGE_MTMASK_THEAD >> ALT_THEAD_MAE_SHIFT),		\
-	  "I"(_PAGE_PMA_THEAD >> ALT_THEAD_MAE_SHIFT),			\
-	  "I"(ALT_THEAD_MAE_SHIFT)					\
-	: "t3")
-#else
-#define ALT_THEAD_PMA(_val)
-#endif
+#define THEAD_inval_A0	".long 0x0265000b"
+#define THEAD_clean_A0	".long 0x0255000b"
+#define THEAD_flush_A0	".long 0x0275000b"
+#define THEAD_SYNC_S	".long 0x0190000b"
 
 #define ALT_CMO_OP(_op, _start, _size, _cachesize)			\
 asm volatile(ALTERNATIVE(						\
diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h
index affd63e11b0a..d8dd9db1f148 100644
--- a/arch/riscv/include/asm/hwcap.h
+++ b/arch/riscv/include/asm/hwcap.h
@@ -106,12 +106,15 @@
 #define RISCV_ISA_EXT_ZAAMO		97
 #define RISCV_ISA_EXT_ZALRSC		98
 #define RISCV_ISA_EXT_ZICBOP		99
+#define RISCV_ISA_EXT_XLINUXMEMALIAS	126
 
 #define RISCV_ISA_EXT_XLINUXENVCFG	127
 
 #define RISCV_ISA_EXT_MAX		128
 #define RISCV_ISA_EXT_INVALID		U32_MAX
 
+
+
 #ifdef CONFIG_RISCV_M_MODE
 #define RISCV_ISA_EXT_SxAIA		RISCV_ISA_EXT_SMAIA
 #define RISCV_ISA_EXT_SUPM		RISCV_ISA_EXT_SMNPM
diff --git a/arch/riscv/include/asm/pgtable-32.h b/arch/riscv/include/asm/pgtable-32.h
index 00f3369570a8..ba50b65b434b 100644
--- a/arch/riscv/include/asm/pgtable-32.h
+++ b/arch/riscv/include/asm/pgtable-32.h
@@ -17,21 +17,12 @@
 
 #define MAX_POSSIBLE_PHYSMEM_BITS 34
 
-/*
- * rv32 PTE format:
- * | XLEN-1  10 | 9             8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
- *       PFN      reserved for SW   D   A   G   U   X   W   R   V
- */
-#define _PAGE_PFN_MASK  GENMASK(31, 10)
-
-#define _PAGE_NOCACHE		0
-#define _PAGE_IO		0
-#define _PAGE_MTMASK		0
+#define ALT_FIXUP_MT(_val)
+#define ALT_UNFIX_MT(_val)
 
-/* Set of bits to preserve across pte_modify() */
-#define _PAGE_CHG_MASK  (~(unsigned long)(_PAGE_PRESENT | _PAGE_READ |	\
-					  _PAGE_WRITE | _PAGE_EXEC |	\
-					  _PAGE_USER | _PAGE_GLOBAL))
+#define pud_pfn(pud)				(pmd_pfn((pmd_t){ pud }))
+#define p4d_pfn(p4d)				(pud_pfn((pud_t){ p4d }))
+#define pgd_pfn(pgd)				(p4d_pfn((p4d_t){ pgd }))
 
 static const __maybe_unused int pgtable_l4_enabled;
 static const __maybe_unused int pgtable_l5_enabled;
diff --git a/arch/riscv/include/asm/pgtable-64.h b/arch/riscv/include/asm/pgtable-64.h
index 7de05db7d3bd..a0bf655d8e53 100644
--- a/arch/riscv/include/asm/pgtable-64.h
+++ b/arch/riscv/include/asm/pgtable-64.h
@@ -8,7 +8,7 @@
 
 #include <linux/bits.h>
 #include <linux/const.h>
-#include <asm/errata_list.h>
+#include <asm/alternative-macros.h>
 
 extern bool pgtable_l4_enabled;
 extern bool pgtable_l5_enabled;
@@ -66,23 +66,8 @@ typedef struct {
 
 #define pmd_val(x)      ((x).pmd)
 #define __pmd(x)        ((pmd_t) { (x) })
-
 #define PTRS_PER_PMD    (PAGE_SIZE / sizeof(pmd_t))
 
-/*
- * rv64 PTE format:
- * | 63 | 62 61 | 60 54 | 53  10 | 9             8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
- *   N      MT     RSV    PFN      reserved for SW   D   A   G   U   X   W   R   V
- */
-#define _PAGE_PFN_MASK  GENMASK(53, 10)
-
-/*
- * [63] Svnapot definitions:
- * 0 Svnapot disabled
- * 1 Svnapot enabled
- */
-#define _PAGE_NAPOT_SHIFT	63
-#define _PAGE_NAPOT		BIT(_PAGE_NAPOT_SHIFT)
 /*
  * Only 64KB (order 4) napot ptes supported.
  */
@@ -110,17 +95,7 @@ enum napot_cont_order {
 #define HUGE_MAX_HSTATE		2
 #endif
 
-/*
- * [62:61] Svpbmt Memory Type definitions:
- *
- *  00 - PMA    Normal Cacheable, No change to implied PMA memory type
- *  01 - NC     Non-cacheable, idempotent, weakly-ordered Main Memory
- *  10 - IO     Non-cacheable, non-idempotent, strongly-ordered I/O memory
- *  11 - Rsvd   Reserved for future standard use
- */
-#define _PAGE_NOCACHE_SVPBMT	(1UL << 61)
-#define _PAGE_IO_SVPBMT		(1UL << 62)
-#define _PAGE_MTMASK_SVPBMT	(_PAGE_NOCACHE_SVPBMT | _PAGE_IO_SVPBMT)
+#ifdef CONFIG_RISCV_ISA_SVPBMT
 
 /*
  * [63:59] T-Head Memory Type definitions:
@@ -132,45 +107,82 @@ enum napot_cont_order {
  * 00110 - NC   Weakly-ordered, Non-cacheable, Bufferable, Shareable, Non-trustable
  * 01110 - PMA  Weakly-ordered, Cacheable, Bufferable, Shareable, Non-trustable
  * 10010 - IO   Strongly-ordered, Non-cacheable, Non-bufferable, Shareable, Non-trustable
+ *
+ * ALT_FIXUP_MT translates Svpbmt memory types to XTheadMae memory types.
+ * Pseudocode operating on bits [63:60]:
+ *   t0 = mt << 1
+ *   if (t0 == 0)
+ *     t0 |= 2
+ *   t0 ^= 0x5
+ *   mt ^= t0
+ *
+ * ALT_UNFIX_MT translates XTheadMae memory types to Svpbmt memory types.
+ * Pseudocode operating on bits [63:60]:
+ *   t0 = mt & 0xd
+ *   t0 ^= t0 >> 1
+ *   mt ^= t0
  */
 #define _PAGE_PMA_THEAD		((1UL << 62) | (1UL << 61) | (1UL << 60))
 #define _PAGE_NOCACHE_THEAD	((1UL << 61) | (1UL << 60))
 #define _PAGE_IO_THEAD		((1UL << 63) | (1UL << 60))
 #define _PAGE_MTMASK_THEAD	(_PAGE_PMA_THEAD | _PAGE_IO_THEAD | (1UL << 59))
 
-static inline u64 riscv_page_mtmask(void)
-{
-	u64 val;
-
-	ALT_SVPBMT(val, _PAGE_MTMASK);
-	return val;
-}
-
-static inline u64 riscv_page_nocache(void)
-{
-	u64 val;
-
-	ALT_SVPBMT(val, _PAGE_NOCACHE);
-	return val;
-}
-
-static inline u64 riscv_page_io(void)
-{
-	u64 val;
+#define ALT_FIXUP_MT(_val)								\
+	asm(ALTERNATIVE_3("addi	t0, zero, 0x3\n\t"					\
+			  "slli	t0, t0, 61\n\t"						\
+			  "not	t0, t0\n\t"						\
+			  "and	%0, %0, t0\n\t"						\
+			  "nop\n\t"							\
+			  "nop\n\t"							\
+			  "nop\n\t"							\
+			  "nop",							\
+			  __nops(8),							\
+			  0, RISCV_ISA_EXT_SVPBMT, CONFIG_RISCV_ISA_SVPBMT,		\
+			  "addi t0, zero, 0x3\n\t"					\
+			  "slli	t0, t0, 61\n\t"						\
+			  "and	t0, %0, t0\n\t"						\
+			  "beqz t0, 2f\n\t"						\
+			  "xor	t1, %0, t0\n\t"						\
+			  "1: auipc t0, %%pcrel_hi(riscv_fixup_memory_alias)\n\t"	\
+			  "jalr	t0, t0, %%pcrel_lo(1b)\n\t"				\
+			  "mv	%0, t1\n"						\
+			  "2:",								\
+			  0, RISCV_ISA_EXT_XLINUXMEMALIAS, CONFIG_RISCV_ISA_SVPBMT,	\
+			  "srli	t0, %0, 59\n\t"						\
+			  "seqz t1, t0\n\t"						\
+			  "slli	t1, t1, 1\n\t"						\
+			  "or	t0, t0, t1\n\t"						\
+			  "xori	t0, t0, 0x5\n\t"					\
+			  "slli	t0, t0, 60\n\t"						\
+			  "xor	%0, %0, t0\n\t"						\
+			  "nop",							\
+			  THEAD_VENDOR_ID, ERRATA_THEAD_MAE, CONFIG_ERRATA_THEAD_MAE)	\
+			  : "+r" (_val) :: "t0", "t1")
+
+#define ALT_UNFIX_MT(_val)								\
+	asm(ALTERNATIVE_2(__nops(6),							\
+			  "mv	t1, %0\n\t"						\
+			  "1: auipc t0, %%pcrel_hi(riscv_unfix_memory_alias)\n\t"	\
+			  "jalr	t0, t0, %%pcrel_lo(1b)\n\t"				\
+			  "mv	%0, t1\n\t"						\
+			  "nop\n\t"							\
+			  "nop",							\
+			  0, RISCV_ISA_EXT_XLINUXMEMALIAS, CONFIG_RISCV_ISA_SVPBMT,	\
+			  "srli	t0, %0, 60\n\t"						\
+			  "andi	t0, t0, 0xd\n\t"					\
+			  "srli	t1, t0, 1\n\t"						\
+			  "xor	t0, t0, t1\n\t"						\
+			  "slli	t0, t0, 60\n\t"						\
+			  "xor	%0, %0, t0",						\
+			  THEAD_VENDOR_ID, ERRATA_THEAD_MAE, CONFIG_ERRATA_THEAD_MAE)	\
+			  : "+r" (_val) :: "t0", "t1")
 
-	ALT_SVPBMT(val, _PAGE_IO);
-	return val;
-}
+#else
 
-#define _PAGE_NOCACHE		riscv_page_nocache()
-#define _PAGE_IO		riscv_page_io()
-#define _PAGE_MTMASK		riscv_page_mtmask()
+#define ALT_FIXUP_MT(_val)
+#define ALT_UNFIX_MT(_val)
 
-/* Set of bits to preserve across pte_modify() */
-#define _PAGE_CHG_MASK  (~(unsigned long)(_PAGE_PRESENT | _PAGE_READ |	\
-					  _PAGE_WRITE | _PAGE_EXEC |	\
-					  _PAGE_USER | _PAGE_GLOBAL |	\
-					  _PAGE_MTMASK))
+#endif /* CONFIG_RISCV_ISA_SVPBMT */
 
 static inline int pud_present(pud_t pud)
 {
@@ -210,22 +222,27 @@ static inline void pud_clear(pud_t *pudp)
 
 static inline pud_t pfn_pud(unsigned long pfn, pgprot_t prot)
 {
-	return __pud((pfn << _PAGE_PFN_SHIFT) | pgprot_val(prot));
+	pud_t pud = __pud((pfn << _PAGE_PFN_SHIFT) | pgprot_val(prot));
+
+	ALT_FIXUP_MT(pud);
+
+	return pud;
 }
 
-static inline unsigned long _pud_pfn(pud_t pud)
+#define pud_pfn pud_pfn
+static inline unsigned long pud_pfn(pud_t pud)
 {
 	return __page_val_to_pfn(pud_val(pud));
 }
 
 static inline pmd_t *pud_pgtable(pud_t pud)
 {
-	return (pmd_t *)pfn_to_virt(__page_val_to_pfn(pud_val(pud)));
+	return (pmd_t *)pfn_to_virt(pud_pfn(pud));
 }
 
 static inline struct page *pud_page(pud_t pud)
 {
-	return pfn_to_page(__page_val_to_pfn(pud_val(pud)));
+	return pfn_to_page(pud_pfn(pud));
 }
 
 #define mm_p4d_folded  mm_p4d_folded
@@ -250,11 +267,11 @@ static inline bool mm_pud_folded(struct mm_struct *mm)
 
 static inline pmd_t pfn_pmd(unsigned long pfn, pgprot_t prot)
 {
-	unsigned long prot_val = pgprot_val(prot);
+	pmd_t pmd = __pmd((pfn << _PAGE_PFN_SHIFT) | pgprot_val(prot));
 
-	ALT_THEAD_PMA(prot_val);
+	ALT_FIXUP_MT(pmd);
 
-	return __pmd((pfn << _PAGE_PFN_SHIFT) | prot_val);
+	return pmd;
 }
 
 static inline unsigned long _pmd_pfn(pmd_t pmd)
@@ -262,6 +279,8 @@ static inline unsigned long _pmd_pfn(pmd_t pmd)
 	return __page_val_to_pfn(pmd_val(pmd));
 }
 
+#define mk_pmd(page, prot)    pfn_pmd(page_to_pfn(page), prot)
+
 #define pmd_ERROR(e) \
 	pr_err("%s:%d: bad pmd %016lx.\n", __FILE__, __LINE__, pmd_val(e))
 
@@ -311,10 +330,14 @@ static inline void p4d_clear(p4d_t *p4d)
 
 static inline p4d_t pfn_p4d(unsigned long pfn, pgprot_t prot)
 {
-	return __p4d((pfn << _PAGE_PFN_SHIFT) | pgprot_val(prot));
+	p4d_t p4d = __p4d((pfn << _PAGE_PFN_SHIFT) | pgprot_val(prot));
+
+	ALT_FIXUP_MT(p4d);
+
+	return p4d;
 }
 
-static inline unsigned long _p4d_pfn(p4d_t p4d)
+static inline unsigned long p4d_pfn(p4d_t p4d)
 {
 	return __page_val_to_pfn(p4d_val(p4d));
 }
@@ -322,7 +345,7 @@ static inline unsigned long _p4d_pfn(p4d_t p4d)
 static inline pud_t *p4d_pgtable(p4d_t p4d)
 {
 	if (pgtable_l4_enabled)
-		return (pud_t *)pfn_to_virt(__page_val_to_pfn(p4d_val(p4d)));
+		return (pud_t *)pfn_to_virt(p4d_pfn(p4d));
 
 	return (pud_t *)pud_pgtable((pud_t) { p4d_val(p4d) });
 }
@@ -330,7 +353,7 @@ static inline pud_t *p4d_pgtable(p4d_t p4d)
 
 static inline struct page *p4d_page(p4d_t p4d)
 {
-	return pfn_to_page(__page_val_to_pfn(p4d_val(p4d)));
+	return pfn_to_page(p4d_pfn(p4d));
 }
 
 #define pud_index(addr) (((addr) >> PUD_SHIFT) & (PTRS_PER_PUD - 1))
@@ -376,10 +399,15 @@ static inline void pgd_clear(pgd_t *pgd)
 		set_pgd(pgd, __pgd(0));
 }
 
+static inline unsigned long pgd_pfn(pgd_t pgd)
+{
+	return __page_val_to_pfn(pgd_val(pgd));
+}
+
 static inline p4d_t *pgd_pgtable(pgd_t pgd)
 {
 	if (pgtable_l5_enabled)
-		return (p4d_t *)pfn_to_virt(__page_val_to_pfn(pgd_val(pgd)));
+		return (p4d_t *)pfn_to_virt(pgd_pfn(pgd));
 
 	return (p4d_t *)p4d_pgtable((p4d_t) { pgd_val(pgd) });
 }
@@ -387,9 +415,8 @@ static inline p4d_t *pgd_pgtable(pgd_t pgd)
 
 static inline struct page *pgd_page(pgd_t pgd)
 {
-	return pfn_to_page(__page_val_to_pfn(pgd_val(pgd)));
+	return pfn_to_page(pgd_pfn(pgd));
 }
-#define pgd_page(pgd)	pgd_page(pgd)
 
 #define p4d_index(addr) (((addr) >> P4D_SHIFT) & (PTRS_PER_P4D - 1))
 
diff --git a/arch/riscv/include/asm/pgtable-bits.h b/arch/riscv/include/asm/pgtable-bits.h
index a8f5205cea54..96710d4c1817 100644
--- a/arch/riscv/include/asm/pgtable-bits.h
+++ b/arch/riscv/include/asm/pgtable-bits.h
@@ -6,6 +6,16 @@
 #ifndef _ASM_RISCV_PGTABLE_BITS_H
 #define _ASM_RISCV_PGTABLE_BITS_H
 
+/*
+ * rv32 PTE format:
+ * | XLEN-1  10 | 9             8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
+ *       PFN      reserved for SW   D   A   G   U   X   W   R   V
+ *
+ * rv64 PTE format:
+ * | 63 | 62 61 | 60 54 | 53 10 | 9             8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
+ *   N      MT     RSV     PFN    reserved for SW   D   A   G   U   X   W   R   V
+ */
+
 #define _PAGE_ACCESSED_OFFSET 6
 
 #define _PAGE_PRESENT   (1 << 0)
@@ -22,6 +32,36 @@
 #define _PAGE_DEVMAP    (1 << 9)    /* RSW, devmap */
 #define _PAGE_TABLE     _PAGE_PRESENT
 
+#define _PAGE_PFN_SHIFT		10
+#ifdef CONFIG_64BIT
+#define _PAGE_PFN_MASK		GENMASK(53, 10)
+#else
+#define _PAGE_PFN_MASK		GENMASK(31, 10)
+#endif /* CONFIG_64BIT */
+
+#ifdef CONFIG_RISCV_ISA_SVPBMT
+/*
+ * [62:61] Svpbmt Memory Type definitions:
+ *
+ *  00 - PMA    Normal Cacheable, No change to implied PMA memory type
+ *  01 - NC     Non-cacheable, idempotent, weakly-ordered Main Memory
+ *  10 - IO     Non-cacheable, non-idempotent, strongly-ordered I/O memory
+ *  11 - Rsvd   Reserved for future standard use
+ */
+#define _PAGE_NOCACHE		(UL(1) << 61)
+#define _PAGE_IO		(UL(2) << 61)
+#define _PAGE_MTMASK		(UL(3) << 61)
+#else
+#define _PAGE_NOCACHE		0
+#define _PAGE_IO		0
+#define _PAGE_MTMASK		0
+#endif /* CONFIG_RISCV_ISA_SVPBMT */
+
+#ifdef CONFIG_RISCV_ISA_SVNAPOT
+#define _PAGE_NAPOT_SHIFT	63
+#define _PAGE_NAPOT		BIT(_PAGE_NAPOT_SHIFT)
+#endif /* CONFIG_RISCV_ISA_SVNAPOT */
+
 /*
  * _PAGE_PROT_NONE is set on not-present pages (and ignored by the hardware) to
  * distinguish them from swapped out pages
@@ -31,8 +71,6 @@
 /* Used for swap PTEs only. */
 #define _PAGE_SWP_EXCLUSIVE _PAGE_ACCESSED
 
-#define _PAGE_PFN_SHIFT 10
-
 /*
  * when all of R/W/X are zero, the PTE is a pointer to the next level
  * of the page table; otherwise, it is a leaf PTE.
diff --git a/arch/riscv/include/asm/pgtable.h b/arch/riscv/include/asm/pgtable.h
index 5bd5aae60d53..cbcbf8993058 100644
--- a/arch/riscv/include/asm/pgtable.h
+++ b/arch/riscv/include/asm/pgtable.h
@@ -206,6 +206,12 @@ extern struct pt_alloc_ops pt_ops __meminitdata;
 #define _PAGE_IOREMAP	((_PAGE_KERNEL & ~_PAGE_MTMASK) | _PAGE_IO)
 #define PAGE_KERNEL_IO		__pgprot(_PAGE_IOREMAP)
 
+/* Set of bits to preserve across pte_modify() */
+#define _PAGE_CHG_MASK  (~(unsigned long)(_PAGE_PRESENT | _PAGE_READ |	\
+					  _PAGE_WRITE | _PAGE_EXEC |	\
+					  _PAGE_USER | _PAGE_GLOBAL |	\
+					  _PAGE_MTMASK))
+
 extern pgd_t swapper_pg_dir[];
 extern pgd_t trampoline_pg_dir[];
 extern pgd_t early_pg_dir[];
@@ -256,26 +262,26 @@ static inline void pmd_clear(pmd_t *pmdp)
 
 static inline pgd_t pfn_pgd(unsigned long pfn, pgprot_t prot)
 {
-	unsigned long prot_val = pgprot_val(prot);
+	pgd_t pgd = __pgd((pfn << _PAGE_PFN_SHIFT) | pgprot_val(prot));
 
-	ALT_THEAD_PMA(prot_val);
+	ALT_FIXUP_MT(pgd);
 
-	return __pgd((pfn << _PAGE_PFN_SHIFT) | prot_val);
+	return pgd;
 }
 
-static inline unsigned long _pgd_pfn(pgd_t pgd)
+static inline unsigned long pmd_pfn(pmd_t pmd)
 {
-	return __page_val_to_pfn(pgd_val(pgd));
+	return __page_val_to_pfn(pmd_val(pmd));
 }
 
 static inline struct page *pmd_page(pmd_t pmd)
 {
-	return pfn_to_page(__page_val_to_pfn(pmd_val(pmd)));
+	return pfn_to_page(pmd_pfn(pmd));
 }
 
 static inline unsigned long pmd_page_vaddr(pmd_t pmd)
 {
-	return (unsigned long)pfn_to_virt(__page_val_to_pfn(pmd_val(pmd)));
+	return (unsigned long)pfn_to_virt(pmd_pfn(pmd));
 }
 
 static inline pte_t pmd_pte(pmd_t pmd)
@@ -323,7 +329,10 @@ static inline unsigned long pte_napot(pte_t pte)
 /* Yields the page frame number (PFN) of a page table entry */
 static inline unsigned long pte_pfn(pte_t pte)
 {
-	unsigned long res  = __page_val_to_pfn(pte_val(pte));
+	unsigned long res;
+
+	ALT_UNFIX_MT(pte);
+	res  = __page_val_to_pfn(pte_val(pte));
 
 	if (has_svnapot() && pte_napot(pte))
 		res = res & (res - 1UL);
@@ -336,11 +345,11 @@ static inline unsigned long pte_pfn(pte_t pte)
 /* Constructs a page table entry */
 static inline pte_t pfn_pte(unsigned long pfn, pgprot_t prot)
 {
-	unsigned long prot_val = pgprot_val(prot);
+	pte_t pte = __pte((pfn << _PAGE_PFN_SHIFT) | pgprot_val(prot));
 
-	ALT_THEAD_PMA(prot_val);
+	ALT_FIXUP_MT(pte);
 
-	return __pte((pfn << _PAGE_PFN_SHIFT) | prot_val);
+	return pte;
 }
 
 #define pte_pgprot pte_pgprot
@@ -493,9 +502,11 @@ static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
 {
 	unsigned long newprot_val = pgprot_val(newprot);
 
-	ALT_THEAD_PMA(newprot_val);
+	ALT_UNFIX_MT(pte);
+	pte = __pte((pte_val(pte) & _PAGE_CHG_MASK) | newprot_val);
+	ALT_FIXUP_MT(pte);
 
-	return __pte((pte_val(pte) & _PAGE_CHG_MASK) | newprot_val);
+	return pte;
 }
 
 #define pgd_ERROR(e) \
@@ -699,21 +710,6 @@ static inline pmd_t pmd_mkinvalid(pmd_t pmd)
 	return __pmd(pmd_val(pmd) & ~(_PAGE_PRESENT|_PAGE_PROT_NONE));
 }
 
-#define __pmd_to_phys(pmd)  (__page_val_to_pfn(pmd_val(pmd)) << PAGE_SHIFT)
-
-static inline unsigned long pmd_pfn(pmd_t pmd)
-{
-	return ((__pmd_to_phys(pmd) & PMD_MASK) >> PAGE_SHIFT);
-}
-
-#define __pud_to_phys(pud)  (__page_val_to_pfn(pud_val(pud)) << PAGE_SHIFT)
-
-#define pud_pfn pud_pfn
-static inline unsigned long pud_pfn(pud_t pud)
-{
-	return ((__pud_to_phys(pud) & PUD_MASK) >> PAGE_SHIFT);
-}
-
 #define pmd_pgprot pmd_pgprot
 static inline pgprot_t pmd_pgprot(pmd_t pmd)
 {
@@ -1114,6 +1110,14 @@ extern u64 satp_mode;
 void paging_init(void);
 void misc_mem_init(void);
 
+#ifdef CONFIG_RISCV_ISA_SVPBMT
+bool __init riscv_have_memory_alias(void);
+void __init riscv_init_memory_alias(void);
+#else
+static inline bool riscv_have_memory_alias(void) { return false; }
+static inline void riscv_init_memory_alias(void) {}
+#endif /* CONFIG_RISCV_ISA_SVPBMT */
+
 /*
  * ZERO_PAGE is a global shared page that is always zero,
  * used for zero-mapped memory areas, etc.
diff --git a/arch/riscv/kernel/alternative.c b/arch/riscv/kernel/alternative.c
index 7eb3cb1215c6..249ee55d0547 100644
--- a/arch/riscv/kernel/alternative.c
+++ b/arch/riscv/kernel/alternative.c
@@ -121,8 +121,8 @@ void riscv_alternative_fix_offsets(void *alt_ptr, unsigned int len,
 			if (!riscv_insn_is_jalr(insn2))
 				continue;
 
-			/* if instruction pair is a call, it will use the ra register */
-			if (RV_EXTRACT_RD_REG(insn) != 1)
+			/* if instruction pair is a call, it will save a link register */
+			if (RV_EXTRACT_RD_REG(insn) == 0)
 				continue;
 
 			riscv_alternative_fix_auipc_jalr(alt_ptr + i * sizeof(u32),
diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
index 743d53415572..1449c43eab72 100644
--- a/arch/riscv/kernel/cpufeature.c
+++ b/arch/riscv/kernel/cpufeature.c
@@ -1093,6 +1093,12 @@ void __init riscv_fill_hwcap(void)
 		riscv_v_setup_vsize();
 	}
 
+	/* Vendor-independent alternatives require a bit in the ISA bitmap. */
+	if (riscv_have_memory_alias()) {
+		set_bit(RISCV_ISA_EXT_XLINUXMEMALIAS, riscv_isa);
+		pr_info("Using physical memory alias for noncached mappings\n");
+	}
+
 	memset(print_str, 0, sizeof(print_str));
 	for (i = 0, j = 0; i < NUM_ALPHA_EXTS; i++)
 		if (riscv_isa[0] & BIT_MASK(i))
diff --git a/arch/riscv/kernel/setup.c b/arch/riscv/kernel/setup.c
index 14888e5ea19a..6a296bd6017c 100644
--- a/arch/riscv/kernel/setup.c
+++ b/arch/riscv/kernel/setup.c
@@ -351,6 +351,7 @@ void __init setup_arch(char **cmdline_p)
 	}
 
 	riscv_init_cbo_blocksizes();
+	riscv_init_memory_alias();
 	riscv_fill_hwcap();
 	apply_boot_alternatives();
 	init_rt_signal_env();
diff --git a/arch/riscv/kvm/vcpu.c b/arch/riscv/kvm/vcpu.c
index 0462863206ca..f148fdc11eec 100644
--- a/arch/riscv/kvm/vcpu.c
+++ b/arch/riscv/kvm/vcpu.c
@@ -591,7 +591,9 @@ void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
 		nacl_csr_write(nsh, CSR_HEDELEG, cfg->hedeleg);
 		nacl_csr_write(nsh, CSR_HVIP, csr->hvip);
 		nacl_csr_write(nsh, CSR_VSATP, csr->vsatp);
+#ifndef CONFIG_SOC_SIFIVE_EIC7700
 		nacl_csr_write(nsh, CSR_HENVCFG, cfg->henvcfg);
+#endif
 		if (IS_ENABLED(CONFIG_32BIT))
 			nacl_csr_write(nsh, CSR_HENVCFGH, cfg->henvcfg >> 32);
 		if (riscv_has_extension_unlikely(RISCV_ISA_EXT_SMSTATEEN)) {
@@ -610,7 +612,9 @@ void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
 		csr_write(CSR_HEDELEG, cfg->hedeleg);
 		csr_write(CSR_HVIP, csr->hvip);
 		csr_write(CSR_VSATP, csr->vsatp);
+#ifndef CONFIG_SOC_SIFIVE_EIC7700
 		csr_write(CSR_HENVCFG, cfg->henvcfg);
+#endif
 		if (IS_ENABLED(CONFIG_32BIT))
 			csr_write(CSR_HENVCFGH, cfg->henvcfg >> 32);
 		if (riscv_has_extension_unlikely(RISCV_ISA_EXT_SMSTATEEN)) {
@@ -786,7 +790,9 @@ static void noinstr kvm_riscv_vcpu_enter_exit(struct kvm_vcpu *vcpu,
 	 * potentially change trap CSRs.
 	 */
 
+#ifndef CONFIG_SOC_SIFIVE_EIC7700
 	kvm_riscv_vcpu_swap_in_guest_state(vcpu);
+#endif
 	guest_state_enter_irqoff();
 
 	if (kvm_riscv_nacl_sync_sret_available()) {
@@ -848,7 +854,9 @@ static void noinstr kvm_riscv_vcpu_enter_exit(struct kvm_vcpu *vcpu,
 
 	vcpu->arch.last_exit_cpu = vcpu->cpu;
 	guest_state_exit_irqoff();
+#ifndef CONFIG_SOC_SIFIVE_EIC7700
 	kvm_riscv_vcpu_swap_in_host_state(vcpu);
+#endif
 }
 
 int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu)
diff --git a/arch/riscv/mm/Makefile b/arch/riscv/mm/Makefile
index b916a68d324a..27eefa08df05 100644
--- a/arch/riscv/mm/Makefile
+++ b/arch/riscv/mm/Makefile
@@ -33,3 +33,4 @@ endif
 obj-$(CONFIG_DEBUG_VIRTUAL) += physaddr.o
 obj-$(CONFIG_RISCV_DMA_NONCOHERENT) += dma-noncoherent.o
 obj-$(CONFIG_RISCV_NONSTANDARD_CACHE_OPS) += cache-ops.o
+obj-$(CONFIG_RISCV_ISA_SVPBMT) += memory-alias.o
diff --git a/arch/riscv/mm/init.c b/arch/riscv/mm/init.c
index 8d0374d7ce8e..b457d317d710 100644
--- a/arch/riscv/mm/init.c
+++ b/arch/riscv/mm/init.c
@@ -552,7 +552,7 @@ static void __meminit create_pmd_mapping(pmd_t *pmdp,
 		ptep = pt_ops.get_pte_virt(pte_phys);
 		memset(ptep, 0, PAGE_SIZE);
 	} else {
-		pte_phys = PFN_PHYS(_pmd_pfn(pmdp[pmd_idx]));
+		pte_phys = PFN_PHYS(pmd_pfn(pmdp[pmd_idx]));
 		ptep = pt_ops.get_pte_virt(pte_phys);
 	}
 
@@ -654,7 +654,7 @@ static void __meminit create_pud_mapping(pud_t *pudp, uintptr_t va, phys_addr_t
 		nextp = pt_ops.get_pmd_virt(next_phys);
 		memset(nextp, 0, PAGE_SIZE);
 	} else {
-		next_phys = PFN_PHYS(_pud_pfn(pudp[pud_index]));
+		next_phys = PFN_PHYS(pud_pfn(pudp[pud_index]));
 		nextp = pt_ops.get_pmd_virt(next_phys);
 	}
 
@@ -680,7 +680,7 @@ static void __meminit create_p4d_mapping(p4d_t *p4dp, uintptr_t va, phys_addr_t
 		nextp = pt_ops.get_pud_virt(next_phys);
 		memset(nextp, 0, PAGE_SIZE);
 	} else {
-		next_phys = PFN_PHYS(_p4d_pfn(p4dp[p4d_index]));
+		next_phys = PFN_PHYS(p4d_pfn(p4dp[p4d_index]));
 		nextp = pt_ops.get_pud_virt(next_phys);
 	}
 
@@ -737,7 +737,7 @@ void __meminit create_pgd_mapping(pgd_t *pgdp, uintptr_t va, phys_addr_t pa, phy
 		nextp = get_pgd_next_virt(next_phys);
 		memset(nextp, 0, PAGE_SIZE);
 	} else {
-		next_phys = PFN_PHYS(_pgd_pfn(pgdp[pgd_idx]));
+		next_phys = PFN_PHYS(pgd_pfn(pgdp[pgd_idx]));
 		nextp = get_pgd_next_virt(next_phys);
 	}
 
diff --git a/arch/riscv/mm/kasan_init.c b/arch/riscv/mm/kasan_init.c
index 41c635d6aca4..45ede663277a 100644
--- a/arch/riscv/mm/kasan_init.c
+++ b/arch/riscv/mm/kasan_init.c
@@ -171,7 +171,7 @@ static void __init kasan_early_clear_pud(p4d_t *p4dp,
 	if (!pgtable_l4_enabled) {
 		pudp = (pud_t *)p4dp;
 	} else {
-		base_pud = pt_ops.get_pud_virt(pfn_to_phys(_p4d_pfn(p4dp_get(p4dp))));
+		base_pud = pt_ops.get_pud_virt(pfn_to_phys(p4d_pfn(p4dp_get(p4dp))));
 		pudp = base_pud + pud_index(vaddr);
 	}
 
@@ -196,7 +196,7 @@ static void __init kasan_early_clear_p4d(pgd_t *pgdp,
 	if (!pgtable_l5_enabled) {
 		p4dp = (p4d_t *)pgdp;
 	} else {
-		base_p4d = pt_ops.get_p4d_virt(pfn_to_phys(_pgd_pfn(pgdp_get(pgdp))));
+		base_p4d = pt_ops.get_p4d_virt(pfn_to_phys(pgd_pfn(pgdp_get(pgdp))));
 		p4dp = base_p4d + p4d_index(vaddr);
 	}
 
@@ -242,7 +242,7 @@ static void __init kasan_early_populate_pud(p4d_t *p4dp,
 	if (!pgtable_l4_enabled) {
 		pudp = (pud_t *)p4dp;
 	} else {
-		base_pud = pt_ops.get_pud_virt(pfn_to_phys(_p4d_pfn(p4dp_get(p4dp))));
+		base_pud = pt_ops.get_pud_virt(pfn_to_phys(p4d_pfn(p4dp_get(p4dp))));
 		pudp = base_pud + pud_index(vaddr);
 	}
 
@@ -280,7 +280,7 @@ static void __init kasan_early_populate_p4d(pgd_t *pgdp,
 	if (!pgtable_l5_enabled) {
 		p4dp = (p4d_t *)pgdp;
 	} else {
-		base_p4d = pt_ops.get_p4d_virt(pfn_to_phys(_pgd_pfn(pgdp_get(pgdp))));
+		base_p4d = pt_ops.get_p4d_virt(pfn_to_phys(pgd_pfn(pgdp_get(pgdp))));
 		p4dp = base_p4d + p4d_index(vaddr);
 	}
 
diff --git a/arch/riscv/mm/memory-alias.S b/arch/riscv/mm/memory-alias.S
new file mode 100644
index 000000000000..df2e8cc3f69c
--- /dev/null
+++ b/arch/riscv/mm/memory-alias.S
@@ -0,0 +1,101 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (C) 2024 SiFive
+ */
+
+#include <linux/bits.h>
+#include <linux/linkage.h>
+#include <asm/asm.h>
+#include <asm/pgtable.h>
+
+#define CACHED_BASE_OFFSET	(0 * RISCV_SZPTR)
+#define NONCACHED_BASE_OFFSET	(1 * RISCV_SZPTR)
+#define SIZE_OFFSET		(2 * RISCV_SZPTR)
+
+#define SIZEOF_PAIR		(4 * RISCV_SZPTR)
+
+SYM_CODE_START(riscv_fixup_memory_alias)
+	addi	sp, sp, -4 * SZREG
+	REG_S	t2, (0 * SZREG)(sp)
+	REG_S	t3, (1 * SZREG)(sp)
+	REG_S	t4, (2 * SZREG)(sp)
+#ifdef CONFIG_RISCV_ISA_SVNAPOT
+	REG_S	t5, (3 * SZREG)(sp)
+
+	/* Save and mask off _PAGE_NAPOT if present. */
+	li	t5, _PAGE_NAPOT
+	and	t5, t1, t5
+	xor	t1, t1, t5
+#endif
+
+	lla	t2, memory_alias_pairs
+.Lfixup_loop:
+	REG_L	t3, SIZE_OFFSET(t2)
+	beqz	t3, .Lfixup_end
+	REG_L	t4, CACHED_BASE_OFFSET(t2)
+	sub	t4, t1, t4
+	bltu	t4, t3, .Lfixup_found
+	addi	t2, t2, SIZEOF_PAIR
+	j	.Lfixup_loop
+
+.Lfixup_found:
+	REG_L	t3, NONCACHED_BASE_OFFSET(t2)
+	add	t1, t3, t4
+
+.Lfixup_end:
+#ifdef CONFIG_RISCV_ISA_SVNAPOT
+	xor	t1, t1, t5
+
+	REG_L	t5, (3 * SZREG)(sp)
+#endif
+	REG_L	t4, (2 * SZREG)(sp)
+	REG_L	t3, (1 * SZREG)(sp)
+	REG_L	t2, (0 * SZREG)(sp)
+	addi	sp, sp, 4 * SZREG
+	jr	t0
+SYM_CODE_END(riscv_fixup_memory_alias)
+
+SYM_CODE_START(riscv_unfix_memory_alias)
+	addi	sp, sp, -4 * SZREG
+	REG_S	t2, (0 * SZREG)(sp)
+	REG_S	t3, (1 * SZREG)(sp)
+	REG_S	t4, (2 * SZREG)(sp)
+#ifdef CONFIG_RISCV_ISA_SVNAPOT
+	REG_S	t5, (3 * SZREG)(sp)
+
+	/* Save and mask off _PAGE_NAPOT if present. */
+	li	t5, _PAGE_NAPOT
+	and	t5, t1, t5
+	xor	t1, t1, t5
+#endif
+
+	lla	t2, memory_alias_pairs
+.Lunfix_loop:
+	REG_L	t3, SIZE_OFFSET(t2)
+	beqz	t3, .Lunfix_end
+	REG_L	t4, NONCACHED_BASE_OFFSET(t2)
+	sub	t4, t1, t4
+	bltu	t4, t3, .Lunfix_found
+	addi	t2, t2, SIZEOF_PAIR
+	j	.Lunfix_loop
+
+.Lunfix_found:
+	REG_L	t3, CACHED_BASE_OFFSET(t2)
+	add	t1, t3, t4
+
+	/* PFN was in the noncached alias, so mark it as such. */
+	li	t2, _PAGE_NOCACHE
+	or	t1, t1, t2
+
+.Lunfix_end:
+#ifdef CONFIG_RISCV_ISA_SVNAPOT
+	xor	t1, t1, t5
+
+	REG_L	t5, (3 * SZREG)(sp)
+#endif
+	REG_L	t4, (2 * SZREG)(sp)
+	REG_L	t3, (1 * SZREG)(sp)
+	REG_L	t2, (0 * SZREG)(sp)
+	addi	sp, sp, 4 * SZREG
+	jr	t0
+SYM_CODE_END(riscv_unfix_memory_alias)
diff --git a/arch/riscv/mm/pageattr.c b/arch/riscv/mm/pageattr.c
index d815448758a1..c73d46ff8730 100644
--- a/arch/riscv/mm/pageattr.c
+++ b/arch/riscv/mm/pageattr.c
@@ -109,9 +109,8 @@ static int __split_linear_mapping_pmd(pud_t *pudp,
 			continue;
 
 		if (pmd_leaf(pmdp_get(pmdp))) {
+			pte_t pte = pmd_pte(pmdp_get(pmdp));
 			struct page *pte_page;
-			unsigned long pfn = _pmd_pfn(pmdp_get(pmdp));
-			pgprot_t prot = __pgprot(pmd_val(pmdp_get(pmdp)) & ~_PAGE_PFN_MASK);
 			pte_t *ptep_new;
 			int i;
 
@@ -121,7 +120,8 @@ static int __split_linear_mapping_pmd(pud_t *pudp,
 
 			ptep_new = (pte_t *)page_address(pte_page);
 			for (i = 0; i < PTRS_PER_PTE; ++i, ++ptep_new)
-				set_pte(ptep_new, pfn_pte(pfn + i, prot));
+				set_pte(ptep_new,
+					__pte(pte_val(pte) + (i << _PAGE_PFN_SHIFT)));
 
 			smp_wmb();
 
@@ -149,9 +149,8 @@ static int __split_linear_mapping_pud(p4d_t *p4dp,
 			continue;
 
 		if (pud_leaf(pudp_get(pudp))) {
+			pmd_t pmd = __pmd(pud_val(pudp_get(pudp)));
 			struct page *pmd_page;
-			unsigned long pfn = _pud_pfn(pudp_get(pudp));
-			pgprot_t prot = __pgprot(pud_val(pudp_get(pudp)) & ~_PAGE_PFN_MASK);
 			pmd_t *pmdp_new;
 			int i;
 
@@ -162,7 +161,8 @@ static int __split_linear_mapping_pud(p4d_t *p4dp,
 			pmdp_new = (pmd_t *)page_address(pmd_page);
 			for (i = 0; i < PTRS_PER_PMD; ++i, ++pmdp_new)
 				set_pmd(pmdp_new,
-					pfn_pmd(pfn + ((i * PMD_SIZE) >> PAGE_SHIFT), prot));
+					__pmd(pmd_val(pmd) +
+					      (i << (PMD_SHIFT - PAGE_SHIFT + _PAGE_PFN_SHIFT))));
 
 			smp_wmb();
 
@@ -198,9 +198,8 @@ static int __split_linear_mapping_p4d(pgd_t *pgdp,
 			continue;
 
 		if (p4d_leaf(p4dp_get(p4dp))) {
+			pud_t pud = __pud(p4d_val(p4dp_get(p4dp)));
 			struct page *pud_page;
-			unsigned long pfn = _p4d_pfn(p4dp_get(p4dp));
-			pgprot_t prot = __pgprot(p4d_val(p4dp_get(p4dp)) & ~_PAGE_PFN_MASK);
 			pud_t *pudp_new;
 			int i;
 
@@ -215,7 +214,8 @@ static int __split_linear_mapping_p4d(pgd_t *pgdp,
 			pudp_new = (pud_t *)page_address(pud_page);
 			for (i = 0; i < PTRS_PER_PUD; ++i, ++pudp_new)
 				set_pud(pudp_new,
-					pfn_pud(pfn + ((i * PUD_SIZE) >> PAGE_SHIFT), prot));
+					__pud(pud_val(pud) +
+					      (i << (PUD_SHIFT - PAGE_SHIFT + _PAGE_PFN_SHIFT))));
 
 			/*
 			 * Make sure the pud filling is not reordered with the
diff --git a/arch/riscv/mm/pgtable.c b/arch/riscv/mm/pgtable.c
index 8b6c0a112a8d..cddeaa66fec7 100644
--- a/arch/riscv/mm/pgtable.c
+++ b/arch/riscv/mm/pgtable.c
@@ -1,8 +1,12 @@
 // SPDX-License-Identifier: GPL-2.0
 
 #include <asm/pgalloc.h>
+#include <dt-bindings/riscv/physical-memory.h>
+#include <linux/bitfield.h>
 #include <linux/gfp.h>
 #include <linux/kernel.h>
+#include <linux/memblock.h>
+#include <linux/of.h>
 #include <linux/pgtable.h>
 
 int ptep_set_access_flags(struct vm_area_struct *vma,
@@ -165,3 +169,90 @@ pud_t pudp_invalidate(struct vm_area_struct *vma, unsigned long address,
 	return old;
 }
 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */
+
+#ifdef CONFIG_RISCV_ISA_SVPBMT
+struct memory_alias_pair {
+	unsigned long cached_base;
+	unsigned long noncached_base;
+	unsigned long size;
+	int index;
+} memory_alias_pairs[5];
+
+bool __init riscv_have_memory_alias(void)
+{
+	return memory_alias_pairs[0].size;
+}
+
+void __init riscv_init_memory_alias(void)
+{
+	int na = of_n_addr_cells(of_root);
+	int ns = of_n_size_cells(of_root);
+	int nc = na + ns + 2;
+	const __be32 *prop;
+	int pairs = 0;
+	int len;
+
+	prop = of_get_property(of_root, "riscv,physical-memory-regions", &len);
+	if (!prop)
+		return;
+
+	len /= sizeof(__be32);
+	for (int i = 0; len >= nc; i++, prop += nc, len -= nc) {
+		unsigned long base = of_read_ulong(prop, na);
+		unsigned long size = of_read_ulong(prop + na, ns);
+		unsigned long flags = be32_to_cpup(prop + na + ns);
+		struct memory_alias_pair *pair;
+		int alias;
+
+		/* We only care about non-coherent memory. */
+		if ((flags & PMA_ORDER_MASK) != PMA_ORDER_MEMORY || (flags & PMA_COHERENT))
+			continue;
+
+		/* The cacheable alias must be usable memory. */
+		if ((flags & PMA_CACHEABLE) &&
+		    !memblock_overlaps_region(&memblock.memory, base, size))
+			continue;
+
+		alias = FIELD_GET(PMR_ALIAS_MASK, flags);
+		if (alias) {
+			pair = NULL;
+			for (int j = 0; j < pairs; j++) {
+				if (alias == memory_alias_pairs[j].index) {
+					pair = &memory_alias_pairs[j];
+					break;
+				}
+			}
+			if (!pair)
+				continue;
+		} else {
+			/* Leave room for the null sentinel. */
+			if (pairs == ARRAY_SIZE(memory_alias_pairs) - 1)
+				continue;
+			pair = &memory_alias_pairs[pairs++];
+			pair->index = i;
+		}
+
+		/* Align the address and size with the page table PFN field. */
+		base >>= PAGE_SHIFT - _PAGE_PFN_SHIFT;
+		size >>= PAGE_SHIFT - _PAGE_PFN_SHIFT;
+
+		if (flags & PMA_CACHEABLE)
+			pair->cached_base = base;
+		else
+			pair->noncached_base = base;
+		pair->size = min_not_zero(pair->size, size);
+	}
+
+	/* Remove any unmatched pairs. */
+	for (int i = 0; i < pairs; i++) {
+		struct memory_alias_pair *pair = &memory_alias_pairs[i];
+
+		if (pair->cached_base && pair->noncached_base && pair->size)
+			continue;
+
+		for (int j = i + 1; j < pairs; j++)
+			memory_alias_pairs[j - 1] = memory_alias_pairs[j];
+		memory_alias_pairs[--pairs].size = 0;
+	}
+}
+#endif /* CONFIG_RISCV_ISA_SVPBMT */
diff --git a/arch/riscv/mm/ptdump.c b/arch/riscv/mm/ptdump.c
index 3b51690cc876..173228401ceb 100644
--- a/arch/riscv/mm/ptdump.c
+++ b/arch/riscv/mm/ptdump.c
@@ -134,12 +134,14 @@ struct prot_bits {
 
 static const struct prot_bits pte_bits[] = {
 	{
-#ifdef CONFIG_64BIT
+#ifdef CONFIG_RISCV_ISA_SVNAPOT
 		.mask = _PAGE_NAPOT,
 		.set = "N",
 		.clear = ".",
 	}, {
-		.mask = _PAGE_MTMASK_SVPBMT,
+#endif
+#ifdef CONFIG_RISCV_ISA_SVPBMT
+		.mask = _PAGE_MTMASK,
 		.set = "MT(%s)",
 		.clear = "  ..  ",
 	}, {
@@ -214,11 +216,11 @@ static void dump_prot(struct pg_state *st)
 		if (val) {
 			if (pte_bits[i].mask == _PAGE_SOFT)
 				sprintf(s, pte_bits[i].set, val >> 8);
-#ifdef CONFIG_64BIT
-			else if (pte_bits[i].mask == _PAGE_MTMASK_SVPBMT) {
-				if (val == _PAGE_NOCACHE_SVPBMT)
+#ifdef CONFIG_RISCV_ISA_SVPBMT
+			else if (pte_bits[i].mask == _PAGE_MTMASK) {
+				if (val == _PAGE_NOCACHE)
 					sprintf(s, pte_bits[i].set, "NC");
-				else if (val == _PAGE_IO_SVPBMT)
+				else if (val == _PAGE_IO)
 					sprintf(s, pte_bits[i].set, "IO");
 				else
 					sprintf(s, pte_bits[i].set, "??");
@@ -279,9 +281,12 @@ static void note_page(struct ptdump_state *pt_st, unsigned long addr,
 		      int level, u64 val)
 {
 	struct pg_state *st = container_of(pt_st, struct pg_state, ptdump);
-	u64 pa = PFN_PHYS(pte_pfn(__pte(val)));
 	u64 prot = 0;
+	u64 pa;
+
+	ALT_UNFIX_MT(val);
 
+	pa = PFN_PHYS(pte_pfn(__pte(val)));
 	if (level >= 0)
 		prot = val & pg_level[level].mask;
 
diff --git a/drivers/ata/Kconfig b/drivers/ata/Kconfig
index 120a2b7067fc..695229f95338 100644
--- a/drivers/ata/Kconfig
+++ b/drivers/ata/Kconfig
@@ -231,6 +231,15 @@ config AHCI_CEVA
 
 	  If unsure, say N.
 
+config AHCI_ESWIN
+	tristate "Eswin AHCI SATA support"
+	select SATA_HOST
+	help
+	  This option enables support for Eswin AHCI Serial ATA
+	  controllers.
+
+	  If unsure, say N.
+
 config AHCI_MTK
 	tristate "MediaTek AHCI SATA support"
 	depends on ARCH_MEDIATEK || COMPILE_TEST
diff --git a/drivers/ata/Makefile b/drivers/ata/Makefile
index 20e6645ab737..515e62a23ae7 100644
--- a/drivers/ata/Makefile
+++ b/drivers/ata/Makefile
@@ -18,6 +18,7 @@ obj-$(CONFIG_AHCI_CEVA)		+= ahci_ceva.o libahci.o libahci_platform.o
 obj-$(CONFIG_AHCI_DA850)	+= ahci_da850.o libahci.o libahci_platform.o
 obj-$(CONFIG_AHCI_DM816)	+= ahci_dm816.o libahci.o libahci_platform.o
 obj-$(CONFIG_AHCI_DWC)		+= ahci_dwc.o libahci.o libahci_platform.o
+obj-$(CONFIG_AHCI_ESWIN)	+= ahci_eswin.o libahci.o libahci_platform.o
 obj-$(CONFIG_AHCI_IMX)		+= ahci_imx.o libahci.o libahci_platform.o
 obj-$(CONFIG_AHCI_MTK)		+= ahci_mtk.o libahci.o libahci_platform.o
 obj-$(CONFIG_AHCI_MVEBU)	+= ahci_mvebu.o libahci.o libahci_platform.o
diff --git a/drivers/ata/ahci_eswin.c b/drivers/ata/ahci_eswin.c
new file mode 100644
index 000000000000..0c534d21b87d
--- /dev/null
+++ b/drivers/ata/ahci_eswin.c
@@ -0,0 +1,291 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * ESWIN AHCI SATA Driver
+ *
+ * Copyright 2024, Beijing ESWIN Computing Technology Co., Ltd.. All rights reserved.
+ * SPDX-License-Identifier: GPL-2.0
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, version 2.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <https://www.gnu.org/licenses/>.
+ *
+ * Authors: Yulin Lu <luyulin@eswincomputing.com>
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/pm.h>
+#include <linux/device.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+#include <linux/libata.h>
+#include <linux/ahci_platform.h>
+#include <linux/acpi.h>
+#include <linux/pci_ids.h>
+#include  <linux/mfd/syscon.h>
+#include <linux/bitfield.h>
+#include <linux/regmap.h>
+#include <linux/reset.h>
+#include "ahci.h"
+
+#define DRV_NAME "ahci"
+
+#define SATA_REF_CTRL1                0x338
+#define SATA_PHY_CTRL0                0x328
+#define SATA_PHY_CTRL1                0x32c
+#define SATA_LOS_IDEN                 0x33c
+#define SATA_AXI_LP_CTRL              0x308
+#define SATA_REG_CTRL                 0x334
+#define SATA_MPLL_CTRL                0x320
+#define SATA_RESET_CTRL               0x340
+#define SATA_RESET_CTRL_ASSERT        0x3
+#define SATA_RESET_CTRL_DEASSERT      0x0
+#define SATA_PHY_RESET                BIT(0)
+#define SATA_P0_RESET                 BIT(1)
+#define SATA_LOS_LEVEL                0x9
+#define SATA_LOS_BIAS                 (0x02 << 16)
+#define SATA_REF_REPEATCLK_EN         BIT(0)
+#define SATA_REF_USE_PAD              BIT(20)
+#define SATA_P0_AMPLITUDE_GEN1        0x42
+#define SATA_P0_AMPLITUDE_GEN2        (0x46 << 8)
+#define SATA_P0_AMPLITUDE_GEN3        (0x73 << 16)
+#define SATA_P0_PHY_TX_PREEMPH_GEN1   0x05
+#define SATA_P0_PHY_TX_PREEMPH_GEN2   (0x05 << 8)
+#define SATA_P0_PHY_TX_PREEMPH_GEN3   (0x23 << 16)
+#define SATA_MPLL_MULTIPLIER          (0x3c << 16)
+#define SATA_M_CSYSREQ                BIT(0)
+#define SATA_S_CSYSREQ                BIT(16)
+#define HSPDME_RST_CTRL               0x41C
+#define SW_HSP_SATA_ARSTN             BIT(27)
+#define SW_SATA_RSTN                  (0xf << 9)
+
+static const struct ata_port_info ahci_port_info = {
+    .flags		= AHCI_FLAG_COMMON,
+    .pio_mask	= ATA_PIO4,
+    .udma_mask	= ATA_UDMA6,
+    .port_ops	= &ahci_platform_ops,
+};
+
+static const struct ata_port_info ahci_port_info_nolpm = {
+    .flags		= AHCI_FLAG_COMMON | ATA_FLAG_NO_LPM,
+    .pio_mask	= ATA_PIO4,
+    .udma_mask	= ATA_UDMA6,
+    .port_ops	= &ahci_platform_ops,
+};
+
+static struct scsi_host_template ahci_platform_sht = {
+    AHCI_SHT(DRV_NAME),
+};
+
+static int eswin_sata_init(struct device *dev)
+{
+    struct regmap *regmap;
+    regmap = syscon_regmap_lookup_by_phandle(dev->of_node, "eswin,hsp_sp_csr");
+    if (IS_ERR(regmap)) {
+        dev_dbg(dev, "No hsp_sp_csr phandle specified\n");
+        return -1;
+    }
+    regmap_write(regmap, SATA_REF_CTRL1, 0x1);
+    regmap_write(regmap, SATA_PHY_CTRL0, (SATA_P0_AMPLITUDE_GEN1|SATA_P0_AMPLITUDE_GEN2|SATA_P0_AMPLITUDE_GEN3));
+    regmap_write(regmap, SATA_PHY_CTRL1, (SATA_P0_PHY_TX_PREEMPH_GEN1|SATA_P0_PHY_TX_PREEMPH_GEN2|SATA_P0_PHY_TX_PREEMPH_GEN3));
+    regmap_write(regmap, SATA_LOS_IDEN, SATA_LOS_LEVEL|SATA_LOS_BIAS);
+    regmap_write(regmap, SATA_AXI_LP_CTRL, (SATA_M_CSYSREQ|SATA_S_CSYSREQ));
+    regmap_write(regmap, SATA_REG_CTRL, (SATA_REF_REPEATCLK_EN|SATA_REF_USE_PAD));
+    regmap_write(regmap, SATA_MPLL_CTRL, SATA_MPLL_MULTIPLIER);
+    regmap_write(regmap, SATA_RESET_CTRL, 0x0);
+
+    return 0;
+}
+
+static int eswin_reset(struct device *dev)
+{
+    struct reset_control *asic0_rst;
+    struct reset_control *oob_rst;
+    struct reset_control *pmalive_rst;
+    struct reset_control *rbc_rst;
+    struct reset_control *apb_rst;
+    int rc;
+
+    asic0_rst = devm_reset_control_get_shared(dev, "asic0");
+    if (IS_ERR_OR_NULL(asic0_rst)) {
+        dev_err(dev, "Failed to asic0_rst handle\n");
+        return -EFAULT;
+    }
+    oob_rst = devm_reset_control_get_shared(dev, "oob");
+    if (IS_ERR_OR_NULL(oob_rst)) {
+        dev_err(dev, "Failed to oob_rst handle\n");
+        return -EFAULT;
+    }
+    pmalive_rst = devm_reset_control_get_shared(dev, "pmalive");
+    if (IS_ERR_OR_NULL(pmalive_rst)) {
+        dev_err(dev, "Failed to pmalive_rst handle\n");
+        return -EFAULT;
+    }
+    rbc_rst = devm_reset_control_get_shared(dev, "rbc");
+    if (IS_ERR_OR_NULL(rbc_rst)) {
+        dev_err(dev, "Failed to rbc_rst handle\n");
+        return -EFAULT;
+    }
+    apb_rst = devm_reset_control_get_shared(dev, "apb");
+    if (IS_ERR_OR_NULL(apb_rst)) {
+        dev_err(dev, "Failed to apb_rst handle\n");
+        return -EFAULT;
+    }
+
+    if (asic0_rst) {
+        rc = reset_control_deassert(asic0_rst);
+        WARN_ON(0 != rc);
+    }
+    if (oob_rst) {
+        rc = reset_control_deassert(oob_rst);
+        WARN_ON(0 != rc);
+    }
+    if (pmalive_rst) {
+        rc = reset_control_deassert(pmalive_rst);
+        WARN_ON(0 != rc);
+    }
+    if (rbc_rst) {
+        rc = reset_control_deassert(rbc_rst);
+        WARN_ON(0 != rc);
+    }
+    if (apb_rst) {
+        rc = reset_control_deassert(apb_rst);
+        WARN_ON(0 != rc);
+    }
+
+    return 0;
+}
+
+
+static int eswin_unreset(struct device *dev)
+{
+    struct reset_control *asic0_rst;
+    struct reset_control *oob_rst;
+    struct reset_control *pmalive_rst;
+    struct reset_control *rbc_rst;
+    int rc;
+
+    asic0_rst = devm_reset_control_get_shared(dev, "asic0");
+    if (IS_ERR_OR_NULL(asic0_rst)) {
+        dev_err(dev, "Failed to asic0_rst handle\n");
+        return -EFAULT;
+    }
+    oob_rst = devm_reset_control_get_shared(dev, "oob");
+    if (IS_ERR_OR_NULL(oob_rst)) {
+        dev_err(dev, "Failed to oob_rst handle\n");
+        return -EFAULT;
+    }
+    pmalive_rst = devm_reset_control_get_shared(dev, "pmalive");
+    if (IS_ERR_OR_NULL(pmalive_rst)) {
+        dev_err(dev, "Failed to pmalive_rst handle\n");
+        return -EFAULT;
+    }
+    rbc_rst = devm_reset_control_get_shared(dev, "rbc");
+    if (IS_ERR_OR_NULL(rbc_rst)) {
+        dev_err(dev, "Failed to rbc_rst handle\n");
+        return -EFAULT;
+    }
+    if (asic0_rst) {
+        rc = reset_control_assert(asic0_rst);
+        WARN_ON(0 != rc);
+    }
+    if (oob_rst) {
+        rc = reset_control_assert(oob_rst);
+        WARN_ON(0 != rc);
+    }
+    if (pmalive_rst) {
+        rc = reset_control_assert(pmalive_rst);
+        WARN_ON(0 != rc);
+    }
+    if (rbc_rst) {
+        rc = reset_control_assert(rbc_rst);
+        WARN_ON(0 != rc);
+    }
+
+return 0;
+}
+
+static int ahci_probe(struct platform_device *pdev)
+{
+    struct device *dev = &pdev->dev;
+    struct ahci_host_priv *hpriv;
+    const struct ata_port_info *port;
+    int rc;
+
+    hpriv = ahci_platform_get_resources(pdev,
+                        0);
+    if (IS_ERR(hpriv))
+        return PTR_ERR(hpriv);
+
+    rc = eswin_reset(dev);
+    if (rc)
+        return rc;
+    eswin_sata_init(dev);
+    rc = dma_set_mask_and_coherent(dev,DMA_BIT_MASK(64));
+
+    if (of_device_is_compatible(dev->of_node, "hisilicon,hisi-ahci"))
+        hpriv->flags |= AHCI_HFLAG_NO_FBS | AHCI_HFLAG_NO_NCQ;
+
+    port = acpi_device_get_match_data(dev);
+    if (!port){
+        port = &ahci_port_info;
+    }
+    rc = ahci_platform_init_host(pdev, hpriv, port,
+                &ahci_platform_sht);
+    if (rc)
+        goto disable_resources;
+
+    return 0;
+
+disable_resources:
+    ahci_platform_disable_resources(hpriv);
+    return rc;
+}
+
+static void ahci_remove(struct platform_device *pdev)
+{
+    eswin_unreset(&pdev->dev);
+
+    ata_platform_remove_one(pdev);
+}
+
+static SIMPLE_DEV_PM_OPS(ahci_pm_ops, ahci_platform_suspend,
+            ahci_platform_resume);
+
+static const struct of_device_id ahci_of_match[] = {
+    { .compatible = "snps,eswin-ahci", },
+    {},
+};
+MODULE_DEVICE_TABLE(of, ahci_of_match);
+
+static const struct acpi_device_id ahci_acpi_match[] = {
+    { "APMC0D33", (unsigned long)&ahci_port_info_nolpm },
+    { ACPI_DEVICE_CLASS(PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff) },
+    {},
+};
+MODULE_DEVICE_TABLE(acpi, ahci_acpi_match);
+
+static struct platform_driver ahci_driver = {
+    .probe = ahci_probe,
+    .remove = ahci_remove,
+    .shutdown = ahci_platform_shutdown,
+    .driver = {
+        .name = DRV_NAME,
+        .of_match_table = ahci_of_match,
+        .acpi_match_table = ahci_acpi_match,
+        .pm = &ahci_pm_ops,
+    },
+};
+module_platform_driver(ahci_driver);
+
+MODULE_DESCRIPTION("ESWIN AHCI SATA driver");
+MODULE_AUTHOR("Lu Yulin <luyulin@eswincomputing.com>");
+MODULE_LICENSE("GPL");
diff --git a/drivers/cache/Kconfig b/drivers/cache/Kconfig
index db51386c663a..1de3911c82b4 100644
--- a/drivers/cache/Kconfig
+++ b/drivers/cache/Kconfig
@@ -11,6 +11,7 @@ config AX45MP_L2_CACHE
 config SIFIVE_CCACHE
 	bool "Sifive Composable Cache controller"
 	depends on ARCH_SIFIVE || ARCH_STARFIVE
+	select RISCV_NONSTANDARD_CACHE_OPS
 	help
 	  Support for the composable cache controller on SiFive platforms.
 
diff --git a/drivers/cache/sifive_ccache.c b/drivers/cache/sifive_ccache.c
index e1a283805ea7..fb57e6028075 100644
--- a/drivers/cache/sifive_ccache.c
+++ b/drivers/cache/sifive_ccache.c
@@ -125,6 +125,8 @@ static const struct of_device_id sifive_ccache_ids[] = {
 	{ .compatible = "starfive,jh7100-ccache",
 	  .data = (void *)(QUIRK_NONSTANDARD_CACHE_OPS | QUIRK_BROKEN_DATA_UNCORR) },
 	{ .compatible = "sifive,ccache0" },
+	{ .compatible = "sifive,eic7700",
+	  .data = (void *)(QUIRK_NONSTANDARD_CACHE_OPS) },
 	{ /* end of table */ }
 };
 
@@ -170,6 +172,16 @@ static const struct riscv_nonstd_cache_ops ccache_mgmt_ops __initconst = {
 };
 #endif /* CONFIG_RISCV_NONSTANDARD_CACHE_OPS */
 
+#ifdef CONFIG_SOC_SIFIVE_EIC7700
+static void ccache_largest_way_enable(void)
+{
+	unsigned int config, ways;
+	config = readl(ccache_base + SIFIVE_CCACHE_CONFIG);
+	ways = (config >> 8) & 0xff;
+	writel(ways-1, ccache_base + SIFIVE_CCACHE_WAYENABLE);
+}
+#endif /* CONFIG_SOC_SIFIVE_EIC7700 */
+
 static int ccache_largest_wayenabled(void)
 {
 	return readl(ccache_base + SIFIVE_CCACHE_WAYENABLE) & 0xFF;
@@ -317,6 +329,11 @@ static int __init sifive_ccache_init(void)
 		goto err_unmap;
 	}
 
+#ifdef CONFIG_SOC_SIFIVE_EIC7700
+	/* Enable all the cache ways */
+	ccache_largest_way_enable();
+#endif
+
 #ifdef CONFIG_RISCV_NONSTANDARD_CACHE_OPS
 	if (quirks & QUIRK_NONSTANDARD_CACHE_OPS) {
 		riscv_cbom_block_size = SIFIVE_CCACHE_LINE_SIZE;
diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
index 19c1ed280fd7..cf52d705206d 100644
--- a/drivers/clk/Kconfig
+++ b/drivers/clk/Kconfig
@@ -497,6 +497,7 @@ source "drivers/clk/actions/Kconfig"
 source "drivers/clk/analogbits/Kconfig"
 source "drivers/clk/baikal-t1/Kconfig"
 source "drivers/clk/bcm/Kconfig"
+source "drivers/clk/eswin/Kconfig"
 source "drivers/clk/hisilicon/Kconfig"
 source "drivers/clk/imgtec/Kconfig"
 source "drivers/clk/imx/Kconfig"
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index 42867cd37c33..d2b4b74936b7 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -118,6 +118,7 @@ obj-$(CONFIG_CLK_BAIKAL_T1)		+= baikal-t1/
 obj-y					+= bcm/
 obj-$(CONFIG_ARCH_BERLIN)		+= berlin/
 obj-$(CONFIG_ARCH_DAVINCI)		+= davinci/
+obj-$(CONFIG_SOC_SIFIVE_EIC7700)	+= eswin/
 obj-$(CONFIG_ARCH_HISI)			+= hisilicon/
 obj-y					+= imgtec/
 obj-y					+= imx/
diff --git a/drivers/clk/eswin/Kconfig b/drivers/clk/eswin/Kconfig
new file mode 100644
index 000000000000..cc906e4b2343
--- /dev/null
+++ b/drivers/clk/eswin/Kconfig
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+config COMMON_CLK_EIC7700
+	bool "EIC7700 Clock Driver"
+	help
+	  Build the Eswin EIC7700 clock driver based on the common clock framework.
diff --git a/drivers/clk/eswin/Makefile b/drivers/clk/eswin/Makefile
new file mode 100644
index 000000000000..a3139e34ee22
--- /dev/null
+++ b/drivers/clk/eswin/Makefile
@@ -0,0 +1,8 @@
+# SPDX-License-Identifier: GPL-2.0
+#
+# Eswin Clock specific Makefile
+#
+
+obj-y	+= clk.o
+
+obj-$(CONFIG_COMMON_CLK_EIC7700)	+= clk-eic7700.o
diff --git a/drivers/clk/eswin/clk-eic7700.c b/drivers/clk/eswin/clk-eic7700.c
new file mode 100644
index 000000000000..80a73eca54ec
--- /dev/null
+++ b/drivers/clk/eswin/clk-eic7700.c
@@ -0,0 +1,1189 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * ESWIN Clk Provider Driver
+ *
+ * Copyright 2024, Beijing ESWIN Computing Technology Co., Ltd.. All rights reserved.
+ * SPDX-License-Identifier: GPL-2.0
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, version 2.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <https://www.gnu.org/licenses/>.
+ *
+ * Authors: HuangYiFeng<huangyifeng@eswincomputing.com>
+ */
+
+#include <linux/kernel.h>
+#include <linux/clk-provider.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+
+#include <dt-bindings/reset/eic7700-syscrg.h>
+#include <dt-bindings/clock/eic7700-clock.h>
+
+#include "clk.h"
+
+/* clock parent list */
+static const char *const mux_u_cpu_root_3mux1_gfree_p[] = {"clk_pll_cpu", "clk_clk_u84_core_lp", "fixed_rate_clk_xtal_24m"};
+static u32  mux_u_cpu_root_3mux1_gfree_p_table[] = {0x000000, 0x000001, 0x000002};
+
+static const char *const mux_u_cpu_aclk_2mux1_gfree_p[] = {"fixed_factor_u_cpu_div2", "mux_u_cpu_root_3mux1_gfree"};
+
+static const char *const dsp_aclk_root_2mux1_gfree_mux_p[] = {"fixed_rate_clk_spll2_fout1", "fixed_rate_clk_spll0_fout1"};
+
+static const char *const d2d_aclk_root_2mux1_gfree_mux_p[] = { "fixed_rate_clk_spll2_fout1", "fixed_rate_clk_spll0_fout1", };
+
+static const char *const ddr_aclk_root_2mux1_gfree_mux_p[] = { "fixed_rate_clk_spll2_fout1", "fixed_rate_clk_spll0_fout1", };
+
+static const char *const mshcore_root_3mux1_0_mux_p[] = {"fixed_rate_clk_spll0_fout3", "fixed_rate_clk_spll2_fout3", "fixed_rate_clk_xtal_24m"};
+static u32  mshcore_root_3mux1_0_mux_p_table[] = {0x000000, 0x000001, 0x100000};
+
+static const char *const mshcore_root_3mux1_1_mux_p[] = {"fixed_rate_clk_spll0_fout3", "fixed_rate_clk_spll2_fout3", "fixed_rate_clk_xtal_24m"};
+static u32  mshcore_root_3mux1_1_mux_p_table[] = {0x000000, 0x000001, 0x100000};
+
+static const char *const mshcore_root_3mux1_2_mux_p[] = {"fixed_rate_clk_spll0_fout3", "fixed_rate_clk_spll2_fout3", "fixed_rate_clk_xtal_24m"};
+static u32  mshcore_root_3mux1_2_mux_p_table[] = {0x000000, 0x000001, 0x100000};
+
+static const char *const npu_llclk_3mux1_gfree_mux_p[] = { "clk_clk_npu_llc_src0", "clk_clk_npu_llc_src1", "fixed_rate_clk_vpll_fout1"};
+static u32  npu_llclk_3mux1_gfree_mux_p_table[] = {0x000000, 0x000001, 0x000002};
+
+static const char *const npu_core_3mux1_gfree_mux_p[] = { "fixed_rate_clk_spll1_fout1", "fixed_rate_clk_vpll_fout1", "fixed_rate_clk_spll2_fout2"};
+static u32  npu_core_3mux1_gfree_mux_p_table[] = {0x000000, 0x000001, 0x000002};
+
+static const char *const npu_e31_3mux1_gfree_mux_p[] = { "fixed_rate_clk_spll1_fout1", "fixed_rate_clk_vpll_fout1", "fixed_rate_clk_spll2_fout2"};
+static u32  npu_e31_3mux1_gfree_mux_p_table[] = {0x000000, 0x000100, 0x000200};
+
+static const char *const vi_aclk_root_2mux1_gfree_mux_p[] = { "fixed_rate_clk_spll0_fout1", "fixed_rate_clk_spll2_fout1"};
+
+static const char *const mux_u_vi_dw_root_2mux1_p[] = { "fixed_rate_clk_vpll_fout1", "fixed_rate_clk_spll0_fout1"};
+
+static const char *const mux_u_vi_dvp_root_2mux1_gfree_p[] = { "fixed_rate_clk_vpll_fout1", "fixed_rate_clk_spll0_fout1"};
+
+static const char *const mux_u_vi_dig_isp_root_2mux1_gfree_p[] = { "fixed_rate_clk_vpll_fout1", "fixed_rate_clk_spll0_fout1"};
+
+static const char *const mux_u_vo_aclk_root_2mux1_gfree_p[] = { "fixed_rate_clk_spll0_fout1", "fixed_rate_clk_spll2_fout1"};
+
+static const char *const mux_u_vo_pixel_root_2mux1_p[] = { "fixed_rate_clk_vpll_fout1", "fixed_rate_clk_spll2_fout2"};
+
+static const char *const mux_u_vcdec_root_2mux1_gfree_p[] = { "fixed_rate_clk_spll0_fout1", "fixed_rate_clk_spll2_fout1"};
+
+static const char *const mux_u_vcaclk_root_2mux1_gfree_p[] = { "fixed_rate_clk_spll0_fout1", "fixed_rate_clk_spll2_fout1"};
+
+static const char *const mux_u_syscfg_clk_root_2mux1_gfree_p[] = { "divder_u_sys_cfg_div_dynm", "fixed_rate_clk_xtal_24m"};
+
+static const char *const mux_u_bootspi_clk_2mux1_gfree_p[] = {  "divder_u_bootspi_div_dynm", "fixed_rate_clk_xtal_24m"};
+
+static const char *const mux_u_scpu_core_clk_2mux1_gfree_p[] = { "divder_u_scpu_core_div_dynm", "fixed_rate_clk_xtal_24m"};
+
+static const char *const mux_u_lpcpu_core_clk_2mux1_gfree_p[] = {"divder_u_lpcpu_core_div_dynm", "fixed_rate_clk_xtal_24m"};
+
+static const char *const mux_u_vo_mclk_2mux_ext_mclk_p[] = {"divder_u_vo_mclk_div_dynm", "fixed_rate_ext_mclk"};
+
+static const char *const mux_u_aondma_axi2mux1_gfree_p[] = { "divder_u_aondma_axi_div_dynm", "fixed_rate_clk_xtal_24m"};
+
+static const char *const mux_u_rmii_ref_2mux1_p[] = { "fixed_factor_u_hsp_rmii_ref_div6", "fixed_rate_lpddr_ref_bak"};
+
+static const char *const mux_u_eth_core_2mux1_p[] = { "fixed_rate_clk_spll1_fout3", "fixed_rate_lpddr_ref_bak"};
+
+static const char *const mux_u_sata_phy_2mux1_p[] = { "divder_u_sata_phy_ref_div_dynm", "fixed_rate_lpddr_ref_bak"};
+
+/* fixed rate clocks */
+static struct eswin_fixed_rate_clock eic7700_fixed_rate_clks[] = {
+	{ EIC7700_XTAL_24M,		"fixed_rate_clk_xtal_24m",	NULL, 0,	24000000, },
+	{ EIC7700_XTAL_32K,		"fixed_rate_clk_xtal_32k",	NULL, 0,	32768, },
+	{ EIC7700_SPLL0_FOUT1,		"fixed_rate_clk_spll0_fout1",	NULL, 0,	1600000000, },
+	{ EIC7700_SPLL0_FOUT2,		"fixed_rate_clk_spll0_fout2",	NULL, 0,	800000000, },
+	{ EIC7700_SPLL0_FOUT3,		"fixed_rate_clk_spll0_fout3",	NULL, 0,	400000000, },
+	{ EIC7700_SPLL1_FOUT1,		"fixed_rate_clk_spll1_fout1",	NULL, 0,	1500000000, },
+	{ EIC7700_SPLL1_FOUT2,  	"fixed_rate_clk_spll1_fout2",	NULL, 0,	300000000, },
+	{ EIC7700_SPLL1_FOUT3,		"fixed_rate_clk_spll1_fout3",	NULL, 0,	250000000, },
+	{ EIC7700_SPLL2_FOUT1,		"fixed_rate_clk_spll2_fout1",	NULL, 0,	2080000000, },
+	{ EIC7700_SPLL2_FOUT2,		"fixed_rate_clk_spll2_fout2",	NULL, 0,	1040000000, },
+	{ EIC7700_SPLL2_FOUT3,		"fixed_rate_clk_spll2_fout3",	NULL, 0,	416000000, },
+	{ EIC7700_VPLL_FOUT1,		"fixed_rate_clk_vpll_fout1",	NULL, 0,	1188000000, },
+	{ EIC7700_VPLL_FOUT2,		"fixed_rate_clk_vpll_fout2",	NULL, 0,	594000000, },
+	{ EIC7700_VPLL_FOUT3,		"fixed_rate_clk_vpll_fout3",	NULL, 0,	49500000, },
+	{ EIC7700_APLL_FOUT2,		"fixed_rate_clk_apll_fout2",	NULL, 0,	0, },
+	{ EIC7700_APLL_FOUT3,		"fixed_rate_clk_apll_fout3",	NULL, 0,	0, },
+	{ EIC7700_EXT_MCLK,		"fixed_rate_ext_mclk",		NULL, 0,	0, },
+	{ EIC7700_LPDDR_REF_BAK,	"fixed_rate_lpddr_ref_bak",	NULL, 0,	50000000, },
+};
+
+static struct eswin_pll_clock eic7700_pll_clks[] = {
+	{
+		EIC7700_APLL_FOUT1, "clk_apll_fout1", NULL,
+		EIC7700_REG_OFFSET_APLL_CFG_0, 0, 1, 12,6, 20,12,
+		EIC7700_REG_OFFSET_APLL_CFG_1, 4,24,
+		EIC7700_REG_OFFSET_APLL_CFG_2, 1,3, 16, 3,
+		EIC7700_REG_OFFSET_PLL_STATUS, 4, 1,
+	},
+	{
+		EIC7700_PLL_CPU, "clk_pll_cpu", NULL,
+		EIC7700_REG_OFFSET_MCPUT_PLL_CFG_0, 0,1, 12,6, 20,12,
+		EIC7700_REG_OFFSET_MCPUT_PLL_CFG_1, 4, 24,
+		EIC7700_REG_OFFSET_MCPUT_PLL_CFG_2, 1,3, 16,3,
+		EIC7700_REG_OFFSET_PLL_STATUS, 5, 1,
+	},
+};
+
+/* fixed factor clocks */
+static struct eswin_fixed_factor_clock eic7700_fixed_factor_clks[] = {
+	{ EIC7700_FIXED_FACTOR_U_CPU_DIV2,	 "fixed_factor_u_cpu_div2",   "mux_u_cpu_root_3mux1_gfree", 1, 2, 0, },
+
+	{ EIC7700_FIXED_FACTOR_U_CLK_1M_DIV24,   "fixed_factor_u_clk_1m_div24",   "fixed_rate_clk_xtal_24m", 1, 24, 0, },
+
+	{ EIC7700_FIXED_FACTOR_U_MIPI_TXESC_DIV10, "fixed_factor_u_mipi_txesc_div10", "clk_clk_sys_cfg",  1, 10, 0, },
+
+	{ EIC7700_FIXED_FACTOR_U_U84_CORE_LP_DIV2,   "fixed_factor_u_u84_core_lp_div2",   "gate_clk_spll0_fout2", 1, 2, 0, },
+
+	{ EIC7700_FIXED_FACTOR_U_SCPU_BUS_DIV2,   "fixed_factor_u_scpu_bus_div2",   "mux_u_scpu_core_clk_2mux1_gfree", 1, 2, 0, },
+
+	{ EIC7700_FIXED_FACTOR_U_LPCPU_BUS_DIV2, "fixed_factor_u_lpcpu_bus_div2", "mux_u_lpcpu_core_clk_2mux1_gfree",  1, 2, 0, },
+
+	{ EIC7700_FIXED_FACTOR_U_PCIE_CR_DIV2,   "fixed_factor_u_pcie_cr_div2",   "clk_clk_sys_cfg", 1, 2, 0, },
+
+	{ EIC7700_FIXED_FACTOR_U_PCIE_AUX_DIV4,   "fixed_factor_u_pcie_aux_div4",   "clk_clk_sys_cfg", 1, 4, 0, },
+
+	{ EIC7700_FIXED_FACTOR_U_PVT_DIV20, "fixed_factor_u_pvt_div20", "fixed_rate_clk_xtal_24m",  1, 20, 0, },
+
+	{ EIC7700_FIXED_FACTOR_U_HSP_RMII_REF_DIV6, "fixed_factor_u_hsp_rmii_ref_div6", "fixed_rate_clk_spll1_fout2",  1, 6, 0, },
+};
+
+static struct eswin_mux_clock eic7700_mux_clks[] = {
+	{ EIC7700_MUX_U_CPU_ROOT_3MUX1_GFREE, "mux_u_cpu_root_3mux1_gfree", mux_u_cpu_root_3mux1_gfree_p,
+		ARRAY_SIZE(mux_u_cpu_root_3mux1_gfree_p), CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_U84_CLK_CTRL,
+		0, BIT_MASK(0) | BIT_MASK(1), 0, mux_u_cpu_root_3mux1_gfree_p_table, },
+
+	{ EIC7700_MUX_U_CPU_ACLK_2MUX1_GFREE, "mux_u_cpu_aclk_2mux1_gfree", mux_u_cpu_aclk_2mux1_gfree_p,
+		ARRAY_SIZE(mux_u_cpu_aclk_2mux1_gfree_p), CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_U84_CLK_CTRL,
+		20, 1, 0,},
+
+	{ EIC7700_MUX_U_DSP_ACLK_ROOT_2MUX1_GFREE, "mux_u_dsp_aclk_root_2mux1_gfree", dsp_aclk_root_2mux1_gfree_mux_p,
+		ARRAY_SIZE(dsp_aclk_root_2mux1_gfree_mux_p), CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_DSP_ACLK_CTRL,
+		0, 1, 0,},
+
+	{ EIC7700_MUX_U_D2D_ACLK_ROOT_2MUX1_GFREE, "mux_u_d2d_aclk_root_2mux1_gfree", d2d_aclk_root_2mux1_gfree_mux_p,
+		ARRAY_SIZE(d2d_aclk_root_2mux1_gfree_mux_p), CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_D2D_ACLK_CTRL,
+		0, 1, 0,},
+
+	{ EIC7700_MUX_U_DDR_ACLK_ROOT_2MUX1_GFREE, "mux_u_ddr_aclk_root_2mux1_gfree", ddr_aclk_root_2mux1_gfree_mux_p,
+		ARRAY_SIZE(ddr_aclk_root_2mux1_gfree_mux_p), CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_DDR_CLK_CTRL,
+		16, 1, 0,},
+
+	{ EIC7700_MUX_U_MSHCORE_ROOT_3MUX1_0, "mux_u_mshcore_root_3mux1_0", mshcore_root_3mux1_0_mux_p,
+		ARRAY_SIZE(mshcore_root_3mux1_0_mux_p), CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_MSHC0_CORECLK_CTRL,
+		0, BIT_MASK(0) | BIT_MASK(20), 0, mshcore_root_3mux1_0_mux_p_table},
+
+	{ EIC7700_MUX_U_MSHCORE_ROOT_3MUX1_1, "mux_u_mshcore_root_3mux1_1", mshcore_root_3mux1_1_mux_p,
+		ARRAY_SIZE(mshcore_root_3mux1_1_mux_p), CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_MSHC1_CORECLK_CTRL,
+		0, BIT_MASK(0) | BIT_MASK(20), 0, mshcore_root_3mux1_1_mux_p_table, },
+
+	{ EIC7700_MUX_U_MSHCORE_ROOT_3MUX1_2, "mux_u_mshcore_root_3mux1_2", mshcore_root_3mux1_2_mux_p,
+		ARRAY_SIZE(mshcore_root_3mux1_2_mux_p), CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_MSHC2_CORECLK_CTRL,
+		0, BIT_MASK(0) | BIT_MASK(20), 0, mshcore_root_3mux1_2_mux_p_table },
+
+	{ EIC7700_MUX_U_NPU_LLCLK_3MUX1_GFREE, "mux_u_npu_llclk_3mux1_gfree", npu_llclk_3mux1_gfree_mux_p,
+		ARRAY_SIZE(npu_llclk_3mux1_gfree_mux_p), CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_NPU_LLC_CTRL,
+		0, BIT_MASK(0) | BIT_MASK(1), 0, npu_llclk_3mux1_gfree_mux_p_table},
+
+	{ EIC7700_MUX_U_NPU_CORE_3MUX1_GFREE, "mux_u_npu_core_3mux1_gfree", npu_core_3mux1_gfree_mux_p,
+		ARRAY_SIZE(npu_core_3mux1_gfree_mux_p), CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_NPU_CORE_CTRL,
+		0, BIT_MASK(0) | BIT_MASK(1), 0, npu_core_3mux1_gfree_mux_p_table},
+
+	{ EIC7700_MUX_U_NPU_E31_3MUX1_GFREE, "mux_u_npu_e31_3mux1_gfree", npu_e31_3mux1_gfree_mux_p,
+		ARRAY_SIZE(npu_e31_3mux1_gfree_mux_p), CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_NPU_CORE_CTRL,
+		0, BIT_MASK(8) | BIT_MASK(9), 0, npu_e31_3mux1_gfree_mux_p_table},
+
+	{ EIC7700_MUX_U_VI_ACLK_ROOT_2MUX1_GFREE, "mux_u_vi_aclk_root_2mux1_gfree", vi_aclk_root_2mux1_gfree_mux_p,
+		ARRAY_SIZE(vi_aclk_root_2mux1_gfree_mux_p), CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_VI_ACLK_CTRL,
+		0, 1, 0,},
+
+	{ EIC7700_MUX_U_VI_DW_ROOT_2MUX1, "mux_u_vi_dw_root_2mux1", mux_u_vi_dw_root_2mux1_p,
+		ARRAY_SIZE(mux_u_vi_dw_root_2mux1_p), CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_VI_DWCLK_CTRL,
+		0, 1, 0,},
+
+	{ EIC7700_MUX_U_VI_DVP_ROOT_2MUX1_GFREE, "mux_u_vi_dvp_root_2mux1_gfree", mux_u_vi_dvp_root_2mux1_gfree_p,
+		ARRAY_SIZE(mux_u_vi_dvp_root_2mux1_gfree_p), CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_VI_DVP_CLK_CTRL,
+		0, 1, 0, },
+
+	{ EIC7700_MUX_U_VI_DIG_ISP_ROOT_2MUX1_GFREE, "mux_u_vi_dig_isp_root_2mux1_gfree", mux_u_vi_dig_isp_root_2mux1_gfree_p,
+		ARRAY_SIZE(mux_u_vi_dig_isp_root_2mux1_gfree_p), CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_VI_DIG_ISP_CLK_CTRL,
+		0, 1, 0, },
+
+	{ EIC7700_MUX_U_VO_ACLK_ROOT_2MUX1_GFREE, "mux_u_vo_aclk_root_2mux1_gfree", mux_u_vo_aclk_root_2mux1_gfree_p,
+		ARRAY_SIZE(mux_u_vo_aclk_root_2mux1_gfree_p), CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_VO_ACLK_CTRL,
+		0, 1, 0, },
+
+	{ EIC7700_MUX_U_VO_PIXEL_ROOT_2MUX1, "mux_u_vo_pixel_root_2mux1", mux_u_vo_pixel_root_2mux1_p,
+		ARRAY_SIZE(mux_u_vo_pixel_root_2mux1_p), CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_VO_PIXEL_CTRL,
+		0, 1, 0, },
+
+	{ EIC7700_MUX_U_VCDEC_ROOT_2MUX1_GFREE,  "mux_u_vcdec_root_2mux1_gfree",  mux_u_vcdec_root_2mux1_gfree_p,
+		ARRAY_SIZE(mux_u_vcdec_root_2mux1_gfree_p),  CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_VCDEC_ROOTCLK_CTRL,
+		0, 1, 0, },
+
+	{ EIC7700_MUX_U_VCACLK_ROOT_2MUX1_GFREE,  "mux_u_vcaclk_root_2mux1_gfree",  mux_u_vcaclk_root_2mux1_gfree_p,
+		ARRAY_SIZE(mux_u_vcaclk_root_2mux1_gfree_p),  CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_VC_ACLK_CTRL,
+		0, 1, 0, },
+
+	{ EIC7700_MUX_U_SYSCFG_CLK_ROOT_2MUX1_GFREE,  "mux_u_syscfg_clk_root_2mux1_gfree",  mux_u_syscfg_clk_root_2mux1_gfree_p,
+		ARRAY_SIZE(mux_u_syscfg_clk_root_2mux1_gfree_p),  CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_SYSCFG_CLK_CTRL,
+		0, 1, 0, },
+
+	{ EIC7700_MUX_U_BOOTSPI_CLK_2MUX1_GFREE,  "mux_u_bootspi_clk_2mux1_gfree",  mux_u_bootspi_clk_2mux1_gfree_p,
+		ARRAY_SIZE(mux_u_bootspi_clk_2mux1_gfree_p),  CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_BOOTSPI_CLK_CTRL,
+		0, 1, 0, },
+
+	{ EIC7700_MUX_U_SCPU_CORE_CLK_2MUX1_GFREE,  "mux_u_scpu_core_clk_2mux1_gfree",  mux_u_scpu_core_clk_2mux1_gfree_p,
+		ARRAY_SIZE(mux_u_scpu_core_clk_2mux1_gfree_p),  CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_SCPU_CORECLK_CTRL,
+		0, 1, 0, },
+
+	{ EIC7700_MUX_U_LPCPU_CORE_CLK_2MUX1_GFREE,  "mux_u_lpcpu_core_clk_2mux1_gfree",  mux_u_lpcpu_core_clk_2mux1_gfree_p,
+		ARRAY_SIZE(mux_u_lpcpu_core_clk_2mux1_gfree_p),  CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_LPCPU_CORECLK_CTRL,
+		0, 1, 0, },
+
+	{ EIC7700_MUX_U_VO_MCLK_2MUX_EXT_MCLK,  "mux_u_vo_mclk_2mux_ext_mclk",  mux_u_vo_mclk_2mux_ext_mclk_p,
+		ARRAY_SIZE(mux_u_vo_mclk_2mux_ext_mclk_p),  CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_VO_MCLK_CTRL,
+		0, 1, 0, },
+
+	{ EIC7700_MUX_U_AONDMA_AXI2MUX1_GFREE,  "mux_u_aondma_axi2mux1_gfree",  mux_u_aondma_axi2mux1_gfree_p,
+		ARRAY_SIZE(mux_u_aondma_axi2mux1_gfree_p),  CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_AON_DMA_CLK_CTRL,
+		20, 1, 0, },
+
+	{ EIC7700_MUX_U_RMII_REF_2MUX,  "mux_u_rmii_ref_2mux1",  mux_u_rmii_ref_2mux1_p,
+		ARRAY_SIZE(mux_u_rmii_ref_2mux1_p),  CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_ETH0_CTRL,
+		2, 1, 0, },
+
+	{ EIC7700_MUX_U_ETH_CORE_2MUX1,  "mux_u_eth_core_2mux1",  mux_u_eth_core_2mux1_p,
+		ARRAY_SIZE(mux_u_eth_core_2mux1_p),  CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_ETH0_CTRL,
+		1, 1, 0, },
+
+	{ EIC7700_MUX_U_SATA_PHY_2MUX1,  "mux_u_sata_phy_2mux1",  mux_u_sata_phy_2mux1_p,
+		ARRAY_SIZE(mux_u_sata_phy_2mux1_p),  CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_SATA_OOB_CTRL,
+		9, 1, 0, },
+
+};
+
+/*The hardware decides vaule 0, 1 and 2 both means 2 divsor, so we have to add these ugly tables*/
+/* +1 makes space for sentinel value to indicate end of table */
+static struct clk_div_table u_3_bit_special_div_table[8+1];
+static struct clk_div_table u_4_bit_special_div_table[16+1];
+static struct clk_div_table u_6_bit_special_div_table[64+1];
+static struct clk_div_table u_7_bit_special_div_table[128+1];
+static struct clk_div_table u_8_bit_special_div_table[256+1];
+static struct clk_div_table u_11_bit_special_div_table[2048+1];
+static struct clk_div_table u_16_bit_special_div_table[65536+1];
+
+static struct eswin_divider_clock eic7700_div_clks[] = {
+	{ EIC7700_DIVDER_U_SYS_CFG_DIV_DYNM, "divder_u_sys_cfg_div_dynm",   "fixed_rate_clk_spll0_fout3", 0,
+		EIC7700_REG_OFFSET_SYSCFG_CLK_CTRL, 4, 3, CLK_DIVIDER_ROUND_CLOSEST, u_3_bit_special_div_table},
+
+	{ EIC7700_DIVDER_U_NOC_NSP_DIV_DYNM,   "divder_u_noc_nsp_div_dynm", "fixed_rate_clk_spll2_fout1", 0,
+		EIC7700_REG_OFFSET_NOC_CLK_CTRL, 0, 3, CLK_DIVIDER_ROUND_CLOSEST, u_3_bit_special_div_table},
+
+	{ EIC7700_DIVDER_U_BOOTSPI_DIV_DYNM,       "divder_u_bootspi_div_dynm",     "gate_clk_spll0_fout2", 0,
+		EIC7700_REG_OFFSET_BOOTSPI_CLK_CTRL, 4, 6, CLK_DIVIDER_ROUND_CLOSEST, u_6_bit_special_div_table},
+
+	{ EIC7700_DIVDER_U_SCPU_CORE_DIV_DYNM,     "divder_u_scpu_core_div_dynm",   "fixed_rate_clk_spll0_fout1", 0,
+		EIC7700_REG_OFFSET_SCPU_CORECLK_CTRL, 4, 4, CLK_DIVIDER_ROUND_CLOSEST, u_4_bit_special_div_table},
+
+	{ EIC7700_DIVDER_U_LPCPU_CORE_DIV_DYNM,     "divder_u_lpcpu_core_div_dynm",   "fixed_rate_clk_spll0_fout1", 0,
+		EIC7700_REG_OFFSET_LPCPU_CORECLK_CTRL, 4, 4, CLK_DIVIDER_ROUND_CLOSEST, u_4_bit_special_div_table},
+
+	{ EIC7700_DIVDER_U_GPU_ACLK_DIV_DYNM,     "divder_u_gpu_aclk_div_dynm",   "fixed_rate_clk_spll0_fout1", 0,
+		EIC7700_REG_OFFSET_GPU_ACLK_CTRL, 4, 4, CLK_DIVIDER_ROUND_CLOSEST, u_4_bit_special_div_table},
+
+	{ EIC7700_DIVDER_U_DSP_ACLK_DIV_DYNM,     "divder_u_dsp_aclk_div_dynm",   "clk_clk_dsp_root", 0,
+		EIC7700_REG_OFFSET_DSP_ACLK_CTRL, 4, 4, CLK_DIVIDER_ROUND_CLOSEST, u_4_bit_special_div_table},
+
+	{ EIC7700_DIVDER_U_D2D_ACLK_DIV_DYNM, "divder_u_d2d_aclk_div_dynm",   "mux_u_d2d_aclk_root_2mux1_gfree", 0,
+		EIC7700_REG_OFFSET_D2D_ACLK_CTRL, 4, 4, CLK_DIVIDER_ROUND_CLOSEST, u_4_bit_special_div_table},
+
+	{ EIC7700_DIVDER_U_DDR_ACLK_DIV_DYNM, "divder_u_ddr_aclk_div_dynm",   "mux_u_ddr_aclk_root_2mux1_gfree", 0,
+		EIC7700_REG_OFFSET_DDR_CLK_CTRL, 20, 4, CLK_DIVIDER_ROUND_CLOSEST, u_4_bit_special_div_table},
+
+	{ EIC7700_DIVDER_U_HSP_ACLK_DIV_DYNM,   "divder_u_hsp_aclk_div_dynm", "fixed_rate_clk_spll0_fout1", 0,
+		EIC7700_REG_OFFSET_HSP_ACLK_CTRL, 4, 4, CLK_DIVIDER_ROUND_CLOSEST, u_4_bit_special_div_table},
+
+	{ EIC7700_DIVDER_U_ETH_TXCLK_DIV_DYNM_0,     "divder_u_eth_txclk_div_dynm_0",   "mux_u_eth_core_2mux1", 0,
+		EIC7700_REG_OFFSET_ETH0_CTRL, 4, 7, CLK_DIVIDER_ROUND_CLOSEST, u_7_bit_special_div_table},
+
+	{ EIC7700_DIVDER_U_ETH_TXCLK_DIV_DYNM_1,     "divder_u_eth_txclk_div_dynm_1",   "mux_u_eth_core_2mux1", 0,
+		EIC7700_REG_OFFSET_ETH1_CTRL, 4, 7, CLK_DIVIDER_ROUND_CLOSEST, u_7_bit_special_div_table},
+
+	{ EIC7700_DIVDER_U_MSHC_CORE_DIV_DYNM_0,     "divder_u_mshc_core_div_dynm_0",   "mux_u_mshcore_root_3mux1_0", 0,
+		EIC7700_REG_OFFSET_MSHC0_CORECLK_CTRL, 4, 12, CLK_DIVIDER_ONE_BASED},
+
+	{ EIC7700_DIVDER_U_MSHC_CORE_DIV_DYNM_1,     "divder_u_mshc_core_div_dynm_1",   "mux_u_mshcore_root_3mux1_1", 0,
+		EIC7700_REG_OFFSET_MSHC1_CORECLK_CTRL, 4, 12, CLK_DIVIDER_ONE_BASED},
+
+	{ EIC7700_DIVDER_U_MSHC_CORE_DIV_DYNM_2,     "divder_u_mshc_core_div_dynm_2",   "mux_u_mshcore_root_3mux1_2",  0,
+		EIC7700_REG_OFFSET_MSHC2_CORECLK_CTRL, 4, 12, CLK_DIVIDER_ONE_BASED},
+
+	{ EIC7700_DIVDER_U_PCIE_ACLK_DIV_DYNM,   "divder_u_pcie_aclk_div_dynm", "fixed_rate_clk_spll2_fout2", 0,
+		EIC7700_REG_OFFSET_PCIE_ACLK_CTRL, 4, 4, CLK_DIVIDER_ROUND_CLOSEST, u_4_bit_special_div_table},
+
+	{ EIC7700_DIVDER_U_NPU_ACLK_DIV_DYNM,        "divder_u_npu_aclk_div_dynm", "fixed_rate_clk_spll0_fout1", 0,
+		EIC7700_REG_OFFSET_NPU_ACLK_CTRL, 4, 4, CLK_DIVIDER_ROUND_CLOSEST, u_4_bit_special_div_table},
+
+	{ EIC7700_DIVDER_U_NPU_LLC_SRC0_DIV_DYNM,    "divder_u_npu_llc_src0_div_dynm",  "fixed_rate_clk_spll0_fout1", 0,
+		EIC7700_REG_OFFSET_NPU_LLC_CTRL, 4, 4, CLK_DIVIDER_ROUND_CLOSEST, u_4_bit_special_div_table},
+
+	{ EIC7700_DIVDER_U_NPU_LLC_SRC1_DIV_DYNM,    "divder_u_npu_llc_src1_div_dynm",   "fixed_rate_clk_spll2_fout1", 0,
+		EIC7700_REG_OFFSET_NPU_LLC_CTRL, 8, 4, CLK_DIVIDER_ROUND_CLOSEST, u_4_bit_special_div_table},
+
+	{ EIC7700_DIVDER_U_NPU_CORECLK_DIV_DYNM,     "divder_u_npu_coreclk_div_dynm",   "mux_u_npu_core_3mux1_gfree", 0,
+		EIC7700_REG_OFFSET_NPU_CORE_CTRL, 4, 4, CLK_DIVIDER_ONE_BASED},
+
+	{ EIC7700_DIVDER_U_NPU_E31_DIV_DYNM,         "divder_u_npu_e31_div_dynm",   "mux_u_npu_e31_3mux1_gfree", 0,
+		EIC7700_REG_OFFSET_NPU_CORE_CTRL, 12, 4, CLK_DIVIDER_ONE_BASED},
+
+	{ EIC7700_DIVDER_U_VI_ACLK_DIV_DYNM,          "divder_u_vi_aclk_div_dynm",   "mux_u_vi_aclk_root_2mux1_gfree", 0,
+		EIC7700_REG_OFFSET_VI_ACLK_CTRL, 4, 4, CLK_DIVIDER_ROUND_CLOSEST, u_4_bit_special_div_table},
+
+	{ EIC7700_DIVDER_U_VI_DW_DIV_DYNM,            "divder_u_vi_dw_div_dynm",   "mux_u_vi_dw_root_2mux1", 0,
+		EIC7700_REG_OFFSET_VI_DWCLK_CTRL, 4, 4, CLK_DIVIDER_ROUND_CLOSEST, u_4_bit_special_div_table},
+
+	{ EIC7700_DIVDER_U_VI_DVP_DIV_DYNM,        "divder_u_vi_dvp_div_dynm",   "mux_u_vi_dig_root_2mux1_gfree", 0,
+		EIC7700_REG_OFFSET_VI_DVP_CLK_CTRL, 4, 4, CLK_DIVIDER_ROUND_CLOSEST, u_4_bit_special_div_table},
+
+	{ EIC7700_DIVDER_U_VI_DIG_ISP_DIV_DYNM,       "divder_u_vi_dig_isp_div_dynm", "mux_u_vi_dig_isp_root_2mux1_gfree", 0,
+		EIC7700_REG_OFFSET_VI_DIG_ISP_CLK_CTRL, 4, 4, CLK_DIVIDER_ROUND_CLOSEST, u_4_bit_special_div_table},
+
+	{ EIC7700_DIVDER_U_VI_SHUTTER_DIV_DYNM_0,     "divder_u_vi_shutter_div_dynm_0",   "fixed_rate_clk_vpll_fout2",0,
+		EIC7700_REG_OFFSET_VI_SHUTTER0, 4, 7, CLK_DIVIDER_ROUND_CLOSEST, u_7_bit_special_div_table},
+
+	{ EIC7700_DIVDER_U_VI_SHUTTER_DIV_DYNM_1,     "divder_u_vi_shutter_div_dynm_1",   "fixed_rate_clk_vpll_fout2", 0,
+		EIC7700_REG_OFFSET_VI_SHUTTER1, 4, 7,  CLK_DIVIDER_ROUND_CLOSEST, u_7_bit_special_div_table},
+
+	{ EIC7700_DIVDER_U_VI_SHUTTER_DIV_DYNM_2,     "divder_u_vi_shutter_div_dynm_2",   "fixed_rate_clk_vpll_fout2", 0,
+		EIC7700_REG_OFFSET_VI_SHUTTER2, 4, 7, CLK_DIVIDER_ROUND_CLOSEST, u_7_bit_special_div_table},
+
+	{ EIC7700_DIVDER_U_VI_SHUTTER_DIV_DYNM_3,     "divder_u_vi_shutter_div_dynm_3",   "fixed_rate_clk_vpll_fout2", 0,
+		EIC7700_REG_OFFSET_VI_SHUTTER3, 4, 7, CLK_DIVIDER_ROUND_CLOSEST, u_7_bit_special_div_table},
+
+	{ EIC7700_DIVDER_U_VI_SHUTTER_DIV_DYNM_4,     "divder_u_vi_shutter_div_dynm_4",   "fixed_rate_clk_vpll_fout2", 0,
+		EIC7700_REG_OFFSET_VI_SHUTTER4, 4, 7, CLK_DIVIDER_ROUND_CLOSEST, u_7_bit_special_div_table},
+
+	{ EIC7700_DIVDER_U_VI_SHUTTER_DIV_DYNM_5,     "divder_u_vi_shutter_div_dynm_5",   "fixed_rate_clk_vpll_fout2", 0,
+		EIC7700_REG_OFFSET_VI_SHUTTER5, 4, 7, CLK_DIVIDER_ROUND_CLOSEST, u_7_bit_special_div_table},
+
+	{ EIC7700_DIVDER_U_VO_ACLK_DIV_DYNM,         "divder_u_vo_aclk_div_dynm", "mux_u_vo_aclk_root_2mux1_gfree", 0,
+		EIC7700_REG_OFFSET_VO_ACLK_CTRL, 4, 4, CLK_DIVIDER_ROUND_CLOSEST, u_4_bit_special_div_table},
+
+	{ EIC7700_DIVDER_U_IESMCLK_DIV_DYNM,       "divder_u_iesmclk_div_dynm",     "fixed_rate_clk_spll0_fout3", 0,
+		EIC7700_REG_OFFSET_VO_IESMCLK_CTRL, 4, 4, CLK_DIVIDER_ROUND_CLOSEST, u_4_bit_special_div_table},
+
+	{ EIC7700_DIVDER_U_VO_PIXEL_DIV_DYNM,	 "divder_u_vo_pixel_div_dynm",	"mux_u_vo_pixel_root_2mux1", 0,
+		EIC7700_REG_OFFSET_VO_PIXEL_CTRL, 4, 6, CLK_DIVIDER_ROUND_CLOSEST, u_6_bit_special_div_table},
+
+	{ EIC7700_DIVDER_U_VO_MCLK_DIV_DYNM,     "divder_u_vo_mclk_div_dynm",   "clk_apll_fout1", 0,
+		EIC7700_REG_OFFSET_VO_MCLK_CTRL, 4, 8, CLK_DIVIDER_ROUND_CLOSEST, u_8_bit_special_div_table},
+
+	{ EIC7700_DIVDER_U_VO_CEC_DIV_DYNM,     "divder_u_vo_cec_div_dynm",   "fixed_rate_clk_vpll_fout2", 0,
+		EIC7700_REG_OFFSET_VO_PHY_CLKCTRL, 16, 16, CLK_DIVIDER_ROUND_CLOSEST, u_16_bit_special_div_table},
+
+	{ EIC7700_DIVDER_U_VC_ACLK_DIV_DYNM,     "divder_u_vc_aclk_div_dynm",   "mux_u_vcaclk_root_2mux1_gfree", 0,
+		EIC7700_REG_OFFSET_VC_ACLK_CTRL, 4, 4, CLK_DIVIDER_ROUND_CLOSEST, u_4_bit_special_div_table},
+
+	{ EIC7700_DIVDER_U_JD_DIV_DYNM,     "divder_u_jd_div_dynm",   "clk_clk_vc_root", 0,
+		EIC7700_REG_OFFSET_JD_CLK_CTRL, 4, 4,  CLK_DIVIDER_ROUND_CLOSEST, u_4_bit_special_div_table},
+
+	{ EIC7700_DIVDER_U_JE_DIV_DYNM,     "divder_u_je_div_dynm",   "clk_clk_vc_root", 0,
+		EIC7700_REG_OFFSET_JE_CLK_CTRL, 4, 4,  CLK_DIVIDER_ROUND_CLOSEST, u_4_bit_special_div_table},
+
+	{ EIC7700_DIVDER_U_VE_DIV_DYNM,     "divder_u_ve_div_dynm",   "clk_clk_vc_root", 0,
+		EIC7700_REG_OFFSET_VE_CLK_CTRL, 4, 4,  CLK_DIVIDER_ROUND_CLOSEST, u_4_bit_special_div_table},
+
+	{ EIC7700_DIVDER_U_VD_DIV_DYNM,     "divder_u_vd_div_dynm",    "clk_clk_vc_root", 0,
+		EIC7700_REG_OFFSET_VD_CLK_CTRL, 4, 4, CLK_DIVIDER_ROUND_CLOSEST, u_4_bit_special_div_table},
+
+	{ EIC7700_DIVDER_U_G2D_DIV_DYNM,       "divder_u_g2d_div_dynm",     "clk_clk_dsp_root", 0,
+		EIC7700_REG_OFFSET_G2D_CTRL, 4, 4, CLK_DIVIDER_ROUND_CLOSEST, u_4_bit_special_div_table},
+
+	{ EIC7700_DIVDER_U_AONDMA_AXI_DIV_DYNM,     "divder_u_aondma_axi_div_dynm",   "fixed_rate_clk_spll0_fout1", 0,
+		EIC7700_REG_OFFSET_AON_DMA_CLK_CTRL, 4, 4, CLK_DIVIDER_ROUND_CLOSEST, u_4_bit_special_div_table},
+
+	{ EIC7700_DIVDER_U_CRYPTO_DIV_DYNM,     "divder_u_crypto_div_dynm",   "fixed_rate_clk_spll0_fout1", 0,
+		EIC7700_REG_OFFSET_SPACC_CLK_CTRL, 4, 4, CLK_DIVIDER_ROUND_CLOSEST, u_4_bit_special_div_table},
+
+	{ EIC7700_DIVDER_U_SATA_PHY_REF_DIV_DYNM,     "divder_u_sata_phy_ref_div_dynm",   "fixed_rate_clk_spll1_fout2", 0,
+		EIC7700_REG_OFFSET_SATA_OOB_CTRL, 0, 4, CLK_DIVIDER_ROUND_CLOSEST, u_4_bit_special_div_table},
+
+	{ EIC7700_DIVDER_U_DSP_0_ACLK_DIV_DYNM,     "divder_u_dsp_0_aclk_div_dynm",   "gate_dspt_aclk", 0,
+		EIC7700_REG_OFFSET_DSP_CFG_CTRL, 19, 1, },
+
+	{ EIC7700_DIVDER_U_DSP_1_ACLK_DIV_DYNM,     "divder_u_dsp_1_aclk_div_dynm",   "gate_dspt_aclk", 0,
+		EIC7700_REG_OFFSET_DSP_CFG_CTRL, 20, 1, },
+
+	{ EIC7700_DIVDER_U_DSP_2_ACLK_DIV_DYNM,     "divder_u_dsp_2_aclk_div_dynm",   "gate_dspt_aclk", 0,
+		EIC7700_REG_OFFSET_DSP_CFG_CTRL, 21, 1, },
+
+	{ EIC7700_DIVDER_U_DSP_3_ACLK_DIV_DYNM,     "divder_u_dsp_3_aclk_div_dynm",   "gate_dspt_aclk", 0,
+		EIC7700_REG_OFFSET_DSP_CFG_CTRL, 22, 1, },
+
+	{ EIC7700_DIVDER_U_AON_RTC_DIV_DYNM,     "divder_u_aon_rtc_div_dynm",   "clk_clk_1m", 0,
+		EIC7700_REG_OFFSET_RTC_CLK_CTRL, 21, 11, CLK_DIVIDER_ROUND_CLOSEST, u_11_bit_special_div_table},
+
+	{ EIC7700_DIVDER_U_U84_RTC_TOGGLE_DIV_DYNM,     "divder_u_u84_rtc_toggle_dynm",   "fixed_rate_clk_xtal_24m", 0,
+		EIC7700_REG_OFFSET_RTC_CLK_CTRL, 16, 5, CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ROUND_CLOSEST},
+
+};
+
+/*
+	these clks should init early to cost down the whole clk module init time
+*/
+static struct eswin_clock eic7700_clks_early_0[] = {
+	{ EIC7700_CLK_CLK_DSP_ROOT , "clk_clk_dsp_root", "mux_u_dsp_aclk_root_2mux1_gfree", CLK_SET_RATE_PARENT,},
+	{ EIC7700_CLK_CLK_VC_ROOT, "clk_clk_vc_root", "mux_u_vcdec_root_2mux1_gfree", CLK_SET_RATE_PARENT,},
+};
+
+static struct eswin_clock eic7700_clks_early_1[] = {
+	{ EIC7700_CLK_CLK_SYS_CFG	,"clk_clk_sys_cfg", "mux_u_syscfg_clk_root_2mux1_gfree", CLK_SET_RATE_PARENT,},
+	{ EIC7700_CLK_CLK_D2DDR_ACLK	,"clk_clk_d2ddr_aclk", "divder_u_ddr_aclk_div_dynm", CLK_SET_RATE_PARENT,},
+	{ EIC7700_CLK_CLK_AONDMA_AXI_ST3,"clk_clk_aondma_axi_st3","mux_u_aondma_axi2mux1_gfree", CLK_SET_RATE_PARENT,},
+	{ EIC7700_CLK_CLK_G2D_ST2	,"clk_clk_g2d_st2",	"divder_u_g2d_div_dynm", CLK_SET_RATE_PARENT,},
+	{ EIC7700_CLK_CLK_MIPI_TXESC	,"clk_clk_mipi_txesc",	"fixed_factor_u_mipi_txesc_div10", CLK_SET_RATE_PARENT,},
+	{ EIC7700_CLK_CLK_VI_ACLK_ST1	,"clk_clk_vi_aclk_st1",	"divder_u_vi_aclk_div_dynm", CLK_SET_RATE_PARENT,},
+};
+
+static struct eswin_gate_clock eic7700_gate_clks[] = {
+
+	{ EIC7700_GATE_CLK_CPU_EXT_SRC_CORE_CLK_0 ,	"gate_clk_cpu_ext_src_core_clk_0", "mux_u_cpu_root_3mux1_gfree", CLK_SET_RATE_PARENT,
+		EIC7700_REG_OFFSET_U84_CLK_CTRL, 28, 0, },
+
+	{ EIC7700_GATE_CLK_CPU_EXT_SRC_CORE_CLK_1 ,	"gate_clk_cpu_ext_src_core_clk_1", "mux_u_cpu_root_3mux1_gfree", CLK_SET_RATE_PARENT,
+		EIC7700_REG_OFFSET_U84_CLK_CTRL, 29, 0, },
+
+	{ EIC7700_GATE_CLK_CPU_EXT_SRC_CORE_CLK_2 ,	"gate_clk_cpu_ext_src_core_clk_2", "mux_u_cpu_root_3mux1_gfree", CLK_SET_RATE_PARENT,
+		EIC7700_REG_OFFSET_U84_CLK_CTRL, 30, 0, },
+
+	{ EIC7700_GATE_CLK_CPU_EXT_SRC_CORE_CLK_3 ,	"gate_clk_cpu_ext_src_core_clk_3", "mux_u_cpu_root_3mux1_gfree", CLK_SET_RATE_PARENT,
+		EIC7700_REG_OFFSET_U84_CLK_CTRL, 31, 0, },
+
+	{ EIC7700_GATE_CLK_CPU_TRACE_CLK_0 ,		"gate_clk_cpu_trace_clk_0", "mux_u_cpu_root_3mux1_gfree", CLK_SET_RATE_PARENT,
+		EIC7700_REG_OFFSET_U84_CLK_CTRL, 24, 0, },
+
+	{ EIC7700_GATE_CLK_CPU_TRACE_CLK_1 ,		"gate_clk_cpu_trace_clk_1", "mux_u_cpu_root_3mux1_gfree", CLK_SET_RATE_PARENT,
+		EIC7700_REG_OFFSET_U84_CLK_CTRL, 25, 0, },
+
+	{ EIC7700_GATE_CLK_CPU_TRACE_CLK_2 ,		"gate_clk_cpu_trace_clk_2", "mux_u_cpu_root_3mux1_gfree", CLK_SET_RATE_PARENT,
+		EIC7700_REG_OFFSET_U84_CLK_CTRL, 26, 0, },
+
+	{ EIC7700_GATE_CLK_CPU_TRACE_CLK_3 ,		"gate_clk_cpu_trace_clk_3", "mux_u_cpu_root_3mux1_gfree", CLK_SET_RATE_PARENT,
+		EIC7700_REG_OFFSET_U84_CLK_CTRL, 27, 0, },
+
+	{ EIC7700_GATE_CLK_CPU_TRACE_COM_CLK ,		"gate_clk_cpu_trace_com_clk", "mux_u_cpu_aclk_2mux1_gfree", CLK_SET_RATE_PARENT,
+		EIC7700_REG_OFFSET_U84_CLK_CTRL, 23, 0, },
+
+	{ EIC7700_GATE_CLK_CPU_CLK ,			"gate_clk_cpu_clk", "mux_u_cpu_aclk_2mux1_gfree", CLK_SET_RATE_PARENT,
+		EIC7700_REG_OFFSET_U84_CLK_CTRL, 28, 0, }, /*same as EIC7700_GATE_CLK_CPU_EXT_SRC_CORE_CLK_0 */
+
+	{ EIC7700_GATE_CLK_SPLL0_FOUT2 ,		"gate_clk_spll0_fout2", "fixed_rate_clk_spll0_fout2", CLK_SET_RATE_PARENT,
+		EIC7700_REG_OFFSET_SPLL0_CFG_2, 31, 0, },
+
+	{ EIC7700_GATE_NOC_NSP_CLK ,			"gate_noc_nsp_clk", "divder_u_noc_nsp_div_dynm", CLK_SET_RATE_PARENT,
+		EIC7700_REG_OFFSET_NOC_CLK_CTRL, 31, 0, },
+
+	{ EIC7700_GATE_CLK_BOOTSPI ,			"gate_clk_bootspi", "mux_u_bootspi_clk_2mux1_gfree", CLK_SET_RATE_PARENT,
+		EIC7700_REG_OFFSET_BOOTSPI_CLK_CTRL, 31, 0, },
+
+	{ EIC7700_GATE_CLK_BOOTSPI_CFG	,		"gate_clk_bootspi_cfg",   "clk_clk_sys_cfg", CLK_SET_RATE_PARENT,
+		EIC7700_REG_OFFSET_BOOTSPI_CFGCLK_CTRL, 31, 0, },
+
+	{ EIC7700_GATE_CLK_SCPU_CORE	,		"gate_clk_scpu_core",   "mux_u_scpu_core_clk_2mux1_gfree", CLK_SET_RATE_PARENT,
+		EIC7700_REG_OFFSET_SCPU_CORECLK_CTRL, 31, 0, },
+
+	{ EIC7700_GATE_CLK_SCPU_BUS 			,"gate_clk_scpu_bus",   "fixed_factor_u_scpu_bus_div2", CLK_SET_RATE_PARENT,
+		EIC7700_REG_OFFSET_SCPU_BUSCLK_CTRL, 31, 0, },
+
+	{ EIC7700_GATE_CLK_LPCPU_CORE			,"gate_clk_lpcpu_core",   "mux_u_lpcpu_core_clk_2mux1_gfree", CLK_SET_RATE_PARENT,
+		EIC7700_REG_OFFSET_LPCPU_CORECLK_CTRL, 31, 0, },
+
+	{ EIC7700_GATE_CLK_LPCPU_BUS			,"gate_clk_lpcpu_bus",   "fixed_factor_u_lpcpu_bus_div2", CLK_SET_RATE_PARENT,
+		EIC7700_REG_OFFSET_LPCPU_BUSCLK_CTRL, 31, 0, },
+
+	{ EIC7700_GATE_GPU_ACLK 			,"gate_gpu_aclk",   "divder_u_gpu_aclk_div_dynm", CLK_SET_RATE_PARENT,
+		EIC7700_REG_OFFSET_GPU_ACLK_CTRL, 31, 0, },
+
+	{ EIC7700_GATE_GPU_GRAY_CLK 			,"gate_gpu_gray_clk",   "fixed_rate_clk_xtal_24m", CLK_SET_RATE_PARENT,
+		EIC7700_REG_OFFSET_GPU_GRAY_CTRL, 31, 0, },
+
+	{ EIC7700_GATE_GPU_CFG_CLK			,"gate_gpu_cfg_clk",   "clk_clk_sys_cfg", CLK_SET_RATE_PARENT,
+		EIC7700_REG_OFFSET_GPU_CFG_CTRL, 31, 0, },
+
+	{ EIC7700_GATE_DSPT_ACLK			,"gate_dspt_aclk",   "divder_u_dsp_aclk_div_dynm", CLK_SET_RATE_PARENT,
+		EIC7700_REG_OFFSET_DSP_ACLK_CTRL, 31, 0, },
+
+	{ EIC7700_GATE_DSPT_CFG_CLK 			,"gate_dspt_cfg_clk",   "clk_clk_sys_cfg", CLK_SET_RATE_PARENT,
+		EIC7700_REG_OFFSET_DSP_CFG_CTRL, 31, 0, },
+
+	{ EIC7700_GATE_D2D_ACLK 			,"gate_d2d_aclk",   "divder_u_d2d_aclk_div_dynm", CLK_SET_RATE_PARENT,
+		EIC7700_REG_OFFSET_D2D_ACLK_CTRL, 31, 0, },
+
+	{ EIC7700_GATE_D2D_CFG_CLK			,"gate_d2d_cfg_clk",   "clk_clk_sys_cfg", CLK_SET_RATE_PARENT,
+		EIC7700_REG_OFFSET_D2D_CFG_CTRL, 31, 0, },
+
+	{ EIC7700_GATE_TCU_ACLK 			,"gate_tcu_aclk",   "clk_clk_d2ddr_aclk", CLK_SET_RATE_PARENT,
+		EIC7700_REG_OFFSET_TCU_ACLK_CTRL, 31, 0, },
+
+	{ EIC7700_GATE_TCU_CFG_CLK			,"gate_tcu_cfg_clk",   "clk_clk_sys_cfg", CLK_SET_RATE_PARENT,
+		EIC7700_REG_OFFSET_TCU_CFG_CTRL, 31, 0, },
+
+	{ EIC7700_GATE_DDRT_CFG_CLK			,"gate_ddrt_cfg_clk",   "clk_clk_sys_cfg", CLK_SET_RATE_PARENT,
+		EIC7700_REG_OFFSET_DDR_CLK_CTRL, 9, 0, },
+
+	{ EIC7700_GATE_DDRT0_P0_ACLK			,"gate_ddrt0_p0_aclk",   "clk_clk_d2ddr_aclk", CLK_SET_RATE_PARENT,
+		EIC7700_REG_OFFSET_DDR_CLK_CTRL, 4, 0, },
+
+	{ EIC7700_GATE_DDRT0_P1_ACLK			,"gate_ddrt0_p1_aclk",   "clk_clk_d2ddr_aclk", CLK_SET_RATE_PARENT,
+		EIC7700_REG_OFFSET_DDR_CLK_CTRL, 5, 0, },
+
+	{ EIC7700_GATE_DDRT0_P2_ACLK			,"gate_ddrt0_p2_aclk",   "clk_clk_d2ddr_aclk", CLK_SET_RATE_PARENT,
+		EIC7700_REG_OFFSET_DDR_CLK_CTRL, 6, 0, },
+
+	{ EIC7700_GATE_DDRT0_P3_ACLK			,"gate_ddrt0_p3_aclk",   "clk_clk_d2ddr_aclk", CLK_SET_RATE_PARENT,
+		EIC7700_REG_OFFSET_DDR_CLK_CTRL, 7, 0, },
+
+	{ EIC7700_GATE_DDRT0_P4_ACLK			,"gate_ddrt0_p4_aclk",   "clk_clk_d2ddr_aclk", CLK_SET_RATE_PARENT,
+		EIC7700_REG_OFFSET_DDR_CLK_CTRL, 8, 0, },
+
+	{ EIC7700_GATE_DDRT1_P0_ACLK			,"gate_ddrt1_p0_aclk",   "clk_clk_d2ddr_aclk", CLK_SET_RATE_PARENT,
+		EIC7700_REG_OFFSET_DDR1_CLK_CTRL, 4, 0, },
+
+	{ EIC7700_GATE_DDRT1_P1_ACLK			,"gate_ddrt1_p1_aclk",   "clk_clk_d2ddr_aclk", CLK_SET_RATE_PARENT,
+		EIC7700_REG_OFFSET_DDR1_CLK_CTRL, 5, 0, },
+
+	{ EIC7700_GATE_DDRT1_P2_ACLK			,"gate_ddrt1_p2_aclk",   "clk_clk_d2ddr_aclk", CLK_SET_RATE_PARENT,
+		EIC7700_REG_OFFSET_DDR1_CLK_CTRL, 6, 0, },
+
+	{ EIC7700_GATE_DDRT1_P3_ACLK			,"gate_ddrt1_p3_aclk",   "clk_clk_d2ddr_aclk", CLK_SET_RATE_PARENT,
+		EIC7700_REG_OFFSET_DDR1_CLK_CTRL, 7, 0, },
+
+	{ EIC7700_GATE_DDRT1_P4_ACLK			,"gate_ddrt1_p4_aclk",   "clk_clk_d2ddr_aclk", CLK_SET_RATE_PARENT,
+		EIC7700_REG_OFFSET_DDR1_CLK_CTRL, 8, 0, },
+
+	{ EIC7700_GATE_CLK_HSP_ACLK			,"gate_clk_hsp_aclk",   "divder_u_hsp_aclk_div_dynm", CLK_SET_RATE_PARENT,
+		EIC7700_REG_OFFSET_HSP_ACLK_CTRL, 31, 0, },
+
+	{ EIC7700_GATE_CLK_HSP_CFGCLK			,"gate_clk_hsp_cfgclk",   "clk_clk_sys_cfg", CLK_SET_RATE_PARENT,
+		EIC7700_REG_OFFSET_HSP_CFG_CTRL, 31, 0, },
+
+	{ EIC7700_GATE_PCIET_ACLK			,"gate_pciet_aclk",   "divder_u_pcie_aclk_div_dynm", CLK_SET_RATE_PARENT,
+		EIC7700_REG_OFFSET_PCIE_ACLK_CTRL, 31, 0, },
+
+	{ EIC7700_GATE_PCIET_CFG_CLK			,"gate_pciet_cfg_clk",   "clk_clk_sys_cfg", CLK_SET_RATE_PARENT,
+		EIC7700_REG_OFFSET_PCIE_CFG_CTRL, 31, 0, },
+
+	{ EIC7700_GATE_PCIET_CR_CLK 			,"gate_pciet_cr_clk",   "fixed_factor_u_pcie_cr_div2", CLK_SET_RATE_PARENT,
+		EIC7700_REG_OFFSET_PCIE_CFG_CTRL, 0, 0, },
+
+	{ EIC7700_GATE_PCIET_AUX_CLK			,"gate_pciet_aux_clk",   "fixed_factor_u_pcie_aux_div4", CLK_SET_RATE_PARENT,
+		EIC7700_REG_OFFSET_PCIE_CFG_CTRL, 1, 0, },
+
+	{ EIC7700_GATE_NPU_ACLK 			,"gate_npu_aclk",   "divder_u_npu_aclk_div_dynm", CLK_SET_RATE_PARENT,
+		EIC7700_REG_OFFSET_NPU_ACLK_CTRL, 31, 0, },
+
+	{ EIC7700_GATE_NPU_CFG_CLK			,"gate_npu_cfg_clk",   "clk_clk_sys_cfg", CLK_SET_RATE_PARENT,
+		EIC7700_REG_OFFSET_NPU_ACLK_CTRL, 30, 0, },
+
+	{ EIC7700_GATE_NPU_LLC_ACLK 			,"gate_npu_llc_aclk",   "mux_u_npu_llclk_3mux1_gfree", CLK_SET_RATE_PARENT,
+		EIC7700_REG_OFFSET_NPU_LLC_CTRL, 31, 0, },
+
+	{ EIC7700_GATE_NPU_CLK				,"gate_npu_clk",   "divder_u_npu_coreclk_div_dynm", CLK_SET_RATE_PARENT,
+		EIC7700_REG_OFFSET_NPU_CORE_CTRL, 31, 0, },
+
+	{ EIC7700_GATE_NPU_E31_CLK			,"gate_npu_e31_clk",   "divder_u_npu_e31_div_dynm", CLK_SET_RATE_PARENT,
+		EIC7700_REG_OFFSET_NPU_CORE_CTRL, 30, 0, },
+
+	{ EIC7700_GATE_VI_ACLK				,"gate_vi_aclk",   "clk_clk_vi_aclk_st1", CLK_SET_RATE_PARENT,
+		EIC7700_REG_OFFSET_VI_ACLK_CTRL, 31, 0, },
+
+	{ EIC7700_GATE_VI_CFG_CLK			,"gate_vi_cfg_clk",   "clk_clk_sys_cfg", CLK_SET_RATE_PARENT,
+		EIC7700_REG_OFFSET_VI_ACLK_CTRL, 30, 0, },
+
+	{ EIC7700_GATE_VI_DIG_DW_CLK			,"gate_vi_dig_dw_clk",   "divder_u_vi_dw_div_dynm", CLK_SET_RATE_PARENT,
+		EIC7700_REG_OFFSET_VI_DWCLK_CTRL, 31, 0, },
+
+	{ EIC7700_GATE_VI_DVP_CLK			,"gate_vi_dvp_clk",   "divder_u_vi_dvp_div_dynm", CLK_SET_RATE_PARENT,
+		EIC7700_REG_OFFSET_VI_DVP_CLK_CTRL, 31, 0, },
+
+	{ EIC7700_GATE_VI_DIG_ISP_CLK			,"gate_vi_dig_isp_clk",   "divder_u_vi_dig_isp_div_dynm", CLK_SET_RATE_PARENT,
+		EIC7700_REG_OFFSET_VI_DIG_ISP_CLK_CTRL, 31, 0, },
+
+	{ EIC7700_GATE_VI_SHUTTER_0			,"gate_vi_shutter_0",   "divder_u_vi_shutter_div_dynm_0", CLK_SET_RATE_PARENT,
+		EIC7700_REG_OFFSET_VI_SHUTTER0, 31, 0, },
+
+	{ EIC7700_GATE_VI_SHUTTER_1			,"gate_vi_shutter_1",   "divder_u_vi_shutter_div_dynm_1", CLK_SET_RATE_PARENT,
+		EIC7700_REG_OFFSET_VI_SHUTTER1, 31, 0, },
+
+	{ EIC7700_GATE_VI_SHUTTER_2			,"gate_vi_shutter_2",   "divder_u_vi_shutter_div_dynm_2", CLK_SET_RATE_PARENT,
+		EIC7700_REG_OFFSET_VI_SHUTTER2, 31, 0, },
+
+	{ EIC7700_GATE_VI_SHUTTER_3			,"gate_vi_shutter_3",   "divder_u_vi_shutter_div_dynm_3", CLK_SET_RATE_PARENT,
+		EIC7700_REG_OFFSET_VI_SHUTTER3, 31, 0, },
+
+	{ EIC7700_GATE_VI_SHUTTER_4			,"gate_vi_shutter_4",   "divder_u_vi_shutter_div_dynm_4", CLK_SET_RATE_PARENT,
+		EIC7700_REG_OFFSET_VI_SHUTTER4, 31, 0, },
+
+	{ EIC7700_GATE_VI_SHUTTER_5			,"gate_vi_shutter_5",   "divder_u_vi_shutter_div_dynm_5", CLK_SET_RATE_PARENT,
+		EIC7700_REG_OFFSET_VI_SHUTTER5, 31, 0, },
+
+	{ EIC7700_GATE_VI_PHY_TXCLKESC			,"gate_vi_phy_txclkesc",   "clk_clk_mipi_txesc", CLK_SET_RATE_PARENT,
+		EIC7700_REG_OFFSET_VI_PHY_CLKCTRL, 0, 0, },
+
+	{ EIC7700_GATE_VI_PHY_CFG			,"gate_vi_phy_cfg",   "fixed_rate_clk_xtal_24m", CLK_SET_RATE_PARENT,
+		EIC7700_REG_OFFSET_VI_PHY_CLKCTRL, 1, 0, },
+
+	{ EIC7700_GATE_VO_ACLK				,"gate_vo_aclk",   "divder_u_vo_aclk_div_dynm", CLK_SET_RATE_PARENT,
+		EIC7700_REG_OFFSET_VO_ACLK_CTRL, 31, 0, },
+
+	{ EIC7700_GATE_VO_CFG_CLK			,"gate_vo_cfg_clk",   "clk_clk_sys_cfg", CLK_SET_RATE_PARENT,
+		EIC7700_REG_OFFSET_VO_ACLK_CTRL, 30, 0, },
+
+	{ EIC7700_GATE_VO_HDMI_IESMCLK			,"gate_vo_hdmi_iesmclk",   "divder_u_iesmclk_div_dynm", CLK_SET_RATE_PARENT,
+		EIC7700_REG_OFFSET_VO_IESMCLK_CTRL, 31, 0, },
+
+	{ EIC7700_GATE_VO_PIXEL_CLK 			,"gate_vo_pixel_clk",   "divder_u_vo_pixel_div_dynm", CLK_SET_RATE_PARENT,
+		EIC7700_REG_OFFSET_VO_PIXEL_CTRL, 31, 0, },
+
+	{ EIC7700_GATE_VO_I2S_MCLK			,"gate_vo_i2s_mclk",   "mux_u_vo_mclk_2mux_ext_mclk", CLK_SET_RATE_PARENT,
+		EIC7700_REG_OFFSET_VO_MCLK_CTRL, 31, 0, },
+
+	{ EIC7700_GATE_VO_CR_CLK			,"gate_vo_cr_clk",   "clk_clk_mipi_txesc", CLK_SET_RATE_PARENT,
+		EIC7700_REG_OFFSET_VO_PHY_CLKCTRL, 1, 0, },
+
+	{ EIC7700_GATE_VC_ACLK				,"gate_vc_aclk",   "divder_u_vc_aclk_div_dynm", CLK_SET_RATE_PARENT,
+		EIC7700_REG_OFFSET_VC_ACLK_CTRL, 31, 0, },
+
+	{ EIC7700_GATE_VC_CFG_CLK			,"gate_vc_cfg_clk",   "clk_clk_sys_cfg", CLK_SET_RATE_PARENT,
+		EIC7700_REG_OFFSET_VC_CLKEN_CTRL, 0, 0, },
+
+	{ EIC7700_GATE_VC_JE_CLK			,"gate_vc_je_clk",   "divder_u_je_div_dynm", CLK_SET_RATE_PARENT,
+		EIC7700_REG_OFFSET_JE_CLK_CTRL, 31, 0, },
+
+	{ EIC7700_GATE_VC_JD_CLK			,"gate_vc_jd_clk",   "divder_u_jd_div_dynm", CLK_SET_RATE_PARENT,
+		EIC7700_REG_OFFSET_JD_CLK_CTRL, 31, 0, },
+
+	{ EIC7700_GATE_VC_VE_CLK			,"gate_vc_ve_clk",   "divder_u_ve_div_dynm", CLK_SET_RATE_PARENT,
+		EIC7700_REG_OFFSET_VE_CLK_CTRL, 31, 0, },
+
+	{ EIC7700_GATE_VC_VD_CLK			,"gate_vc_vd_clk",   "divder_u_vd_div_dynm", CLK_SET_RATE_PARENT,
+		EIC7700_REG_OFFSET_VD_CLK_CTRL, 31, 0, },
+
+	{ EIC7700_GATE_G2D_CFG_CLK			,"gate_g2d_cfg_clk",   "clk_clk_sys_cfg", CLK_SET_RATE_PARENT,
+		EIC7700_REG_OFFSET_G2D_CTRL, 28, 0, },
+
+	{ EIC7700_GATE_G2D_CLK				,"gate_g2d_clk",   "clk_clk_g2d_st2", CLK_SET_RATE_PARENT,
+		EIC7700_REG_OFFSET_G2D_CTRL, 30, 0, },
+
+	{ EIC7700_GATE_G2D_ACLK 			,"gate_g2d_aclk",   "clk_clk_g2d_st2", CLK_SET_RATE_PARENT,
+		EIC7700_REG_OFFSET_G2D_CTRL, 31, 0, },
+
+	{ EIC7700_GATE_CLK_AONDMA_CFG			,"gate_clk_aondma_cfg",   "clk_clk_sys_cfg", CLK_SET_RATE_PARENT,
+		EIC7700_REG_OFFSET_AON_DMA_CLK_CTRL, 30, 0, },
+
+	{ EIC7700_GATE_AONDMA_ACLK			,"gate_aondma_aclk",   "clk_clk_aondma_axi_st3", CLK_SET_RATE_PARENT,
+		EIC7700_REG_OFFSET_AON_DMA_CLK_CTRL, 31, 0, },
+
+	{ EIC7700_GATE_AON_ACLK 			,"gate_aon_aclk",   "clk_clk_aondma_axi_st3", CLK_SET_RATE_PARENT,
+		EIC7700_REG_OFFSET_AON_DMA_CLK_CTRL, 29, 0, },
+
+	{ EIC7700_GATE_TIMER_CLK_0 			,"gate_time_clk_0",   "fixed_rate_clk_xtal_24m", CLK_SET_RATE_PARENT,
+		EIC7700_REG_OFFSET_TIMER_CLK_CTRL, 0, 0, },
+
+	{ EIC7700_GATE_TIMER_CLK_1 			,"gate_time_clk_1",   "fixed_rate_clk_xtal_24m", CLK_SET_RATE_PARENT,
+		EIC7700_REG_OFFSET_TIMER_CLK_CTRL, 1, 0, },
+
+	{ EIC7700_GATE_TIMER_CLK_2 			,"gate_time_clk_2",   "fixed_rate_clk_xtal_24m", CLK_SET_RATE_PARENT,
+		EIC7700_REG_OFFSET_TIMER_CLK_CTRL, 2, 0, },
+
+	{ EIC7700_GATE_TIMER_CLK_3 			,"gate_time_clk_3",   "fixed_rate_clk_xtal_24m", CLK_SET_RATE_PARENT,
+		EIC7700_REG_OFFSET_TIMER_CLK_CTRL, 3, 0, },
+
+	{ EIC7700_GATE_TIMER_PCLK_0			,"gate_timer_pclk_0",   "clk_clk_sys_cfg", CLK_SET_RATE_PARENT,
+		EIC7700_REG_OFFSET_TIMER_CLK_CTRL, 4, 0, },
+
+	{ EIC7700_GATE_TIMER_PCLK_1			,"gate_timer_pclk_1",   "clk_clk_sys_cfg", CLK_SET_RATE_PARENT,
+		EIC7700_REG_OFFSET_TIMER_CLK_CTRL, 5, 0, },
+
+	{ EIC7700_GATE_TIMER_PCLK_2			,"gate_timer_pclk_2",   "clk_clk_sys_cfg", CLK_SET_RATE_PARENT,
+		EIC7700_REG_OFFSET_TIMER_CLK_CTRL, 6, 0, },
+
+	{ EIC7700_GATE_TIMER_PCLK_3			,"gate_timer_pclk_3",   "clk_clk_sys_cfg", CLK_SET_RATE_PARENT,
+		EIC7700_REG_OFFSET_TIMER_CLK_CTRL, 7, 0, },
+
+	{ EIC7700_GATE_TIMER3_CLK8			,"gate_timer3_clk8",   "fixed_rate_clk_vpll_fout3", CLK_SET_RATE_PARENT,
+		EIC7700_REG_OFFSET_TIMER_CLK_CTRL, 8, 0, },
+
+	{ EIC7700_GATE_CLK_RTC_CFG			,"gate_clk_rtc_cfg",   "clk_clk_sys_cfg", CLK_SET_RATE_PARENT,
+		EIC7700_REG_OFFSET_RTC_CLK_CTRL, 2, 0, },
+
+	{ EIC7700_GATE_CLK_RTC				,"gate_clk_rtc",   "divder_u_aon_rtc_div_dynm", CLK_SET_RATE_PARENT,
+		EIC7700_REG_OFFSET_RTC_CLK_CTRL, 1, 0, },
+
+	{ EIC7700_GATE_CLK_PKA_CFG			,"gate_clk_pka_cfg",   "clk_clk_sys_cfg", CLK_SET_RATE_PARENT,
+		EIC7700_REG_OFFSET_PKA_CLK_CTRL, 31, 0, },
+
+	{ EIC7700_GATE_CLK_SPACC_CFG			,"gate_clk_spacc_cfg",   "clk_clk_sys_cfg", CLK_SET_RATE_PARENT,
+		EIC7700_REG_OFFSET_SPACC_CLK_CTRL, 31, 0, },
+
+	{ EIC7700_GATE_CLK_CRYPTO			,"gate_clk_crypto",   "divder_u_crypto_div_dynm", CLK_SET_RATE_PARENT,
+		EIC7700_REG_OFFSET_SPACC_CLK_CTRL, 30, 0, },
+
+	{ EIC7700_GATE_CLK_TRNG_CFG 			,"gate_clk_trng_cfg",   "clk_clk_sys_cfg", CLK_SET_RATE_PARENT,
+		EIC7700_REG_OFFSET_TRNG_CLK_CTRL, 31, 0, },
+
+	{ EIC7700_GATE_CLK_OTP_CFG			,"gate_clk_otp_cfg",   "clk_clk_sys_cfg", CLK_SET_RATE_PARENT,
+		EIC7700_REG_OFFSET_OTP_CLK_CTRL, 31, 0, },
+
+	{ EIC7700_GATE_CLK_MAILBOX_0			,"gate_clk_mailbox_0",   "clk_clk_sys_cfg", CLK_SET_RATE_PARENT,
+		EIC7700_REG_OFFSET_LSP_CLK_EN1, 0, 0, },
+
+	{ EIC7700_GATE_CLK_MAILBOX_1			,"gate_clk_mailbox_1",   "clk_clk_sys_cfg", CLK_SET_RATE_PARENT,
+		EIC7700_REG_OFFSET_LSP_CLK_EN1, 1, 0, },
+
+	{ EIC7700_GATE_CLK_MAILBOX_2			,"gate_clk_mailbox_2",   "clk_clk_sys_cfg", CLK_SET_RATE_PARENT,
+		EIC7700_REG_OFFSET_LSP_CLK_EN1, 2, 0, },
+
+	{ EIC7700_GATE_CLK_MAILBOX_3			,"gate_clk_mailbox_3",   "clk_clk_sys_cfg", CLK_SET_RATE_PARENT,
+		EIC7700_REG_OFFSET_LSP_CLK_EN1, 3, 0, },
+
+	{ EIC7700_GATE_CLK_MAILBOX_4			,"gate_clk_mailbox_4",   "clk_clk_sys_cfg", CLK_SET_RATE_PARENT,
+		EIC7700_REG_OFFSET_LSP_CLK_EN1, 4, 0, },
+
+	{ EIC7700_GATE_CLK_MAILBOX_5			,"gate_clk_mailbox_5",   "clk_clk_sys_cfg", CLK_SET_RATE_PARENT,
+		EIC7700_REG_OFFSET_LSP_CLK_EN1, 5, 0, },
+
+	{ EIC7700_GATE_CLK_MAILBOX_6			,"gate_clk_mailbox_6",   "clk_clk_sys_cfg", CLK_SET_RATE_PARENT,
+		EIC7700_REG_OFFSET_LSP_CLK_EN1, 6, 0, },
+
+	{ EIC7700_GATE_CLK_MAILBOX_7			,"gate_clk_mailbox_7",   "clk_clk_sys_cfg", CLK_SET_RATE_PARENT,
+		EIC7700_REG_OFFSET_LSP_CLK_EN1, 7, 0, },
+
+	{ EIC7700_GATE_CLK_MAILBOX_8			,"gate_clk_mailbox_8",   "clk_clk_sys_cfg", CLK_SET_RATE_PARENT,
+		EIC7700_REG_OFFSET_LSP_CLK_EN1, 8, 0, },
+
+	{ EIC7700_GATE_CLK_MAILBOX_9			,"gate_clk_mailbox_9",   "clk_clk_sys_cfg", CLK_SET_RATE_PARENT,
+		EIC7700_REG_OFFSET_LSP_CLK_EN1, 9, 0, },
+
+	{ EIC7700_GATE_CLK_MAILBOX_10			,"gate_clk_mailbox_10",   "clk_clk_sys_cfg", CLK_SET_RATE_PARENT,
+		EIC7700_REG_OFFSET_LSP_CLK_EN1, 10, 0, },
+
+	{ EIC7700_GATE_CLK_MAILBOX_11			,"gate_clk_mailbox_11",   "clk_clk_sys_cfg", CLK_SET_RATE_PARENT,
+		EIC7700_REG_OFFSET_LSP_CLK_EN1, 11, 0, },
+
+	{ EIC7700_GATE_CLK_MAILBOX_12			,"gate_clk_mailbox_12",   "clk_clk_sys_cfg", CLK_SET_RATE_PARENT,
+		EIC7700_REG_OFFSET_LSP_CLK_EN1, 12, 0, },
+
+	{ EIC7700_GATE_CLK_MAILBOX_13			,"gate_clk_mailbox_13",   "clk_clk_sys_cfg", CLK_SET_RATE_PARENT,
+		EIC7700_REG_OFFSET_LSP_CLK_EN1, 13, 0, },
+
+	{ EIC7700_GATE_CLK_MAILBOX_14			,"gate_clk_mailbox_14",   "clk_clk_sys_cfg", CLK_SET_RATE_PARENT,
+		EIC7700_REG_OFFSET_LSP_CLK_EN1, 14, 0, },
+
+	{ EIC7700_GATE_CLK_MAILBOX_15			,"gate_clk_mailbox_15",   "clk_clk_sys_cfg", CLK_SET_RATE_PARENT,
+		EIC7700_REG_OFFSET_LSP_CLK_EN1, 15, 0, },
+
+	{ EIC7700_GATE_LSP_I2C0_PCLK			,"gate_i2c0_pclk",   "clk_clk_sys_cfg", CLK_SET_RATE_PARENT,
+		EIC7700_REG_OFFSET_LSP_CLK_EN0, 7, 0, },
+
+	{ EIC7700_GATE_LSP_I2C1_PCLK			,"gate_i2c1_pclk",   "clk_clk_sys_cfg", CLK_SET_RATE_PARENT,
+		EIC7700_REG_OFFSET_LSP_CLK_EN0, 8, 0, },
+
+	{ EIC7700_GATE_LSP_I2C2_PCLK			,"gate_i2c2_pclk",   "clk_clk_sys_cfg", CLK_SET_RATE_PARENT,
+		EIC7700_REG_OFFSET_LSP_CLK_EN0, 9, 0, },
+
+	{ EIC7700_GATE_LSP_I2C3_PCLK			,"gate_i2c3_pclk",   "clk_clk_sys_cfg", CLK_SET_RATE_PARENT,
+		EIC7700_REG_OFFSET_LSP_CLK_EN0, 10, 0, },
+
+	{ EIC7700_GATE_LSP_I2C4_PCLK			,"gate_i2c4_pclk",   "clk_clk_sys_cfg", CLK_SET_RATE_PARENT,
+		EIC7700_REG_OFFSET_LSP_CLK_EN0, 11, 0, },
+
+	{ EIC7700_GATE_LSP_I2C5_PCLK			,"gate_i2c5_pclk",   "clk_clk_sys_cfg", CLK_SET_RATE_PARENT,
+		EIC7700_REG_OFFSET_LSP_CLK_EN0, 12, 0, },
+
+	{ EIC7700_GATE_LSP_I2C6_PCLK			,"gate_i2c6_pclk",   "clk_clk_sys_cfg", CLK_SET_RATE_PARENT,
+		EIC7700_REG_OFFSET_LSP_CLK_EN0, 13, 0, },
+
+	{ EIC7700_GATE_LSP_I2C7_PCLK			,"gate_i2c7_pclk",   "clk_clk_sys_cfg", CLK_SET_RATE_PARENT,
+		EIC7700_REG_OFFSET_LSP_CLK_EN0, 14, 0, },
+
+	{ EIC7700_GATE_LSP_I2C8_PCLK			,"gate_i2c8_pclk",   "clk_clk_sys_cfg", CLK_SET_RATE_PARENT,
+		EIC7700_REG_OFFSET_LSP_CLK_EN0, 15, 0, },
+
+	{ EIC7700_GATE_LSP_I2C9_PCLK			,"gate_i2c9_pclk",   "clk_clk_sys_cfg", CLK_SET_RATE_PARENT,
+		EIC7700_REG_OFFSET_LSP_CLK_EN0, 16, 0, },
+
+	{ EIC7700_GATE_LSP_WDT0_PCLK			,"gate_lsp_wdt0_pclk",   "clk_clk_sys_cfg", CLK_SET_RATE_PARENT,
+		EIC7700_REG_OFFSET_LSP_CLK_EN0, 28, 0, },
+
+	{ EIC7700_GATE_LSP_WDT1_PCLK			,"gate_lsp_wdt1_pclk",   "clk_clk_sys_cfg", CLK_SET_RATE_PARENT,
+		EIC7700_REG_OFFSET_LSP_CLK_EN0, 29, 0, },
+
+	{ EIC7700_GATE_LSP_WDT2_PCLK			,"gate_lsp_wdt2_pclk",   "clk_clk_sys_cfg", CLK_SET_RATE_PARENT,
+		EIC7700_REG_OFFSET_LSP_CLK_EN0, 30, 0, },
+
+	{ EIC7700_GATE_LSP_WDT3_PCLK			,"gate_lsp_wdt3_pclk",   "clk_clk_sys_cfg", CLK_SET_RATE_PARENT,
+		EIC7700_REG_OFFSET_LSP_CLK_EN0, 31, 0, },
+
+	{ EIC7700_GATE_LSP_SSI0_PCLK			,"gate_lsp_ssi0_pclk",   "clk_clk_sys_cfg", CLK_SET_RATE_PARENT,
+		EIC7700_REG_OFFSET_LSP_CLK_EN0, 26, 0, },
+
+	{ EIC7700_GATE_LSP_SSI1_PCLK			,"gate_lsp_ssi1_pclk",   "clk_clk_sys_cfg", CLK_SET_RATE_PARENT,
+		EIC7700_REG_OFFSET_LSP_CLK_EN0, 27, 0, },
+
+	{ EIC7700_GATE_LSP_UART0_PCLK			,"gate_lsp_uart0_pclk",   "clk_clk_sys_cfg", CLK_SET_RATE_PARENT,
+		EIC7700_REG_OFFSET_LSP_CLK_EN0, 17, 0, },
+
+	{ EIC7700_GATE_LSP_UART1_PCLK			,"gate_lsp_uart1_pclk",   "clk_clk_sys_cfg", CLK_SET_RATE_PARENT,
+		EIC7700_REG_OFFSET_LSP_CLK_EN0, 18, 0, },
+
+	{ EIC7700_GATE_LSP_UART2_PCLK			,"gate_lsp_uart2_pclk",   "clk_clk_sys_cfg", CLK_SET_RATE_PARENT,
+		EIC7700_REG_OFFSET_LSP_CLK_EN0, 19, 0, },
+
+	{ EIC7700_GATE_LSP_UART3_PCLK			,"gate_lsp_uart3_pclk",   "clk_clk_sys_cfg", CLK_SET_RATE_PARENT,
+		EIC7700_REG_OFFSET_LSP_CLK_EN0, 20, 0, },
+
+	{ EIC7700_GATE_LSP_UART4_PCLK			,"gate_lsp_uart4_pclk",   "clk_clk_sys_cfg", CLK_SET_RATE_PARENT,
+		EIC7700_REG_OFFSET_LSP_CLK_EN0, 21, 0, },
+
+	{ EIC7700_GATE_LSP_TIMER_PCLK			,"gate_lsp_timer_pclk",   "clk_clk_sys_cfg", CLK_SET_RATE_PARENT,
+		EIC7700_REG_OFFSET_LSP_CLK_EN0, 25, 0, },
+
+	{ EIC7700_GATE_LSP_FAN_PCLK			,"gate_lsp_fan_pclk",   "clk_clk_sys_cfg", CLK_SET_RATE_PARENT,
+		EIC7700_REG_OFFSET_LSP_CLK_EN0, 0, 0, },
+
+	{ EIC7700_GATE_LSP_PVT_PCLK			,"gate_lsp_pvt_pclk",   "clk_clk_sys_cfg", CLK_SET_RATE_PARENT,
+		EIC7700_REG_OFFSET_LSP_CLK_EN0, 1, 0, },
+
+	{ EIC7700_GATE_LSP_PVT0_CLK			,"gate_pvt0_clk",   "fixed_factor_u_pvt_div20", CLK_SET_RATE_PARENT,
+		EIC7700_REG_OFFSET_LSP_CLK_EN1, 16, 0, },
+
+	{ EIC7700_GATE_LSP_PVT1_CLK			,"gate_pvt1_clk",   "fixed_factor_u_pvt_div20", CLK_SET_RATE_PARENT,
+		EIC7700_REG_OFFSET_LSP_CLK_EN1, 17, 0, },
+
+	{ EIC7700_GATE_VC_JE_PCLK			,"gate_vc_je_pclk",   "clk_clk_sys_cfg", CLK_SET_RATE_PARENT,
+		EIC7700_REG_OFFSET_VC_CLKEN_CTRL, 2, 0, },
+
+	{ EIC7700_GATE_VC_JD_PCLK			,"gate_vc_jd_pclk",   "clk_clk_sys_cfg", CLK_SET_RATE_PARENT,
+		EIC7700_REG_OFFSET_VC_CLKEN_CTRL, 1, 0, },
+
+	{ EIC7700_GATE_VC_VE_PCLK			,"gate_vc_ve_pclk",   "clk_clk_sys_cfg", CLK_SET_RATE_PARENT,
+		EIC7700_REG_OFFSET_VC_CLKEN_CTRL, 5, 0, },
+
+	{ EIC7700_GATE_VC_VD_PCLK			,"gate_vc_vd_pclk",   "clk_clk_sys_cfg", CLK_SET_RATE_PARENT,
+		EIC7700_REG_OFFSET_VC_CLKEN_CTRL, 4, 0, },
+
+	{ EIC7700_GATE_VC_MON_PCLK			,"gate_vc_mon_pclk",   "clk_clk_sys_cfg", CLK_SET_RATE_PARENT,
+		EIC7700_REG_OFFSET_VC_CLKEN_CTRL, 3, 0, },
+
+	{ EIC7700_GATE_HSP_MSHC0_CORE_CLK		,"gate_hsp_mshc0_core_clk",   "divder_u_mshc_core_div_dynm_0", CLK_SET_RATE_PARENT,
+		EIC7700_REG_OFFSET_MSHC0_CORECLK_CTRL, 16, 0, },
+
+	{ EIC7700_GATE_HSP_MSHC1_CORE_CLK		,"gate_hsp_mshc1_core_clk",   "divder_u_mshc_core_div_dynm_1", CLK_SET_RATE_PARENT,
+		EIC7700_REG_OFFSET_MSHC1_CORECLK_CTRL, 16, 0, },
+
+	{ EIC7700_GATE_HSP_MSHC2_CORE_CLK		,"gate_hsp_mshc2_core_clk",   "divder_u_mshc_core_div_dynm_2", CLK_SET_RATE_PARENT,
+		EIC7700_REG_OFFSET_MSHC2_CORECLK_CTRL, 16, 0, },
+
+	{ EIC7700_GATE_HSP_SATA_RBC_CLK			,"gate_hsp_sata_rbc_clk",   "fixed_rate_clk_spll1_fout2", CLK_SET_RATE_PARENT,
+		EIC7700_REG_OFFSET_SATA_RBC_CTRL, 0, 0, },
+
+	{ EIC7700_GATE_HSP_SATA_OOB_CLK			,"gate_hsp_sata_oob_clk",   "mux_u_sata_phy_2mux1", CLK_SET_RATE_PARENT,
+		EIC7700_REG_OFFSET_SATA_OOB_CTRL, 31, 0, },
+
+	{ EIC7700_GATE_HSP_DMA0_CLK			,"gate_hsp_dma0_clk",   "gate_clk_hsp_aclk", CLK_SET_RATE_PARENT,
+		EIC7700_REG_OFFSET_HSP_ACLK_CTRL, 0, 0, },
+
+	{ EIC7700_GATE_HSP_ETH0_CORE_CLK		,"gate_hsp_eth0_core_clk",   "divder_u_eth_txclk_div_dynm_0", CLK_SET_RATE_PARENT,
+		EIC7700_REG_OFFSET_ETH0_CTRL, 0, 0, },
+
+	{ EIC7700_GATE_HSP_ETH1_CORE_CLK		,"gate_hsp_eth1_core_clk",   "divder_u_eth_txclk_div_dynm_1", CLK_SET_RATE_PARENT,
+		EIC7700_REG_OFFSET_ETH1_CTRL, 0, 0, },
+
+	{ EIC7700_GATE_HSP_RMII_REF_0			,"gate_hsp_rmii_ref_0",   "mux_u_rmii_ref_2mux1", CLK_SET_RATE_PARENT,
+		EIC7700_REG_OFFSET_ETH0_CTRL, 31, 0, },
+
+	{ EIC7700_GATE_HSP_RMII_REF_1			,"gate_hsp_rmii_ref_1",   "mux_u_rmii_ref_2mux1", CLK_SET_RATE_PARENT,
+		EIC7700_REG_OFFSET_ETH1_CTRL, 31, 0, },
+
+	{ EIC7700_GATE_AON_I2C0_PCLK			,"gate_aon_i2c0_pclk",   "clk_clk_sys_cfg", CLK_SET_RATE_PARENT,
+		EIC7700_REG_OFFSET_I2C0_CLK_CTRL, 31, 0, },
+
+	{ EIC7700_GATE_AON_I2C1_PCLK			,"gate_aon_i2c1_pclk",   "clk_clk_sys_cfg", CLK_SET_RATE_PARENT,
+		EIC7700_REG_OFFSET_I2C1_CLK_CTRL, 31, 0, },
+};
+
+/* eic7700 clocks */
+static struct eswin_clock eic7700_clks[] = {
+	{  EIC7700_CLK_CPU_EXT_SRC_CORE_CLK_0	,"clk_cpu_ext_src_core_clk_0",	"gate_clk_cpu_ext_src_core_clk_0", CLK_SET_RATE_PARENT,},
+	{  EIC7700_CLK_CPU_EXT_SRC_CORE_CLK_1	,"clk_cpu_ext_src_core_clk_1",	"gate_clk_cpu_ext_src_core_clk_1", CLK_SET_RATE_PARENT,},
+	{  EIC7700_CLK_CPU_EXT_SRC_CORE_CLK_2	,"clk_cpu_ext_src_core_clk_2",	"gate_clk_cpu_ext_src_core_clk_2", CLK_SET_RATE_PARENT,},
+	{  EIC7700_CLK_CPU_EXT_SRC_CORE_CLK_3	,"clk_cpu_ext_src_core_clk_3",	"gate_clk_cpu_ext_src_core_clk_3", CLK_SET_RATE_PARENT,},
+	{  EIC7700_CLK_CPU_TRACE_CLK_0		,"clk_cpu_trace_clk_0",	 	"gate_clk_cpu_trace_clk_0", CLK_SET_RATE_PARENT,},
+	{  EIC7700_CLK_CPU_TRACE_CLK_1		,"clk_cpu_trace_clk_1",	 	"gate_clk_cpu_trace_clk_1", CLK_SET_RATE_PARENT,},
+	{  EIC7700_CLK_CPU_TRACE_CLK_2		,"clk_cpu_trace_clk_2",	 	"gate_clk_cpu_trace_clk_2", CLK_SET_RATE_PARENT,},
+	{  EIC7700_CLK_CPU_TRACE_CLK_3		,"clk_cpu_trace_clk_3",	 	"gate_clk_cpu_trace_clk_3", CLK_SET_RATE_PARENT,},
+
+	{  EIC7700_CLK_CPU_TRACE_COM_CLK 	,"clk_cpu_trace_com_clk",	"gate_clk_cpu_trace_com_clk", CLK_SET_RATE_PARENT,},
+	{  EIC7700_CLK_CPU_CLK			,"clk_cpu_clk",			"gate_clk_cpu_clk", CLK_SET_RATE_PARENT,},
+
+	{  EIC7700_CLK_CLK_1M			,"clk_clk_1m",			"fixed_factor_u_clk_1m_div24", CLK_SET_RATE_PARENT,},
+	{  EIC7700_CLK_NOC_CFG_CLK		,"clk_noc_cfg_clk",		"clk_clk_sys_cfg", CLK_SET_RATE_PARENT,},
+	{  EIC7700_CLK_NOC_NSP_CLK		,"clk_noc_nsp_clk",		"gate_noc_nsp_clk", CLK_SET_RATE_PARENT,},
+	{  EIC7700_CLK_CLK_BOOTSPI		,"clk_clk_bootspi",		"gate_clk_bootspi", CLK_SET_RATE_PARENT,},
+	{  EIC7700_CLK_CLK_BOOTSPI_CFG		,"clk_clk_bootspi_cfg",		"gate_clk_bootspi_cfg", CLK_SET_RATE_PARENT,},
+	{  EIC7700_CLK_CLK_U84_CORE_LP		,"clk_clk_u84_core_lp",		"fixed_factor_u_u84_core_lp_div2", CLK_SET_RATE_PARENT,},
+	{  EIC7700_CLK_CLK_SCPU_CORE		,"clk_clk_scpu_core",		"gate_clk_scpu_core", CLK_SET_RATE_PARENT,},
+	{  EIC7700_CLK_CLK_SCPU_BUS 		,"clk_clk_scpu_bus",		"gate_clk_scpu_bus", CLK_SET_RATE_PARENT,},
+	{  EIC7700_CLK_CLK_LPCPU_CORE		,"clk_clk_lpcpu_core",		"gate_clk_lpcpu_core", CLK_SET_RATE_PARENT,},
+	{  EIC7700_CLK_CLK_LPCPU_BUS		,"clk_clk_lpcpu_bus",		"gate_clk_lpcpu_bus", CLK_SET_RATE_PARENT,},
+	{  EIC7700_CLK_GPU_ACLK 		,"clk_gpu_aclk",		"gate_gpu_aclk", CLK_SET_RATE_PARENT,},
+	{  EIC7700_CLK_GPU_GRAY_CLK 		,"clk_gpu_gray_clk",		"gate_gpu_gray_clk", CLK_SET_RATE_PARENT,},
+	{  EIC7700_CLK_GPU_CFG_CLK		,"clk_gpu_cfg_clk",		"gate_gpu_cfg_clk", CLK_SET_RATE_PARENT,},
+	{  EIC7700_CLK_DSPT_ACLK		,"clk_dspt_aclk",		"gate_dspt_aclk", CLK_SET_RATE_PARENT,},
+	{  EIC7700_CLK_DSPT_CFG_CLK 		,"clk_dspt_cfg_clk",		"gate_dspt_cfg_clk", CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,},
+	{  EIC7700_CLK_D2D_ACLK 		,"clk_d2d_aclk",		"gate_d2d_aclk", CLK_SET_RATE_PARENT,},
+	{  EIC7700_CLK_D2D_CFG_CLK		,"clk_d2d_cfg_clk",	 	"gate_d2d_cfg_clk", CLK_SET_RATE_PARENT,},
+	{  EIC7700_CLK_TCU_ACLK 		,"clk_tcu_aclk",		"gate_tcu_aclk", CLK_SET_RATE_PARENT,},
+	{  EIC7700_CLK_TCU_CFG_CLK		,"clk_tcu_cfg_clk",		"gate_tcu_cfg_clk", CLK_SET_RATE_PARENT,},
+	{  EIC7700_CLK_DDRT_CFG_CLK 		,"clk_ddrt_cfg_clk",		"gate_ddrt_cfg_clk", CLK_SET_RATE_PARENT,},
+	{  EIC7700_CLK_DDRT0_P0_ACLK		,"clk_ddrt0_p0_aclk",		"gate_ddrt0_p0_aclk", CLK_SET_RATE_PARENT,},
+	{  EIC7700_CLK_DDRT0_P1_ACLK		,"clk_ddrt0_p1_aclk",		"gate_ddrt0_p1_aclk", CLK_SET_RATE_PARENT,},
+	{  EIC7700_CLK_DDRT0_P2_ACLK		,"clk_ddrt0_p2_aclk",		"gate_ddrt0_p2_aclk", CLK_SET_RATE_PARENT,},
+	{  EIC7700_CLK_DDRT0_P3_ACLK		,"clk_ddrt0_p3_aclk",		"gate_ddrt0_p3_aclk", CLK_SET_RATE_PARENT,},
+	{  EIC7700_CLK_DDRT0_P4_ACLK		,"clk_ddrt0_p4_aclk",		"gate_ddrt0_p4_aclk", CLK_SET_RATE_PARENT,},
+	{  EIC7700_CLK_DDRT1_P0_ACLK		,"clk_ddrt1_p0_aclk",		"gate_ddrt1_p0_aclk", CLK_SET_RATE_PARENT,},
+	{  EIC7700_CLK_DDRT1_P1_ACLK		,"clk_ddrt1_p1_aclk",		"gate_ddrt1_p1_aclk", CLK_SET_RATE_PARENT,},
+	{  EIC7700_CLK_DDRT1_P2_ACLK		,"clk_ddrt1_p2_aclk",		"gate_ddrt1_p2_aclk", CLK_SET_RATE_PARENT,},
+	{  EIC7700_CLK_DDRT1_P3_ACLK		,"clk_ddrt1_p3_aclk",		"gate_ddrt1_p3_aclk", CLK_SET_RATE_PARENT,},
+	{  EIC7700_CLK_DDRT1_P4_ACLK		,"clk_ddrt1_p4_aclk",		"gate_ddrt1_p4_aclk", CLK_SET_RATE_PARENT,},
+	{  EIC7700_CLK_HSP_ACLK 		,"clk_hsp_aclk",		"gate_clk_hsp_aclk", CLK_SET_RATE_PARENT,},
+	{  EIC7700_CLK_HSP_CFG_CLK		,"clk_hsp_cfg_clk",		"gate_clk_hsp_cfgclk", CLK_SET_RATE_PARENT,},
+	{  EIC7700_CLK_HSP_SATA_RBC_CLK 	,"clk_hsp_sata_rbc_clk",	"gate_hsp_sata_rbc_clk", CLK_SET_RATE_PARENT,},
+	{  EIC7700_CLK_HSP_SATA_OOB_CLK 	,"clk_hsp_sata_oob_clk",	"gate_hsp_sata_oob_clk", CLK_SET_RATE_PARENT,},
+	{  EIC7700_CLK_HSP_SATA_PHY_REF		,"clk_hsp_sata_phy_ref",	"gate_hsp_sata_oob_clk", CLK_SET_RATE_PARENT,},
+	{  EIC7700_CLK_HSP_SATA_PMALIVE_CLK 	,"clk_hsp_sata_pmalive_clk",  	"gate_hsp_sata_oob_clk", CLK_SET_RATE_PARENT,},
+	{  EIC7700_CLK_HSP_ETH_APP_CLK		,"clk_hsp_eth_app_clk",		"clk_clk_sys_cfg", CLK_SET_RATE_PARENT,},
+	{  EIC7700_CLK_HSP_ETH_CSR_CLK		,"clk_hsp_eth_csr_clk",		"clk_clk_sys_cfg", CLK_SET_RATE_PARENT,},
+	{  EIC7700_CLK_HSP_ETH0_CORE_CLK	,"clk_hsp_eth0_core_clk",	"gate_hsp_eth0_core_clk", CLK_SET_RATE_PARENT,},
+	{  EIC7700_CLK_HSP_ETH1_CORE_CLK	,"clk_hsp_eth1_core_clk",	"gate_hsp_eth1_core_clk", CLK_SET_RATE_PARENT,},
+	{  EIC7700_CLK_HSP_MSHC0_CORE_CLK	,"clk_hsp_mshc0_core_clk",	"gate_hsp_mshc0_core_clk", CLK_SET_RATE_PARENT,},
+	{  EIC7700_CLK_HSP_MSHC1_CORE_CLK	,"clk_hsp_mshc1_core_clk",	"gate_hsp_mshc1_core_clk", CLK_SET_RATE_PARENT,},
+	{  EIC7700_CLK_HSP_MSHC2_CORE_CLK	,"clk_hsp_mshc2_core_clk",	"gate_hsp_mshc2_core_clk", CLK_SET_RATE_PARENT,},
+	{  EIC7700_CLK_HSP_MSHC0_TMR_CLK	,"clk_hsp_mshc0_tmr_clk",	"clk_clk_1m", CLK_SET_RATE_PARENT,},
+	{  EIC7700_CLK_HSP_MSHC1_TMR_CLK	,"clk_hsp_mshc1_tmr_clk",	"clk_clk_1m", CLK_SET_RATE_PARENT,},
+	{  EIC7700_CLK_HSP_MSHC2_TMR_CLK	,"clk_hsp_mshc2_tmr_clk",	"clk_clk_1m", CLK_SET_RATE_PARENT,},
+	{  EIC7700_CLK_HSP_USB0_SUSPEND_CLK 	,"clk_hsp_usb0_suspend_clk",	"clk_clk_1m", CLK_SET_RATE_PARENT,},
+	{  EIC7700_CLK_HSP_USB1_SUSPEND_CLK 	,"clk_hsp_usb1_suspend_clk",	"clk_clk_1m", CLK_SET_RATE_PARENT,},
+	{  EIC7700_CLK_PCIET_ACLK		,"clk_pciet_aclk",		"gate_pciet_aclk", CLK_SET_RATE_PARENT,},
+	{  EIC7700_CLK_PCIET_CFG_CLK		,"clk_pciet_cfg_clk",		"gate_pciet_cfg_clk", CLK_SET_RATE_PARENT,},
+	{  EIC7700_CLK_PCIET_CR_CLK 		,"clk_pciet_cr_clk",		"gate_pciet_cr_clk", CLK_SET_RATE_PARENT,},
+	{  EIC7700_CLK_PCIET_AUX_CLK		,"clk_pciet_aux_clk",		"gate_pciet_aux_clk", CLK_SET_RATE_PARENT,},
+	{  EIC7700_CLK_NPU_ACLK 		,"clk_npu_aclk",		"gate_npu_aclk", CLK_SET_RATE_PARENT,},
+	{  EIC7700_CLK_NPU_CFG_CLK		,"clk_npu_cfg_clk",		"gate_npu_cfg_clk", CLK_SET_RATE_PARENT,},
+	{  EIC7700_CLK_CLK_NPU_LLC_SRC0 	,"clk_clk_npu_llc_src0",	"divder_u_npu_llc_src0_div_dynm", CLK_SET_RATE_PARENT,},
+	{  EIC7700_CLK_CLK_NPU_LLC_SRC1 	,"clk_clk_npu_llc_src1",	"divder_u_npu_llc_src1_div_dynm", CLK_SET_RATE_PARENT,},
+	{  EIC7700_CLK_NPU_LLC_ACLK 		,"clk_npu_llc_aclk",		"gate_npu_llc_aclk", CLK_SET_RATE_PARENT,},
+	{  EIC7700_CLK_NPU_CLK			,"clk_npu_clk",			"gate_npu_clk", CLK_SET_RATE_PARENT,},
+	{  EIC7700_CLK_NPU_E31_CLK		,"clk_npu_e31_clk",		"gate_npu_e31_clk", CLK_SET_RATE_PARENT,},
+	{  EIC7700_CLK_VI_ACLK			,"clk_vi_aclk",			"gate_vi_aclk", CLK_SET_RATE_PARENT,},
+	{  EIC7700_CLK_VI_DIG_DW_CLK		,"clk_vi_dig_dw_clk",		"gate_vi_dig_dw_clk", CLK_SET_RATE_PARENT,},
+	{  EIC7700_CLK_VI_CFG_CLK		,"clk_vi_cfg_clk",		"gate_vi_cfg_clk", CLK_SET_RATE_PARENT,},
+	{  EIC7700_CLK_VI_DVP_CLK		,"clk_vi_dvp_clk",		"gate_vi_dvp_clk", CLK_SET_RATE_PARENT,},
+	{  EIC7700_CLK_VI_DIG_ISP_CLK		,"clk_vi_dig_isp_clk",		"gate_vi_dig_isp_clk", CLK_SET_RATE_PARENT,},
+	{  EIC7700_CLK_VI_SHUTTER_0 		,"clk_vi_shutter_0",		"gate_vi_shutter_0", CLK_SET_RATE_PARENT,},
+	{  EIC7700_CLK_VI_SHUTTER_1 		,"clk_vi_shutter_1",		"gate_vi_shutter_1", CLK_SET_RATE_PARENT,},
+	{  EIC7700_CLK_VI_SHUTTER_2 		,"clk_vi_shutter_2",		"gate_vi_shutter_2", CLK_SET_RATE_PARENT,},
+	{  EIC7700_CLK_VI_SHUTTER_3 		,"clk_vi_shutter_3",		"gate_vi_shutter_3", CLK_SET_RATE_PARENT,},
+	{  EIC7700_CLK_VI_SHUTTER_4 		,"clk_vi_shutter_4",		"gate_vi_shutter_4", CLK_SET_RATE_PARENT,},
+	{  EIC7700_CLK_VI_SHUTTER_5 		,"clk_vi_shutter_5",		"gate_vi_shutter_5", CLK_SET_RATE_PARENT,},
+	{  EIC7700_CLK_VI_PHY_TXCLKESC		,"clk_vi_phy_txclkesc",		"gate_vi_phy_txclkesc", CLK_SET_RATE_PARENT,},
+	{  EIC7700_CLK_VI_PHY_CFG		,"clk_vi_phy_cfg",		"gate_vi_phy_cfg", CLK_SET_RATE_PARENT,},
+	{  EIC7700_CLK_VO_ACLK			,"clk_vo_aclk",			"gate_vo_aclk", CLK_SET_RATE_PARENT,},
+	{  EIC7700_CLK_VO_CFG_CLK		,"clk_vo_cfg_clk",		"gate_vo_cfg_clk", CLK_SET_RATE_PARENT,},
+	{  EIC7700_CLK_VO_HDMI_IESMCLK		,"clk_vo_hdmi_iesmclk",		"gate_vo_hdmi_iesmclk", CLK_SET_RATE_PARENT,},
+	{  EIC7700_CLK_VO_PIXEL_CLK 		,"clk_vo_pixel_clk",		"gate_vo_pixel_clk", CLK_SET_RATE_PARENT,},
+	{  EIC7700_CLK_VO_I2S_MCLK		,"clk_vo_i2s_mclk",		"gate_vo_i2s_mclk", CLK_SET_RATE_PARENT,},
+	{  EIC7700_CLK_VO_CR_CLK		,"clk_vo_cr_clk",		"gate_vo_cr_clk", CLK_SET_RATE_PARENT,},
+	{  EIC7700_CLK_VO_CEC_CLK		,"clk_vo_cec_clk",		"divder_u_vo_cec_div_dynm", CLK_SET_RATE_PARENT,},
+	{  EIC7700_CLK_VC_ACLK			,"clk_vc_aclk",			"gate_vc_aclk", CLK_SET_RATE_PARENT,},
+	{  EIC7700_CLK_VC_CFG_CLK		,"clk_vc_cfg_clk",		"gate_vc_cfg_clk", CLK_SET_RATE_PARENT,},
+	{  EIC7700_CLK_VC_JE_CLK		,"clk_vc_je_clk",		"gate_vc_je_clk", CLK_SET_RATE_PARENT,},
+	{  EIC7700_CLK_VC_JD_CLK		,"clk_vc_jd_clk",		"gate_vc_jd_clk", CLK_SET_RATE_PARENT,},
+	{  EIC7700_CLK_VC_VE_CLK		,"clk_vc_ve_clk",		"gate_vc_ve_clk", CLK_SET_RATE_PARENT,},
+	{  EIC7700_CLK_VC_VD_CLK		,"clk_vc_vd_clk",		"gate_vc_vd_clk", CLK_SET_RATE_PARENT,},
+	{  EIC7700_CLK_G2D_CFG_CLK		,"clk_g2d_cfg_clk",		"gate_g2d_cfg_clk", CLK_SET_RATE_PARENT,},
+	{  EIC7700_CLK_G2D_CLK			,"clk_g2d_clk",			"gate_g2d_clk", CLK_SET_RATE_PARENT,},
+	{  EIC7700_CLK_G2D_ACLK 		,"clk_g2d_aclk",		"gate_g2d_aclk", CLK_SET_RATE_PARENT,},
+	{  EIC7700_CLK_AONDMA_CFG		,"clk_aondma_cfg",		"gate_clk_aondma_cfg", CLK_SET_RATE_PARENT,},
+	{  EIC7700_CLK_AONDMA_ACLK		,"clk_aondma_aclk",		"gate_aondma_aclk", CLK_SET_RATE_PARENT,},
+	{  EIC7700_CLK_AON_ACLK 		,"clk_aon_aclk",		"gate_aon_aclk", CLK_SET_RATE_PARENT,},
+	{  EIC7700_CLK_TIMER_CLK_0 		,"clk_timer_clk_0",		"gate_time_clk_0", CLK_SET_RATE_PARENT,},
+	{  EIC7700_CLK_TIMER_CLK_1 		,"clk_timer_clk_1",		"gate_time_clk_1", CLK_SET_RATE_PARENT,},
+	{  EIC7700_CLK_TIMER_CLK_2 		,"clk_timer_clk_2",		"gate_time_clk_2", CLK_SET_RATE_PARENT,},
+	{  EIC7700_CLK_TIMER_CLK_3 		,"clk_timer_clk_3",		"gate_time_clk_3", CLK_SET_RATE_PARENT,},
+	{  EIC7700_CLK_TIMER_PCLK_0		,"clk_timer_pclk_0",		"gate_timer_pclk_0", CLK_SET_RATE_PARENT,},
+	{  EIC7700_CLK_TIMER_PCLK_1		,"clk_timer_pclk_1",		"gate_timer_pclk_1", CLK_SET_RATE_PARENT,},
+	{  EIC7700_CLK_TIMER_PCLK_2		,"clk_timer_pclk_2",		"gate_timer_pclk_2", CLK_SET_RATE_PARENT,},
+	{  EIC7700_CLK_TIMER_PCLK_3		,"clk_timer_pclk_3",		"gate_timer_pclk_3", CLK_SET_RATE_PARENT,},
+	{  EIC7700_CLK_TIMER3_CLK8		,"clk_timer3_clk8",		"gate_timer3_clk8", CLK_SET_RATE_PARENT,},
+	{  EIC7700_CLK_CLK_RTC_CFG		,"clk_clk_rtc_cfg",		"gate_clk_rtc_cfg", CLK_SET_RATE_PARENT,},
+	{  EIC7700_CLK_CLK_RTC			,"clk_clk_rtc",			"gate_clk_rtc", CLK_SET_RATE_PARENT,},
+	{  EIC7700_CLK_CLK_PKA_CFG		,"clk_clk_pka_cfg",	 	"gate_clk_pka_cfg", CLK_SET_RATE_PARENT,},
+	{  EIC7700_CLK_CLK_SPACC_CFG		,"clk_clk_spacc_cfg",		"gate_clk_spacc_cfg", CLK_SET_RATE_PARENT,},
+	{  EIC7700_CLK_CLK_CRYPTO		,"clk_clk_crypto",		"gate_clk_crypto", CLK_SET_RATE_PARENT,},
+	{  EIC7700_CLK_CLK_TRNG_CFG 		,"clk_clk_trng_cfg",		"gate_clk_trng_cfg", CLK_SET_RATE_PARENT,},
+	{  EIC7700_CLK_CLK_OTP_CFG		,"clk_clk_otp_cfg",	 	"gate_clk_otp_cfg", CLK_SET_RATE_PARENT,},
+	{  EIC7700_CLK_CLMM_CFG_CLK 		,"clk_clmm_cfg_clk",		"clk_clk_sys_cfg", CLK_SET_RATE_PARENT,},
+	{  EIC7700_CLK_CLMM_DEB_CLK 		,"clk_clmm_deb_clk",		"clk_clk_1m", CLK_SET_RATE_PARENT,},
+	{  EIC7700_CLK_MAILBOX_0 		,"clk_mailbox0",		"gate_clk_mailbox_0", CLK_SET_RATE_PARENT,},
+	{  EIC7700_CLK_MAILBOX_1 		,"clk_mailbox1",		"gate_clk_mailbox_1", CLK_SET_RATE_PARENT,},
+	{  EIC7700_CLK_MAILBOX_2 		,"clk_mailbox2",		"gate_clk_mailbox_2", CLK_SET_RATE_PARENT,},
+	{  EIC7700_CLK_MAILBOX_3 		,"clk_mailbox3",		"gate_clk_mailbox_3", CLK_SET_RATE_PARENT,},
+	{  EIC7700_CLK_MAILBOX_4 		,"clk_mailbox4",		"gate_clk_mailbox_4", CLK_SET_RATE_PARENT,},
+	{  EIC7700_CLK_MAILBOX_5 		,"clk_mailbox5",		"gate_clk_mailbox_5", CLK_SET_RATE_PARENT,},
+	{  EIC7700_CLK_MAILBOX_6 		,"clk_mailbox6",		"gate_clk_mailbox_6", CLK_SET_RATE_PARENT,},
+	{  EIC7700_CLK_MAILBOX_7 		,"clk_mailbox7",		"gate_clk_mailbox_7", CLK_SET_RATE_PARENT,},
+	{  EIC7700_CLK_MAILBOX_8 		,"clk_mailbox8",		"gate_clk_mailbox_8", CLK_SET_RATE_PARENT,},
+	{  EIC7700_CLK_MAILBOX_9 		,"clk_mailbox9",		"gate_clk_mailbox_9", CLK_SET_RATE_PARENT,},
+	{  EIC7700_CLK_MAILBOX_10 		,"clk_mailbox10",		"gate_clk_mailbox_10", CLK_SET_RATE_PARENT,},
+	{  EIC7700_CLK_MAILBOX_11 		,"clk_mailbox11",		"gate_clk_mailbox_11", CLK_SET_RATE_PARENT,},
+	{  EIC7700_CLK_MAILBOX_12 		,"clk_mailbox12",		"gate_clk_mailbox_12", CLK_SET_RATE_PARENT,},
+	{  EIC7700_CLK_MAILBOX_13 		,"clk_mailbox13",		"gate_clk_mailbox_13", CLK_SET_RATE_PARENT,},
+	{  EIC7700_CLK_MAILBOX_14 		,"clk_mailbox14",		"gate_clk_mailbox_14", CLK_SET_RATE_PARENT,},
+	{  EIC7700_CLK_MAILBOX_15 		,"clk_mailbox15",		"gate_clk_mailbox_15", CLK_SET_RATE_PARENT,},
+	{  EIC7700_CLK_LSP_I2C0_PCLK		,"clk_i2c0_pclk",		"gate_i2c0_pclk", CLK_SET_RATE_PARENT,},
+	{  EIC7700_CLK_LSP_I2C1_PCLK		,"clk_i2c1_pclk",		"gate_i2c1_pclk", CLK_SET_RATE_PARENT,},
+	{  EIC7700_CLK_LSP_I2C2_PCLK		,"clk_i2c2_pclk",		"gate_i2c2_pclk", CLK_SET_RATE_PARENT,},
+	{  EIC7700_CLK_LSP_I2C3_PCLK		,"clk_i2c3_pclk",		"gate_i2c3_pclk", CLK_SET_RATE_PARENT,},
+	{  EIC7700_CLK_LSP_I2C4_PCLK		,"clk_i2c4_pclk",		"gate_i2c4_pclk", CLK_SET_RATE_PARENT,},
+	{  EIC7700_CLK_LSP_I2C5_PCLK		,"clk_i2c5_pclk",		"gate_i2c5_pclk", CLK_SET_RATE_PARENT,},
+	{  EIC7700_CLK_LSP_I2C6_PCLK		,"clk_i2c6_pclk",		"gate_i2c6_pclk", CLK_SET_RATE_PARENT,},
+	{  EIC7700_CLK_LSP_I2C7_PCLK		,"clk_i2c7_pclk",		"gate_i2c7_pclk", CLK_SET_RATE_PARENT,},
+	{  EIC7700_CLK_LSP_I2C8_PCLK		,"clk_i2c8_pclk",		"gate_i2c8_pclk", CLK_SET_RATE_PARENT,},
+	{  EIC7700_CLK_LSP_I2C9_PCLK		,"clk_i2c9_pclk",		"gate_i2c9_pclk", CLK_SET_RATE_PARENT,},
+
+	{  EIC7700_CLK_LSP_WDT0_PCLK		,"clk_lsp_wdt0_pclk",		"gate_lsp_wdt0_pclk", CLK_SET_RATE_PARENT,},
+	{  EIC7700_CLK_LSP_WDT1_PCLK		,"clk_lsp_wdt1_pclk",		"gate_lsp_wdt1_pclk", CLK_SET_RATE_PARENT,},
+	{  EIC7700_CLK_LSP_WDT2_PCLK		,"clk_lsp_wdt2_pclk",		"gate_lsp_wdt2_pclk", CLK_SET_RATE_PARENT,},
+	{  EIC7700_CLK_LSP_WDT3_PCLK		,"clk_lsp_wdt3_pclk",		"gate_lsp_wdt3_pclk", CLK_SET_RATE_PARENT,},
+	{  EIC7700_CLK_LSP_SSI0_PCLK		,"clk_lsp_ssi0_pclk",		"gate_lsp_ssi0_pclk", CLK_SET_RATE_PARENT,},
+	{  EIC7700_CLK_LSP_SSI1_PCLK		,"clk_lsp_ssi1_pclk",		"gate_lsp_ssi1_pclk", CLK_SET_RATE_PARENT,},
+	{  EIC7700_CLK_LSP_UART0_PCLK		,"clk_lsp_uart0_pclk",		"gate_lsp_uart0_pclk", CLK_SET_RATE_PARENT,},
+	{  EIC7700_CLK_LSP_UART1_PCLK		,"clk_lsp_uart1_pclk",		"gate_lsp_uart1_pclk", CLK_SET_RATE_PARENT,},
+	{  EIC7700_CLK_LSP_UART2_PCLK		,"clk_lsp_uart2_pclk",		"gate_lsp_uart2_pclk", CLK_SET_RATE_PARENT,},
+	{  EIC7700_CLK_LSP_UART3_PCLK		,"clk_lsp_uart3_pclk",		"gate_lsp_uart3_pclk", CLK_SET_RATE_PARENT,},
+	{  EIC7700_CLK_LSP_UART4_PCLK		,"clk_lsp_uart4_pclk",		"gate_lsp_uart4_pclk", CLK_SET_RATE_PARENT,},
+	{  EIC7700_CLK_LSP_TIMER_PCLK		,"clk_lsp_timer_pclk",		"gate_lsp_timer_pclk", CLK_SET_RATE_PARENT,},
+	{  EIC7700_CLK_LSP_FAN_PCLK		,"clk_lsp_fan_pclk",		"gate_lsp_fan_pclk", CLK_SET_RATE_PARENT,},
+	{  EIC7700_CLK_LSP_PVT_PCLK		,"clk_lsp_pvt_pclk",		"gate_lsp_pvt_pclk", CLK_SET_RATE_PARENT,},
+	{  EIC7700_CLK_PVT_CLK_0		,"clk_pvt0_clk",		"gate_pvt0_clk", CLK_SET_RATE_PARENT,},
+	{  EIC7700_CLK_PVT_CLK_1		,"clk_pvt1_clk",		"gate_pvt1_clk", CLK_SET_RATE_PARENT,},
+	{  EIC7700_CLK_VC_JE_PCLK		,"clk_vc_je_pclk",		"gate_vc_je_pclk", CLK_SET_RATE_PARENT,},
+	{  EIC7700_CLK_VC_JD_PCLK		,"clk_vc_jd_pclk",		"gate_vc_jd_pclk", CLK_SET_RATE_PARENT,},
+	{  EIC7700_CLK_VC_VE_PCLK		,"clk_vc_ve_pclk",		"gate_vc_ve_pclk", CLK_SET_RATE_PARENT,},
+	{  EIC7700_CLK_VC_VD_PCLK		,"clk_vc_vd_pclk",		"gate_vc_vd_pclk", CLK_SET_RATE_PARENT,},
+	{  EIC7700_CLK_VC_MON_PCLK		,"clk_vc_mon_pclk",		"gate_vc_mon_pclk", CLK_SET_RATE_PARENT,},
+
+	{  EIC7700_CLK_HSP_DMA0_CLK		,"clk_hsp_dma0_clk",		"gate_hsp_dma0_clk", CLK_SET_RATE_PARENT,},
+	{  EIC7700_CLK_HSP_RMII_REF_0		,"clk_hsp_rmii_ref_0",		"gate_hsp_rmii_ref_0", CLK_SET_RATE_PARENT,},
+	{  EIC7700_CLK_HSP_RMII_REF_1		,"clk_hsp_rmii_ref_1",		"gate_hsp_rmii_ref_1", CLK_SET_RATE_PARENT,},
+
+	{  EIC7700_CLK_DSP_ACLK_0		,"clk_dsp_aclk_0",	"divder_u_dsp_0_aclk_div_dynm", CLK_SET_RATE_PARENT,},
+	{  EIC7700_CLK_DSP_ACLK_1		,"clk_dsp_aclk_1",	"divder_u_dsp_1_aclk_div_dynm", CLK_SET_RATE_PARENT,},
+	{  EIC7700_CLK_DSP_ACLK_2		,"clk_dsp_aclk_2",	"divder_u_dsp_2_aclk_div_dynm", CLK_SET_RATE_PARENT,},
+	{  EIC7700_CLK_DSP_ACLK_3		,"clk_dsp_aclk_3",	"divder_u_dsp_3_aclk_div_dynm", CLK_SET_RATE_PARENT,},
+	{  EIC7700_CLK_CLK_U84_RTC_TOGGLE		,"clk_clk_u84_rtc_toggle",	"divder_u_u84_rtc_toggle_dynm", CLK_SET_RATE_PARENT,},
+
+	{  EIC7700_CLK_AON_I2C0_PCLK		,"clk_aon_i2c0_pclk",	"gate_aon_i2c0_pclk", CLK_SET_RATE_PARENT,},
+	{  EIC7700_CLK_AON_I2C1_PCLK		,"clk_aon_i2c1_pclk",	"gate_aon_i2c1_pclk", CLK_SET_RATE_PARENT,},
+};
+
+static void special_div_table_init(struct clk_div_table *table, int table_size)
+{
+	int i;
+
+	if (table_size < 3) {
+		return;
+	}
+	if (!table) {
+		return;
+	}
+	/*The hardware decides vaule 0, 1 and 2 both means 2 divsor*/
+	for (i = 0; i < 3; i++) {
+		table[i].val = i;
+		table[i].div = 2;
+	}
+	for (i = 3; i < table_size; i++) {
+		table[i].val = i;
+		table[i].div = i;
+	}
+	return;
+}
+
+static int eswin_clk_probe(struct platform_device *pdev)
+{
+	struct eswin_clock_data *clk_data;
+
+	clk_data = eswin_clk_init(pdev, EIC7700_NR_CLKS);
+	if (!clk_data)
+		return -EAGAIN;
+
+	/* -1 to exclude sentinel index from initialization */
+	special_div_table_init(u_3_bit_special_div_table, ARRAY_SIZE(u_3_bit_special_div_table)-1);
+	special_div_table_init(u_4_bit_special_div_table, ARRAY_SIZE(u_4_bit_special_div_table)-1);
+	special_div_table_init(u_6_bit_special_div_table, ARRAY_SIZE(u_6_bit_special_div_table)-1);
+	special_div_table_init(u_7_bit_special_div_table, ARRAY_SIZE(u_7_bit_special_div_table)-1);
+	special_div_table_init(u_8_bit_special_div_table, ARRAY_SIZE(u_8_bit_special_div_table)-1);
+	special_div_table_init(u_11_bit_special_div_table, ARRAY_SIZE(u_11_bit_special_div_table)-1);
+	special_div_table_init(u_16_bit_special_div_table, ARRAY_SIZE(u_16_bit_special_div_table)-1);
+
+	eswin_clk_register_fixed_rate(eic7700_fixed_rate_clks,
+				ARRAY_SIZE(eic7700_fixed_rate_clks),
+				clk_data);
+	eswin_clk_register_pll(eic7700_pll_clks,
+			ARRAY_SIZE(eic7700_pll_clks), clk_data, &pdev->dev);
+
+	eswin_clk_register_fixed_factor(eic7700_fixed_factor_clks,
+				ARRAY_SIZE(eic7700_fixed_factor_clks),
+				clk_data);
+	eswin_clk_register_mux(eic7700_mux_clks, ARRAY_SIZE(eic7700_mux_clks),
+				clk_data);
+	eswin_clk_register_clk(eic7700_clks_early_0, ARRAY_SIZE(eic7700_clks_early_0),
+				clk_data);
+	eswin_clk_register_divider(eic7700_div_clks, ARRAY_SIZE(eic7700_div_clks),
+				clk_data);
+	eswin_clk_register_clk(eic7700_clks_early_1, ARRAY_SIZE(eic7700_clks_early_1),
+				clk_data);
+	eswin_clk_register_gate(eic7700_gate_clks, ARRAY_SIZE(eic7700_gate_clks),
+				clk_data);
+	eswin_clk_register_clk(eic7700_clks, ARRAY_SIZE(eic7700_clks), clk_data);
+	return 0;
+}
+
+static const struct of_device_id eswin_clock_dt_ids[] = {
+	 { .compatible = "eswin,eic7700-clock", },
+	 { /* sentinel */ },
+};
+
+static struct platform_driver eswin_clock_driver = {
+	.probe	= eswin_clk_probe,
+	.driver = {
+		.name	= "eswin-clock",
+		.of_match_table	= eswin_clock_dt_ids,
+	},
+};
+static int __init eic7700_clk_init(void)
+{
+	return platform_driver_register(&eswin_clock_driver);
+}
+arch_initcall(eic7700_clk_init);
diff --git a/drivers/clk/eswin/clk.c b/drivers/clk/eswin/clk.c
new file mode 100644
index 000000000000..667ffa782bcd
--- /dev/null
+++ b/drivers/clk/eswin/clk.c
@@ -0,0 +1,915 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * ESWIN Clk Provider Driver
+ *
+ * Copyright 2024, Beijing ESWIN Computing Technology Co., Ltd.. All rights reserved.
+ * SPDX-License-Identifier: GPL-2.0
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, version 2.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <https://www.gnu.org/licenses/>.
+ *
+ * Authors: HuangYiFeng<huangyifeng@eswincomputing.com>
+ */
+
+#include <linux/clkdev.h>
+#include <linux/clk-provider.h>
+#include <linux/io.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_device.h>
+#include <linux/slab.h>
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/util_macros.h>
+#include <dt-bindings/clock/eic7700-clock.h>
+
+#include "clk.h"
+
+static struct clk_hw *eswin_clk_find_parent(struct eswin_clock_data *data, char *parent_name)
+{
+	int i;
+	struct clk *clks;
+
+	for (i = 0; i < data->clk_data.clk_num; i++) {
+		clks = data->clk_data.clks[i];
+		if (NULL == clks) {
+			continue;
+		}
+		if (!strcmp(__clk_get_name(clks), parent_name)) {
+			return __clk_get_hw(clks);
+		}
+	}
+	return NULL;
+}
+
+struct eswin_clock_data *eswin_clk_init(struct platform_device *pdev,
+					     int nr_clks)
+{
+	struct eswin_clock_data *clk_data;
+	struct clk **clk_table;
+	void __iomem *base;
+	struct device *parent;
+
+	parent = pdev->dev.parent;
+	if (!parent) {
+		dev_err(&pdev->dev, "no parent\n");
+		goto err;
+	}
+
+	base = of_iomap(parent->of_node, 0);
+	if (!base) {
+		dev_err(&pdev->dev,"failed to map clock registers\n");
+		goto err;
+	}
+	clk_data = kzalloc(sizeof(*clk_data), GFP_KERNEL);
+	if (!clk_data)
+		goto err;
+
+	clk_data->base = base;
+	clk_table = kcalloc(nr_clks, sizeof(*clk_table), GFP_KERNEL);
+	if (!clk_table)
+		goto err_data;
+
+	clk_data->clk_data.clks = clk_table;
+	clk_data->clk_data.clk_num = nr_clks;
+	clk_data->numa_id = dev_to_node(parent);
+	spin_lock_init(&clk_data->lock);
+
+	of_clk_add_provider(pdev->dev.of_node, of_clk_src_onecell_get, &clk_data->clk_data);
+	return clk_data;
+
+err_data:
+	kfree(clk_data);
+err:
+	return NULL;
+}
+EXPORT_SYMBOL_GPL(eswin_clk_init);
+
+int eswin_clk_register_fixed_rate(const struct eswin_fixed_rate_clock *clks,
+					 int nums, struct eswin_clock_data *data)
+{
+	struct clk *clk;
+	int i;
+
+	for (i = 0; i < nums; i++) {
+		char *name = kzalloc(strlen(clks[i].name) + 2 * sizeof(char) + sizeof(int),
+			GFP_KERNEL );
+		if (data->numa_id < 0) {
+			sprintf(name, "%s", clks[i].name);
+		} else {
+			sprintf(name, "d%d_%s", data->numa_id, clks[i].name);
+		}
+		clk = clk_register_fixed_rate(NULL, name, clks[i].parent_name,
+				clks[i].flags, clks[i].fixed_rate);
+		if (IS_ERR(clk)) {
+			pr_err("%s: failed to register clock %s\n", __func__, name);
+			kfree(name);
+			goto err;
+		}
+		data->clk_data.clks[clks[i].id] = clk;
+		kfree(name);
+	}
+
+	return 0;
+err:
+	while (i--)
+		clk_unregister_fixed_rate(data->clk_data.clks[clks[i].id]);
+
+	return PTR_ERR(clk);
+}
+EXPORT_SYMBOL_GPL(eswin_clk_register_fixed_rate);
+
+static int eswin_calc_pll(u32 *frac_val, u32 *postdiv1_val,
+				 u32 *fbdiv_val, u32 *refdiv_val, u64 rate,
+				 const struct eswin_clk_pll *clk)
+{
+	int ret = 0;
+
+	switch (clk->id) {
+		case EIC7700_APLL_FOUT1:
+			switch (rate) {
+				case APLL_LOW_FREQ:
+					*frac_val = 10603200;
+					*postdiv1_val = 0;
+					*fbdiv_val = 37;
+					*refdiv_val = 1;
+					break;
+				case APLL_HIGH_FREQ:
+				default:
+					*frac_val = 14092861;
+					*postdiv1_val = 0;
+					*fbdiv_val = 163;
+					*refdiv_val = 1;
+					break;
+			}
+			break;
+		case EIC7700_PLL_CPU:
+			switch (rate) {
+				case CLK_FREQ_1800M:
+					*frac_val = 0;
+					*postdiv1_val = 0;
+					*fbdiv_val = 300;
+					*refdiv_val = 1;
+					break;
+				case CLK_FREQ_1700M:
+					*frac_val = 5592405;
+					*postdiv1_val = 0;
+					*fbdiv_val = 283;
+					*refdiv_val = 1;
+					break;
+				case CLK_FREQ_1600M:
+					*frac_val = 11184810;
+					*postdiv1_val = 0;
+					*fbdiv_val = 266;
+					*refdiv_val = 1;
+					break;
+				case CLK_FREQ_1500M:
+					*frac_val = 0;
+					*postdiv1_val = 0;
+					*fbdiv_val = 250;
+					*refdiv_val = 1;
+					break;
+				case CLK_FREQ_1300M:
+					*frac_val = 11184810;
+					*postdiv1_val = 0;
+					*fbdiv_val = 216;
+					*refdiv_val = 1;
+					break;
+				case CLK_FREQ_1200M:
+					*frac_val = 0;
+					*postdiv1_val = 0;
+					*fbdiv_val = 200;
+					*refdiv_val = 1;
+					break;
+				case CLK_FREQ_1000M:
+					*frac_val = 11184810;
+					*postdiv1_val = 0;
+					*fbdiv_val = 166;
+					*refdiv_val = 1;
+					break;
+				case CLK_FREQ_900M:
+					*frac_val = 0;
+					*postdiv1_val = 0;
+					*fbdiv_val = 150;
+					*refdiv_val = 1;
+					break;
+				case CLK_FREQ_800M:
+					*frac_val = 5592405;
+					*postdiv1_val = 0;
+					*fbdiv_val = 133;
+					*refdiv_val = 1;
+					break;
+				case CLK_FREQ_700M:
+					*frac_val = 11184810;
+					*postdiv1_val = 0;
+					*fbdiv_val = 116;
+					*refdiv_val = 1;
+					break;
+				case CLK_FREQ_600M:
+					*frac_val = 0;
+					*postdiv1_val = 0;
+					*fbdiv_val = 100;
+					*refdiv_val = 1;
+					break;
+				case CLK_FREQ_500M:
+					*frac_val = 5592405;
+					*postdiv1_val = 0;
+					*fbdiv_val = 83;
+					*refdiv_val = 1;
+					break;
+				case CLK_FREQ_400M:
+					*frac_val = 11184810;
+					*postdiv1_val = 0;
+					*fbdiv_val = 66;
+					*refdiv_val = 1;
+					break;
+				case CLK_FREQ_200M:
+					*frac_val = 5592405;
+					*postdiv1_val = 0;
+					*fbdiv_val = 33;
+					*refdiv_val = 1;
+					break;
+				case CLK_FREQ_100M:
+					*frac_val = 11184810;
+					*postdiv1_val = 0;
+					*fbdiv_val = 16;
+					*refdiv_val = 1;
+					break;
+				case CLK_FREQ_1400M:
+				default:
+					*frac_val = 5592405;
+					*postdiv1_val = 0;
+					*fbdiv_val = 233;
+					*refdiv_val = 1;
+					break;
+			}
+			break;
+		default:
+			ret = -EINVAL;
+			pr_err("%s %d, Invalid pll set req, rate %lld, clk id %d\n", __func__, __LINE__, rate, clk->id);
+			break;
+	}
+	return ret;
+}
+
+#define to_pll_clk(_hw) container_of(_hw, struct eswin_clk_pll, hw)
+static int clk_pll_set_rate(struct clk_hw *hw,
+			    unsigned long rate,
+			    unsigned long parent_rate)
+{
+	struct eswin_clk_pll *clk = to_pll_clk(hw);
+	u32 frac_val = 0, postdiv1_val, fbdiv_val, refdiv_val;
+	u32 val;
+	int ret;
+	struct clk *clk_cpu_mux = NULL;
+	struct clk *clk_cpu_lp_pll = NULL;
+	struct clk *clk_cpu_pll = NULL;
+	int try_count = 0;
+	bool lock_flag = false;
+	char clk_cpu_mux_name[50] = {0};
+	char clk_cpu_lp_pll_name[50] = {0};
+	char clk_cpu_pll_name[50] = {0};
+
+	ret = eswin_calc_pll(&frac_val, &postdiv1_val, &fbdiv_val, &refdiv_val, (u64)rate, clk);
+	if (ret) {
+		return ret;
+	}
+
+	/*
+	  we must switch the cpu to other clk before we change the cpu pll
+	*/
+	if (EIC7700_PLL_CPU == clk->id) {
+		if (clk->numa_id < 0) {
+			sprintf(clk_cpu_mux_name, "%s", "mux_u_cpu_root_3mux1_gfree");
+			sprintf(clk_cpu_lp_pll_name, "%s", "clk_clk_u84_core_lp");
+			sprintf(clk_cpu_pll_name, "%s", "clk_pll_cpu");
+		} else {
+			sprintf(clk_cpu_mux_name, "d%d_%s", clk->numa_id, "mux_u_cpu_root_3mux1_gfree");
+			sprintf(clk_cpu_lp_pll_name, "d%d_%s", clk->numa_id, "clk_clk_u84_core_lp");
+			sprintf(clk_cpu_pll_name, "d%d_%s", clk->numa_id, "clk_pll_cpu");
+		}
+
+		clk_cpu_mux = __clk_lookup(clk_cpu_mux_name);
+		if (!clk_cpu_mux) {
+			pr_err("%s %d, failed to get %s\n",__func__,__LINE__, clk_cpu_mux_name);
+			return -EINVAL;
+		}
+		clk_cpu_lp_pll = __clk_lookup(clk_cpu_lp_pll_name);
+		if (!clk_cpu_lp_pll) {
+			pr_err("%s %d, failed to get %s\n",__func__,__LINE__, clk_cpu_lp_pll_name);
+			return -EINVAL;
+		}
+		clk_cpu_pll = __clk_lookup(clk_cpu_pll_name);
+		if (!clk_cpu_pll) {
+			pr_err("%s %d, failed to get %s\n",__func__,__LINE__, clk_cpu_pll_name);
+			return -EINVAL;
+		}
+
+		ret = clk_set_parent(clk_cpu_mux, clk_cpu_lp_pll);
+		if (ret) {
+			pr_err("%s %d, faild to switch %s to %s, ret %d\n",__func__,__LINE__, clk_cpu_mux_name,
+				clk_cpu_lp_pll_name, ret);
+			return -EPERM;
+		}
+	}
+
+	/*first disable pll */
+	val = readl_relaxed(clk->ctrl_reg0);
+	val &= ~(((1 << clk->pllen_width) - 1) << clk->pllen_shift);
+	val |= 0 << clk->pllen_shift;
+	writel_relaxed(val, clk->ctrl_reg0);
+
+	val = readl_relaxed(clk->ctrl_reg0);
+	val &= ~(((1 << clk->fbdiv_width) - 1) << clk->fbdiv_shift);
+	val &= ~(((1 << clk->refdiv_width) - 1) << clk->refdiv_shift);
+	val |= refdiv_val << clk->refdiv_shift;
+	val |= fbdiv_val << clk->fbdiv_shift;
+	writel_relaxed(val, clk->ctrl_reg0);
+
+	val = readl_relaxed(clk->ctrl_reg1);
+	val &= ~(((1 << clk->frac_width) - 1) << clk->frac_shift);
+	val |= frac_val << clk->frac_shift;
+	writel_relaxed(val, clk->ctrl_reg1);
+
+	val = readl_relaxed(clk->ctrl_reg2);
+	val &= ~(((1 << clk->postdiv1_width) - 1) << clk->postdiv1_shift);
+	val |= postdiv1_val << clk->postdiv1_shift;
+	writel_relaxed(val, clk->ctrl_reg2);
+
+	/*at last, enable pll */
+	val = readl_relaxed(clk->ctrl_reg0);
+	val &= ~(((1 << clk->pllen_width) - 1) << clk->pllen_shift);
+	val |= 1 << clk->pllen_shift;
+	writel_relaxed(val, clk->ctrl_reg0);
+
+	/*
+	  usually the pll wil lock in 50us
+	*/
+	do {
+		usleep_range(refdiv_val * 80, refdiv_val * 80 * 2);
+		val = readl_relaxed(clk->status_reg);
+		if (val & 1 << clk->lock_shift) {
+			lock_flag = true;
+			break;
+		}
+	} while (try_count++ < 10);
+
+	if (false == lock_flag) {
+		pr_err("%s %d, faild to lock the cpu pll, cpu will work on low power pll\n",__func__,__LINE__);
+		return -EBUSY;
+	}
+	if (EIC7700_PLL_CPU == clk->id) {
+		ret = clk_set_parent(clk_cpu_mux, clk_cpu_pll);
+		if (ret) {
+			pr_err("%s %d, faild to switch %s to %s, ret %d\n",__func__,__LINE__,
+				clk_cpu_mux_name, clk_cpu_pll_name, ret);
+			return -EPERM;
+		}
+	}
+	return  0;
+}
+
+static unsigned long clk_pll_recalc_rate(struct clk_hw *hw,
+		unsigned long parent_rate)
+{
+	struct eswin_clk_pll *clk = to_pll_clk(hw);
+	u64 frac_val, fbdiv_val, refdiv_val;
+	u32 postdiv1_val;
+	u32 val;
+	u64 rate;
+
+	val = readl_relaxed(clk->ctrl_reg0);
+	val = val >> clk->fbdiv_shift;
+	val &= ((1 << clk->fbdiv_width) - 1);
+	fbdiv_val = val;
+
+	val = readl_relaxed(clk->ctrl_reg0);
+	val = val >> clk->refdiv_shift;
+	val &= ((1 << clk->refdiv_width) - 1);
+	refdiv_val = val;
+
+	val = readl_relaxed(clk->ctrl_reg1);
+	val = val >> clk->frac_shift;
+	val &= ((1 << clk->frac_width) - 1);
+	frac_val = val;
+
+	val = readl_relaxed(clk->ctrl_reg2);
+	val = val >> clk->postdiv1_shift;
+	val &= ((1 << clk->postdiv1_width) - 1);
+	postdiv1_val = val;
+
+	switch (clk->id) {
+		case EIC7700_APLL_FOUT1:
+			switch (frac_val) {
+				case 14092861:
+					rate = APLL_HIGH_FREQ;
+					break;
+				case 10603200:
+					rate = APLL_LOW_FREQ;
+					break;
+				default:
+					pr_err("%s %d, clk id %d, unknow frac_val %llu\n", __func__, __LINE__, clk->id, frac_val);
+					rate = 0;
+					break;
+			}
+			break;
+		case EIC7700_PLL_CPU:
+			switch (fbdiv_val) {
+				case 300:
+					rate = CLK_FREQ_1800M;
+					break;
+				case 283:
+					rate = CLK_FREQ_1700M;
+					break;
+				case 266:
+					rate = CLK_FREQ_1600M;
+					break;
+				case 250:
+					rate = CLK_FREQ_1500M;
+					break;
+				case 216:
+					rate = CLK_FREQ_1300M;
+					break;
+				case 200:
+					rate = CLK_FREQ_1200M;
+					break;
+				case 166:
+					rate = CLK_FREQ_1000M;
+					break;
+				case 150:
+					rate = CLK_FREQ_900M;
+					break;
+				case 133:
+					rate = CLK_FREQ_800M;
+					break;
+				case 116:
+					rate = CLK_FREQ_700M;
+					break;
+				case 100:
+					rate = CLK_FREQ_600M;
+					break;
+				case 83:
+					rate = CLK_FREQ_500M;
+					break;
+				case 66:
+					rate = CLK_FREQ_400M;
+					break;
+				case 33:
+					rate = CLK_FREQ_200M;
+					break;
+				case 16:
+					rate = CLK_FREQ_100M;
+					break;
+				case 233:
+					rate = CLK_FREQ_1400M;
+					break;
+				default:
+					pr_err("%s %d, clk id %d, unknow fbdiv_val %llu\n", __func__, __LINE__, clk->id, fbdiv_val);
+					rate = 0;
+					break;
+			}
+			break;
+		default:
+			pr_err("%s %d, unknow clk id %d\n", __func__, __LINE__, clk->id);
+			rate = 0;
+			break;
+	}
+	return rate;
+}
+
+static long clk_pll_round_rate(struct clk_hw *hw, unsigned long rate,
+					unsigned long *parent_rate)
+{
+	struct eswin_clk_pll *clk = to_pll_clk(hw);
+	int index;
+	u64 round_rate = 0;
+
+	/*Must be sorted in ascending order*/
+	u64 apll_clk[] = {APLL_LOW_FREQ, APLL_HIGH_FREQ};
+	u64 cpu_pll_clk[] = {CLK_FREQ_100M, CLK_FREQ_200M, CLK_FREQ_400M, CLK_FREQ_500M, CLK_FREQ_600M, CLK_FREQ_700M,
+				CLK_FREQ_800M, CLK_FREQ_900M, CLK_FREQ_1000M, CLK_FREQ_1200M, CLK_FREQ_1300M,
+				CLK_FREQ_1400M, CLK_FREQ_1500M, CLK_FREQ_1600M, CLK_FREQ_1700M, CLK_FREQ_1800M};
+
+	switch (clk->id) {
+		case EIC7700_APLL_FOUT1:
+			index = find_closest(rate, apll_clk, ARRAY_SIZE(apll_clk));
+			round_rate = apll_clk[index];
+			break;
+		case EIC7700_PLL_CPU:
+			index = find_closest(rate, cpu_pll_clk, ARRAY_SIZE(cpu_pll_clk));
+			round_rate = cpu_pll_clk[index];
+			break;
+		default:
+			pr_err("%s %d, unknow clk id %d\n", __func__, __LINE__, clk->id);
+			round_rate = 0;
+			break;
+	}
+	return round_rate;
+}
+
+static const struct clk_ops eswin_clk_pll_ops = {
+	.set_rate = clk_pll_set_rate,
+	.recalc_rate = clk_pll_recalc_rate,
+	.round_rate = clk_pll_round_rate,
+};
+
+void eswin_clk_register_pll(struct eswin_pll_clock *clks,
+		int nums, struct eswin_clock_data *data, struct device *dev)
+{
+	void __iomem *base = data->base;
+	struct eswin_clk_pll *p_clk = NULL;
+	struct clk *clk = NULL;
+	struct clk_init_data init;
+	int i;
+
+	p_clk = devm_kzalloc(dev, sizeof(*p_clk) * nums, GFP_KERNEL);
+
+	if (!p_clk)
+		return;
+
+	for (i = 0; i < nums; i++) {
+		char *name = kzalloc(strlen(clks[i].name)
+			+ 2 * sizeof(char) + sizeof(int), GFP_KERNEL);
+		const char *parent_name = clks[i].parent_name ? kzalloc(strlen(clks[i].parent_name)
+			+ 2 * sizeof(char) + sizeof(int), GFP_KERNEL) : NULL;
+		if (data->numa_id < 0) {
+			sprintf(name, "%s", clks[i].name);
+			if (parent_name) {
+				sprintf((char *)parent_name, "%s", clks[i].parent_name);
+			}
+		} else {
+			sprintf(name, "d%d_%s", data->numa_id, clks[i].name);
+			if (parent_name) {
+				sprintf((char *)parent_name, "d%d_%s", data->numa_id, clks[i].parent_name);
+			}
+		}
+
+		init.name = name;
+		init.flags = 0;
+		init.parent_names = parent_name ? &parent_name : NULL;
+		init.num_parents = parent_name ? 1 : 0;
+		init.ops = &eswin_clk_pll_ops;
+
+		p_clk->id = clks[i].id;
+		p_clk->numa_id = data->numa_id;
+		p_clk->ctrl_reg0 = base + clks[i].ctrl_reg0;
+		p_clk->pllen_shift = clks[i].pllen_shift;
+		p_clk->pllen_width = clks[i].pllen_width;
+		p_clk->refdiv_shift = clks[i].refdiv_shift;
+		p_clk->refdiv_width = clks[i].refdiv_width;
+		p_clk->fbdiv_shift = clks[i].fbdiv_shift;
+		p_clk->fbdiv_width = clks[i].fbdiv_width;
+
+		p_clk->ctrl_reg1 = base + clks[i].ctrl_reg1;
+		p_clk->frac_shift = clks[i].frac_shift;
+		p_clk->frac_width = clks[i].frac_width;
+
+		p_clk->ctrl_reg2 = base + clks[i].ctrl_reg2;
+		p_clk->postdiv1_shift = clks[i].postdiv1_shift;
+		p_clk->postdiv1_width = clks[i].postdiv1_width;
+		p_clk->postdiv2_shift = clks[i].postdiv2_shift;
+		p_clk->postdiv2_width = clks[i].postdiv2_width;
+
+		p_clk->status_reg = base + clks[i].status_reg;
+		p_clk->lock_shift = clks[i].lock_shift;
+		p_clk->lock_width = clks[i].lock_width;
+
+		p_clk->hw.init = &init;
+
+		clk = clk_register(dev, &p_clk->hw);
+		if (IS_ERR(clk)) {
+			devm_kfree(dev, p_clk);
+			dev_err(dev, "%s: failed to register clock %s\n", __func__, clks[i].name);
+			continue;
+		}
+
+		data->clk_data.clks[clks[i].id] = clk;
+		p_clk++;
+		kfree(name);
+		if (parent_name) {
+			kfree(parent_name);
+		}
+	}
+}
+EXPORT_SYMBOL_GPL(eswin_clk_register_pll);
+
+int eswin_clk_register_fixed_factor(const struct eswin_fixed_factor_clock *clks,
+					   int nums,
+					   struct eswin_clock_data *data)
+{
+	struct clk *clk;
+	int i;
+
+	for (i = 0; i < nums; i++) {
+		char *name = kzalloc(strlen(clks[i].name)
+			+ 2 * sizeof(char) + sizeof(int), GFP_KERNEL );
+		char *parent_name = kzalloc(strlen(clks[i].parent_name)
+			+ 2 * sizeof(char) + sizeof(int), GFP_KERNEL );
+		if (data->numa_id < 0) {
+			sprintf(name, "%s", clks[i].name);
+			sprintf(parent_name, "%s", clks[i].parent_name);
+		} else {
+			sprintf(name, "d%d_%s", data->numa_id, clks[i].name);
+			sprintf(parent_name, "d%d_%s", data->numa_id, clks[i].parent_name);
+		}
+
+		clk = clk_register_fixed_factor(NULL, name,
+						parent_name,
+						clks[i].flags, clks[i].mult,
+						clks[i].div);
+		if (IS_ERR(clk)) {
+			pr_err("%s: failed to register clock %s\n", __func__, name);
+			kfree(name);
+			kfree(parent_name);
+			goto err;
+		}
+		data->clk_data.clks[clks[i].id] = clk;
+
+		kfree(name);
+		kfree(parent_name);
+	}
+
+	return 0;
+
+err:
+	while (i--)
+		clk_unregister_fixed_factor(data->clk_data.clks[clks[i].id]);
+
+	return PTR_ERR(clk);
+}
+EXPORT_SYMBOL_GPL(eswin_clk_register_fixed_factor);
+
+int eswin_clk_register_mux(const struct eswin_mux_clock *clks,
+				  int nums, struct eswin_clock_data *data)
+{
+	struct clk *clk;
+	void __iomem *base = data->base;
+	int i;
+	int j;
+
+	for (i = 0; i < nums; i++) {
+		char *name = kzalloc(strlen(clks[i].name)
+			+ 2 * sizeof(char) + sizeof(int), GFP_KERNEL );
+
+		char **parent_names = kzalloc(sizeof(char *) * clks[i].num_parents,
+			GFP_KERNEL );
+		if (data->numa_id < 0) {
+			sprintf(name, "%s", clks[i].name);
+		} else {
+			sprintf(name, "d%d_%s", data->numa_id, clks[i].name);
+		}
+		for (j = 0; j < clks[i].num_parents; j++) {
+			parent_names[j] = kzalloc(strlen(clks[i].parent_names[j])
+				+ 2 * sizeof(char) + sizeof(int), GFP_KERNEL );
+			if (data->numa_id < 0) {
+				sprintf(parent_names[j], "%s", clks[i].parent_names[j]);
+			} else {
+				sprintf(parent_names[j], "d%d_%s",
+					data->numa_id, clks[i].parent_names[j]);
+			}
+		}
+		clk = clk_register_mux_table(NULL, name,
+				(const char * const*)parent_names,
+				clks[i].num_parents, clks[i].flags,
+				base + clks[i].offset, clks[i].shift,
+				clks[i].mask, clks[i].mux_flags,
+				clks[i].table, &data->lock);
+		if (IS_ERR(clk)) {
+			pr_err("%s: failed to register clock %s\n", __func__, clks[i].name);
+			kfree(name);
+			for (j = 0; j < clks[i].num_parents; j++) {
+				kfree(parent_names[j]);
+			}
+			kfree(parent_names);
+			goto err;
+		}
+
+		if (clks[i].alias)
+			clk_register_clkdev(clk, clks[i].alias, NULL);
+
+		data->clk_data.clks[clks[i].id] = clk;
+
+		kfree(name);
+		for (j = 0; j < clks[i].num_parents; j++) {
+			kfree(parent_names[j]);
+		}
+		kfree(parent_names);
+	}
+	return 0;
+
+err:
+	while (i--)
+		clk_unregister_mux(data->clk_data.clks[clks[i].id]);
+
+	return PTR_ERR(clk);
+}
+EXPORT_SYMBOL_GPL(eswin_clk_register_mux);
+
+int eswin_clk_register_divider(const struct eswin_divider_clock *clks,
+				      int nums, struct eswin_clock_data *data)
+{
+	struct clk *clk;
+	void __iomem *base = data->base;
+	int i;
+	struct clk_hw *clk_hw;
+	struct clk_hw *parent_hw;
+	struct clk_parent_data	parent_data;
+
+	for (i = 0; i < nums; i++) {
+		char *name = kzalloc(strlen(clks[i].name)
+			+ 2 * sizeof(char) + sizeof(int), GFP_KERNEL );
+		char *parent_name = kzalloc(strlen(clks[i].parent_name)
+			+ 2 * sizeof(char) + sizeof(int), GFP_KERNEL );
+		if (data->numa_id < 0) {
+			sprintf(name, "%s", clks[i].name);
+			sprintf(parent_name, "%s", clks[i].parent_name);
+		} else {
+			sprintf(name, "d%d_%s", data->numa_id, clks[i].name);
+			sprintf(parent_name, "d%d_%s", data->numa_id, clks[i].parent_name);
+		}
+		parent_hw = eswin_clk_find_parent(data, parent_name);
+		parent_data.name = parent_name;
+		parent_data.hw = parent_hw;
+		parent_data.fw_name = NULL;
+		clk_hw = clk_hw_register_divider_table_parent_data(NULL, name,
+						&parent_data,
+						clks[i].flags,
+						base + clks[i].offset,
+						clks[i].shift, clks[i].width,
+						clks[i].div_flags,
+						clks[i].table,
+						&data->lock);
+		if (IS_ERR(clk_hw)) {
+			pr_err("%s: failed to register clock %s\n", __func__, clks[i].name);
+			kfree(name);
+			kfree(parent_name);
+			goto err;
+		}
+		clk = clk_hw->clk;
+		if (clks[i].alias)
+			clk_register_clkdev(clk, clks[i].alias, NULL);
+
+		data->clk_data.clks[clks[i].id] = clk;
+		kfree(name);
+		kfree(parent_name);
+	}
+	return 0;
+
+err:
+	while (i--)
+		clk_unregister_divider(data->clk_data.clks[clks[i].id]);
+
+	return PTR_ERR(clk);
+}
+EXPORT_SYMBOL_GPL(eswin_clk_register_divider);
+
+int eswin_clk_register_gate(const struct eswin_gate_clock *clks,
+				       int nums, struct eswin_clock_data *data)
+{
+	struct clk *clk;
+	void __iomem *base = data->base;
+	int i;
+	struct clk_hw *clk_hw;
+	struct clk_hw *parent_hw;
+	struct clk_parent_data	parent_data;
+
+	for (i = 0; i < nums; i++) {
+		char *name = kzalloc(strlen(clks[i].name)
+			+ 2 * sizeof(char) + sizeof(int), GFP_KERNEL);
+		char *parent_name = kzalloc(strlen(clks[i].parent_name)
+			+ 2 * sizeof(char) + sizeof(int), GFP_KERNEL);
+		if (data->numa_id < 0) {
+			sprintf(name, "%s", clks[i].name);
+			sprintf(parent_name, "%s", clks[i].parent_name);
+		} else {
+			sprintf(name, "d%d_%s", data->numa_id, clks[i].name);
+			sprintf(parent_name, "d%d_%s", data->numa_id, clks[i].parent_name);
+		}
+		parent_hw = eswin_clk_find_parent(data, parent_name);
+		parent_data.name = parent_name;
+		parent_data.hw = parent_hw;
+		parent_data.fw_name = NULL;
+		clk_hw = clk_hw_register_gate_parent_data(NULL, name,
+				&parent_data,
+				clks[i].flags,
+				base + clks[i].offset,
+				clks[i].bit_idx,
+				clks[i].gate_flags,
+				&data->lock);
+		if (IS_ERR(clk_hw)) {
+			pr_err("%s: failed to register clock %s\n",__func__, clks[i].name);
+			kfree(name);
+			kfree(parent_name);
+			goto err;
+		}
+		clk = clk_hw->clk;
+		if (clks[i].alias)
+			clk_register_clkdev(clk, clks[i].alias, NULL);
+
+		data->clk_data.clks[clks[i].id] = clk;
+		kfree(name);
+		kfree(parent_name);
+	}
+	return 0;
+
+err:
+	while (i--)
+		clk_unregister_gate(data->clk_data.clks[clks[i].id]);
+
+	return PTR_ERR(clk);
+}
+EXPORT_SYMBOL_GPL(eswin_clk_register_gate);
+
+static const struct clk_ops clk_dummpy_ops = {
+
+};
+
+static struct clk *eswin_register_clk(struct eswin_clock_data *data,
+				     struct device *dev, const char *name,
+				      const char *parent_name,
+				      unsigned long flags,
+				      spinlock_t *lock)
+{
+	struct eswin_clock *eclk;
+	struct clk *clk;
+	struct clk_init_data init;
+	struct clk_parent_data	parent_data;
+	struct clk_hw 		*parent_hw;
+
+	eclk = kzalloc(sizeof(*eclk), GFP_KERNEL );
+	if (!eclk)
+		return ERR_PTR(-ENOMEM);
+
+	init.ops = &clk_dummpy_ops;
+
+	init.name = name;
+	init.flags = flags;
+	init.parent_names = NULL;
+	init.num_parents = (parent_name ? 1 : 0);
+	init.parent_data = &parent_data;
+
+	parent_hw = eswin_clk_find_parent(data, (char *)parent_name);
+	parent_data.name = parent_name;
+	parent_data.hw = parent_hw;
+	parent_data.fw_name = NULL;
+
+	eclk->hw.init = &init;
+
+	clk = clk_register(dev, &eclk->hw);
+	if (IS_ERR(clk))
+		kfree(eclk);
+
+	return clk;
+}
+
+int eswin_clk_register_clk(const struct eswin_clock *clks,
+				       int nums, struct eswin_clock_data *data)
+{
+	struct clk *clk;
+	int 	i;
+
+	for (i = 0; i < nums; i++) {
+		char *name = kzalloc(strlen(clks[i].name)
+			+ 2 * sizeof(char) + sizeof(int), GFP_KERNEL );
+		char *parent_name = kzalloc(strlen(clks[i].parent_name)
+			+ 2 * sizeof(char) + sizeof(int), GFP_KERNEL );
+		if (data->numa_id < 0) {
+			sprintf(name, "%s", clks[i].name);
+			sprintf(parent_name, "%s", clks[i].parent_name);
+		} else {
+			sprintf(name, "d%d_%s", data->numa_id, clks[i].name);
+			sprintf(parent_name, "d%d_%s", data->numa_id, clks[i].parent_name);
+		}
+		clk = eswin_register_clk(data, NULL, name, parent_name,
+					clks[i].flags, &data->lock);
+		if (IS_ERR(clk)) {
+			pr_err("%s: failed to register clock %s\n", __func__, clks[i].name);
+			kfree(name);
+			kfree(parent_name);
+			goto err;
+		}
+
+		if (clks[i].alias)
+			clk_register_clkdev(clk, clks[i].alias, NULL);
+
+		data->clk_data.clks[clks[i].id] = clk;
+		kfree(name);
+		kfree(parent_name);
+	}
+	return 0;
+err:
+	while (i--)
+		clk_unregister_gate(data->clk_data.clks[clks[i].id]);
+
+	return PTR_ERR(clk);
+}
+EXPORT_SYMBOL_GPL(eswin_clk_register_clk);
diff --git a/drivers/clk/eswin/clk.h b/drivers/clk/eswin/clk.h
new file mode 100644
index 000000000000..19bf2a995471
--- /dev/null
+++ b/drivers/clk/eswin/clk.h
@@ -0,0 +1,199 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * ESWIN Clk Provider Driver
+ *
+ * Copyright 2024, Beijing ESWIN Computing Technology Co., Ltd.. All rights reserved.
+ * SPDX-License-Identifier: GPL-2.0
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, version 2.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <https://www.gnu.org/licenses/>.
+ *
+ * Authors: HuangYiFeng<huangyifeng@eswincomputing.com>
+ */
+
+#ifndef	__ESWIN_CLK_H
+#define	__ESWIN_CLK_H
+
+#include <linux/clk-provider.h>
+#include <linux/io.h>
+#include <linux/spinlock.h>
+#include <linux/platform_device.h>
+
+struct platform_device;
+
+struct eswin_clock_data {
+	struct clk_onecell_data	clk_data;
+	void __iomem		*base;
+	int 			numa_id;
+	spinlock_t 		lock;
+};
+
+struct eswin_clock {
+	unsigned int		id;
+	char			*name;
+	const char		*parent_name;
+	unsigned long		flags;
+	struct clk_hw		hw;
+	const char		*alias;
+};
+
+struct eswin_fixed_rate_clock {
+	unsigned int		id;
+	char			*name;
+	const char		*parent_name;
+	unsigned long		flags;
+	unsigned long		fixed_rate;
+};
+
+struct eswin_fixed_factor_clock {
+	unsigned int		id;
+	char				*name;
+	const char			*parent_name;
+	unsigned long		mult;
+	unsigned long		div;
+	unsigned long		flags;
+};
+
+struct eswin_mux_clock {
+	unsigned int		id;
+	const char			*name;
+	const char	*const 	*parent_names;
+	u8					num_parents;
+	unsigned long		flags;
+	unsigned long		offset;
+	u8					shift;
+	u32 				mask;
+	u8					mux_flags;
+	u32					*table;
+	const char			*alias;
+};
+
+
+struct eswin_divider_clock {
+	unsigned int		id;
+	const char		*name;
+	const char		*parent_name;
+	unsigned long		flags;
+	unsigned long		offset;
+	u8			shift;
+	u8			width;
+	u8			div_flags;
+	struct clk_div_table	*table;
+	const char		*alias;
+};
+
+struct eswin_gate_clock {
+	unsigned int		id;
+	const char		*name;
+	const char		*parent_name;
+	unsigned long		flags;
+	unsigned long		offset;
+	u8			bit_idx;
+	u8			gate_flags;
+	const char		*alias;
+};
+
+struct eswin_pll_clock {
+	u32	id;
+	const char	*name;
+	const char	*parent_name;
+	const u32	ctrl_reg0;
+	const u8	pllen_shift;
+	const u8	pllen_width;
+	const u8	refdiv_shift;
+	const u8	refdiv_width;
+	const u8	fbdiv_shift;
+	const u8	fbdiv_width;
+
+	const u32	ctrl_reg1;
+	const u8	frac_shift;
+	const u8	frac_width;
+
+	const u32	ctrl_reg2;
+	const u8	postdiv1_shift;
+	const u8	postdiv1_width;
+	const u8	postdiv2_shift;
+	const u8	postdiv2_width;
+
+	const u32	status_reg;
+	const u8	lock_shift;
+	const u8	lock_width;
+};
+
+struct eswin_clk_pll {
+	struct clk_hw	hw;
+	u32	id;
+	int 	numa_id;
+	void __iomem	*ctrl_reg0;
+	u8	pllen_shift;
+	u8	pllen_width;
+	u8	refdiv_shift;
+	u8	refdiv_width;
+	u8	fbdiv_shift;
+	u8	fbdiv_width;
+
+	void __iomem	*ctrl_reg1;
+	u8	frac_shift;
+	u8	frac_width;
+
+	void __iomem	*ctrl_reg2;
+	u8	postdiv1_shift;
+	u8	postdiv1_width;
+	u8	postdiv2_shift;
+	u8	postdiv2_width;
+
+	void __iomem	*status_reg;
+	u8	lock_shift;
+	u8	lock_width;
+};
+
+struct eswin_clock_data *eswin_clk_init(struct platform_device *, int);
+int eswin_clk_register_fixed_rate(const struct eswin_fixed_rate_clock *,
+				int, struct eswin_clock_data *);
+
+void eswin_clk_register_pll(struct eswin_pll_clock *clks,
+		int nums, struct eswin_clock_data *data, struct device *dev);
+
+int eswin_clk_register_fixed_factor(const struct eswin_fixed_factor_clock *,
+				int, struct eswin_clock_data *);
+int eswin_clk_register_mux(const struct eswin_mux_clock *, int,
+				struct eswin_clock_data *);
+
+int eswin_clk_register_divider(const struct eswin_divider_clock *,
+				int, struct eswin_clock_data *);
+int eswin_clk_register_gate(const struct eswin_gate_clock *,
+				int, struct eswin_clock_data *);
+
+int eswin_clk_register_clk(const struct eswin_clock *,
+				       int , struct eswin_clock_data *);
+
+#define eswin_clk_unregister(type) \
+static inline \
+void eswin_clk_unregister_##type(const struct eswin_##type##_clock *clks, \
+				int nums, struct eswin_clock_data *data) \
+{ \
+	struct clk **clocks = data->clk_data.clks; \
+	int i; \
+	for (i = 0; i < nums; i++) { \
+		int id = clks[i].id; \
+		if (clocks[id])  \
+			clk_unregister_##type(clocks[id]); \
+	} \
+}
+
+eswin_clk_unregister(fixed_rate)
+eswin_clk_unregister(fixed_factor)
+eswin_clk_unregister(mux)
+eswin_clk_unregister(divider)
+eswin_clk_unregister(gate)
+
+#endif	/* __ESWIN_CLK_H */
diff --git a/drivers/gpu/drm/drm_gem_vram_helper.c b/drivers/gpu/drm/drm_gem_vram_helper.c
index 22b1fe9c03b8..f12319e5d11f 100644
--- a/drivers/gpu/drm/drm_gem_vram_helper.c
+++ b/drivers/gpu/drm/drm_gem_vram_helper.c
@@ -798,7 +798,11 @@ static struct ttm_tt *bo_driver_ttm_tt_create(struct ttm_buffer_object *bo,
 	if (!tt)
 		return NULL;
 
+#ifdef CONFIG_SOC_SIFIVE_EIC7700
+	ret = ttm_tt_init(tt, bo, page_flags, ttm_write_combined, 0);
+#else
 	ret = ttm_tt_init(tt, bo, page_flags, ttm_cached, 0);
+#endif
 	if (ret < 0)
 		goto err_ttm_tt_init;
 
diff --git a/drivers/gpu/drm/ttm/ttm_bo_util.c b/drivers/gpu/drm/ttm/ttm_bo_util.c
index bd90404ea609..f572e269aaa2 100644
--- a/drivers/gpu/drm/ttm/ttm_bo_util.c
+++ b/drivers/gpu/drm/ttm/ttm_bo_util.c
@@ -355,7 +355,7 @@ static int ttm_bo_kmap_ttm(struct ttm_buffer_object *bo,
 	if (ret)
 		return ret;
 
-	if (num_pages == 1 && ttm->caching == ttm_cached &&
+	if (num_pages == 1 && ttm->caching == ttm_cached && !IS_ENABLED(CONFIG_SOC_SIFIVE_EIC7700) &&
 	    !(man->use_tt && (ttm->page_flags & TTM_TT_FLAG_DECRYPTED))) {
 		/*
 		 * We're mapping a single page, and the desired
diff --git a/drivers/gpu/drm/ttm/ttm_module.c b/drivers/gpu/drm/ttm/ttm_module.c
index b3fffe7b5062..aa137ead5cc5 100644
--- a/drivers/gpu/drm/ttm/ttm_module.c
+++ b/drivers/gpu/drm/ttm/ttm_module.c
@@ -74,7 +74,8 @@ pgprot_t ttm_prot_from_caching(enum ttm_caching caching, pgprot_t tmp)
 #endif /* CONFIG_UML */
 #endif /* __i386__ || __x86_64__ */
 #if defined(__ia64__) || defined(__arm__) || defined(__aarch64__) || \
-	defined(__powerpc__) || defined(__mips__) || defined(__loongarch__)
+	defined(__powerpc__) || defined(__mips__) || defined(__loongarch__) || \
+	defined(__riscv)
 	if (caching == ttm_write_combined)
 		tmp = pgprot_writecombine(tmp);
 	else
diff --git a/drivers/gpu/drm/ttm/ttm_resource.c b/drivers/gpu/drm/ttm/ttm_resource.c
index 006202fcd3c2..fc6ea7ac21f0 100644
--- a/drivers/gpu/drm/ttm/ttm_resource.c
+++ b/drivers/gpu/drm/ttm/ttm_resource.c
@@ -335,7 +335,11 @@ void ttm_resource_init(struct ttm_buffer_object *bo,
 	res->bus.addr = NULL;
 	res->bus.offset = 0;
 	res->bus.is_iomem = false;
+#ifdef CONFIG_SOC_SIFIVE_EIC7700
+	res->bus.caching = ttm_write_combined;
+#else
 	res->bus.caching = ttm_cached;
+#endif
 	res->bo = bo;
 
 	man = ttm_manager_type(bo->bdev, place->mem_type);
@@ -842,10 +846,13 @@ ttm_kmap_iter_linear_io_init(struct ttm_kmap_iter_linear_io *iter_io,
 	} else {
 		iter_io->needs_unmap = true;
 		memset(&iter_io->dmap, 0, sizeof(iter_io->dmap));
+
+#ifndef CONFIG_SOC_SIFIVE_EIC7700
 		if (mem->bus.caching == ttm_write_combined)
 			iosys_map_set_vaddr_iomem(&iter_io->dmap,
 						  ioremap_wc(mem->bus.offset,
 							     mem->size));
+
 		else if (mem->bus.caching == ttm_cached)
 			iosys_map_set_vaddr(&iter_io->dmap,
 					    memremap(mem->bus.offset, mem->size,
@@ -853,6 +860,12 @@ ttm_kmap_iter_linear_io_init(struct ttm_kmap_iter_linear_io *iter_io,
 						     MEMREMAP_WT |
 						     MEMREMAP_WC));
 
+#else
+		if (mem->bus.caching == ttm_write_combined || mem->bus.caching == ttm_cached)
+			iosys_map_set_vaddr_iomem(&iter_io->dmap,
+						  ioremap_wc(mem->bus.offset,
+							     mem->size));
+#endif
 		/* If uncached requested or if mapping cached or wc failed */
 		if (iosys_map_is_null(&iter_io->dmap))
 			iosys_map_set_vaddr_iomem(&iter_io->dmap,
diff --git a/drivers/gpu/drm/ttm/ttm_tt.c b/drivers/gpu/drm/ttm/ttm_tt.c
index 698cd4bf5e46..d0ff3a2b259d 100644
--- a/drivers/gpu/drm/ttm/ttm_tt.c
+++ b/drivers/gpu/drm/ttm/ttm_tt.c
@@ -158,7 +158,11 @@ static void ttm_tt_init_fields(struct ttm_tt *ttm,
 	ttm->dma_address = NULL;
 	ttm->swap_storage = NULL;
 	ttm->sg = bo->sg;
+#ifdef CONFIG_SOC_SIFIVE_EIC7700
+	ttm->caching = ttm_write_combined;
+#else
 	ttm->caching = caching;
+#endif
 	ttm->restore = NULL;
 	ttm->backup = NULL;
 }
diff --git a/drivers/hwmon/Kconfig b/drivers/hwmon/Kconfig
index 079620dd4286..4e3c7531be9b 100644
--- a/drivers/hwmon/Kconfig
+++ b/drivers/hwmon/Kconfig
@@ -310,6 +310,15 @@ config SENSORS_AXI_FAN_CONTROL
 	  This driver can also be built as a module. If so, the module
 	  will be called axi-fan-control
 
+config SENSORS_ESWIN_FAN_CONTROL
+	tristate "ESWIN FAN Control Core driver"
+	help
+	  If you say yes here you get support for the Analog Devices
+	  ESWIN FAN monitoring core.
+
+	  This driver can also be built as a module. If so, the module
+	  will be called eswin-fan-control
+
 config SENSORS_K8TEMP
 	tristate "AMD Athlon64/FX or Opteron temperature sensor"
 	depends on X86 && PCI
@@ -620,6 +629,12 @@ config SENSORS_DA9055
 	  This driver can also be built as a module. If so, the module
 	  will be called da9055-hwmon.
 
+config SENSORS_ESWIN_PVT
+	tristate "Eswin Process, Voltage, Temperature sensor driver"
+	depends on HWMON
+	help
+	  If you say yes here you get support for Eswin PVT sensor.
+
 config SENSORS_I5K_AMB
 	tristate "FB-DIMM AMB temperature sensor on Intel 5000 series chipsets"
 	depends on PCI
@@ -1630,6 +1645,13 @@ config SENSORS_LM95245
 	  This driver can also be built as a module. If so, the module
 	  will be called lm95245.
 
+config SENSORS_PAC1934
+	tristate "microchip PAC193X  Hardware Monitoring"
+	depends on I2C
+	help
+	  If you say yes here you get support for microchip PAC193X
+	  Single/Multi-Channel DC Power/Energy  Monitor with Accumulator.
+
 config SENSORS_PC87360
 	tristate "National Semiconductor PC87360 family"
 	depends on HAS_IOPORT
diff --git a/drivers/hwmon/Makefile b/drivers/hwmon/Makefile
index 48e5866c0c9a..d7c90146e3c6 100644
--- a/drivers/hwmon/Makefile
+++ b/drivers/hwmon/Makefile
@@ -76,6 +76,8 @@ obj-$(CONFIG_SENSORS_EMC1403)	+= emc1403.o
 obj-$(CONFIG_SENSORS_EMC2103)	+= emc2103.o
 obj-$(CONFIG_SENSORS_EMC2305)	+= emc2305.o
 obj-$(CONFIG_SENSORS_EMC6W201)	+= emc6w201.o
+obj-$(CONFIG_SENSORS_ESWIN_FAN_CONTROL)	+= eswin-fan-control.o
+obj-$(CONFIG_SENSORS_ESWIN_PVT)	+= eswin_pvt.o
 obj-$(CONFIG_SENSORS_F71805F)	+= f71805f.o
 obj-$(CONFIG_SENSORS_F71882FG)	+= f71882fg.o
 obj-$(CONFIG_SENSORS_F75375S)	+= f75375s.o
@@ -186,6 +188,8 @@ obj-$(CONFIG_SENSORS_NTC_THERMISTOR)	+= ntc_thermistor.o
 obj-$(CONFIG_SENSORS_NZXT_KRAKEN2) += nzxt-kraken2.o
 obj-$(CONFIG_SENSORS_NZXT_KRAKEN3) += nzxt-kraken3.o
 obj-$(CONFIG_SENSORS_NZXT_SMART2) += nzxt-smart2.o
+obj-$(CONFIG_SENSORS_OXP) += oxp-sensors.o
+obj-$(CONFIG_SENSORS_PAC1934)	+= pac193x.o
 obj-$(CONFIG_SENSORS_PC87360)	+= pc87360.o
 obj-$(CONFIG_SENSORS_PC87427)	+= pc87427.o
 obj-$(CONFIG_SENSORS_PCF8591)	+= pcf8591.o
diff --git a/drivers/hwmon/eswin-fan-control.c b/drivers/hwmon/eswin-fan-control.c
new file mode 100644
index 000000000000..aa230a88166e
--- /dev/null
+++ b/drivers/hwmon/eswin-fan-control.c
@@ -0,0 +1,514 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Fan Control CORE driver
+ *
+ * Copyright 2022 ESWIN Inc.
+ */
+#include <linux/bits.h>
+#include <linux/clk.h>
+#include <linux/reset.h>
+#include <linux/hwmon.h>
+#include <linux/hwmon-sysfs.h>
+#include <linux/interrupt.h>
+#include <linux/io.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+#include <linux/pwm.h>
+#include <linux/wait.h>
+
+#define FAN_PWM_DUTY           0x0
+#define FAN_PWM_PERIOD         0x1
+#define FAN_PWM_FREE	       0x2
+
+/* register map */
+#define REG_FAN_INT            0x0
+#define REG_FAN_RPM            0x4
+
+/* wait for 50 times pwm period to trigger read interrupt */
+#define TIMEOUT(period)        nsecs_to_jiffies(50*(period))
+
+struct eswin_fan_control_data {
+	struct reset_control *fan_rst;
+	struct clk *clk;
+	void __iomem *base;
+	struct device *hdev;
+	unsigned long clk_rate;
+	int pwm_id;
+	struct pwm_device *pwm;
+	wait_queue_head_t wq;
+	bool wait_flag;
+	int irq;
+	/* pwm minimum period */
+	u32 min_period;
+	/* pulses per revolution */
+	u32 ppr;
+	/* revolutions per minute */
+	u32 rpm;
+};
+
+static inline void fan_iowrite(const u32 val, const u32 reg,
+			       const struct eswin_fan_control_data *ctl)
+{
+	iowrite32(val, ctl->base + reg);
+}
+
+static inline u32 fan_ioread(const u32 reg,
+			     const struct eswin_fan_control_data *ctl)
+{
+	return ioread32(ctl->base + reg);
+}
+
+static ssize_t eswin_fan_pwm_ctl_show(struct device *dev, struct device_attribute *da, char *buf)
+{
+	struct eswin_fan_control_data *ctl = dev_get_drvdata(dev);
+	struct sensor_device_attribute *attr = to_sensor_dev_attr(da);
+	long temp = 0;
+
+	if (FAN_PWM_DUTY == attr->index) {
+		temp = pwm_get_duty_cycle(ctl->pwm);
+	}
+	else if (FAN_PWM_PERIOD == attr->index) {
+		temp = pwm_get_period(ctl->pwm);
+	}
+	else {
+		dev_err(dev, "get error attr index 0x%x\n", attr->index);
+	}
+
+	return sprintf(buf, "%lu\n", temp);
+}
+
+static ssize_t eswin_fan_pwm_ctl_store(struct device *dev, struct device_attribute *da,
+				     const char *buf, size_t count)
+{
+	struct eswin_fan_control_data *ctl = dev_get_drvdata(dev);
+	struct sensor_device_attribute *attr = to_sensor_dev_attr(da);
+	struct pwm_state state;
+	int ret;
+
+	pwm_get_state(ctl->pwm, &state);
+
+	if (FAN_PWM_DUTY == attr->index) {
+		long val = 0;
+		ret = kstrtoul(buf, 10, &val);
+		if (ret)
+			return ret;
+
+		state.duty_cycle = val;
+	}
+	else if (FAN_PWM_PERIOD == attr->index) {
+		long val = 0;
+		ret = kstrtoul(buf, 10, &val);
+		if (ret)
+			return ret;
+		if (val >= ctl->min_period)
+			state.period = val;
+		else
+			dev_err(dev, "invalid pwm period!\n");
+	}
+	else {
+		dev_err(dev, "get error attr index 0x%x\n", attr->index);
+	}
+
+	pwm_apply_might_sleep(ctl->pwm, &state);
+
+	return count;
+}
+
+static ssize_t eswin_fan_pwm_free_store(struct device *dev, struct device_attribute *da,
+				     const char *buf, size_t count)
+{
+	struct eswin_fan_control_data *ctl = dev_get_drvdata(dev);
+	long val;
+	int ret;
+	ret = kstrtoul(buf, 10, &val);
+	if (ret)
+		return ret;
+
+	if (val) {
+		pwm_put(ctl->pwm);
+	}
+
+	return count;
+}
+
+static long eswin_fan_control_get_pwm_duty(const struct eswin_fan_control_data *ctl)
+{
+	struct pwm_state state;
+	int duty;
+
+	pwm_get_state(ctl->pwm, &state);
+	duty = pwm_get_relative_duty_cycle(&state, 256);
+
+	return duty;
+}
+
+static long eswin_fan_control_get_fan_rpm(struct eswin_fan_control_data *ctl)
+{
+	unsigned int val;
+	long period, timeout;
+	int ret;
+
+	ctl->wait_flag = false;
+	period = pwm_get_period(ctl->pwm);
+	timeout = msecs_to_jiffies(1500);
+
+	val = fan_ioread(REG_FAN_INT, ctl);
+	val = val | 0x1;
+	fan_iowrite(val, REG_FAN_INT, ctl);
+
+	/* wait read interrupt */
+	ret = wait_event_interruptible_timeout(ctl->wq,
+                                        ctl->wait_flag,
+                                        timeout);
+
+	if (!ret){
+		/* timeout, set rpm to 0 */
+		ctl->rpm = 0;
+	}
+
+	if(ctl->rpm)
+		ctl->rpm = DIV_ROUND_CLOSEST(60 * ctl->clk_rate, ctl->ppr * ctl->rpm);
+
+	return ret;
+}
+
+static int eswin_fan_control_read_fan(struct device *dev, u32 attr, long *val)
+{
+	struct eswin_fan_control_data *ctl = dev_get_drvdata(dev);
+
+	switch (attr) {
+	case hwmon_fan_input:
+		if(!eswin_fan_control_get_fan_rpm(ctl)){
+			dev_err(dev, "wait read interrupt timeout!\n");
+		}
+		*val = ctl->rpm;
+		return 0;
+	default:
+		return -ENOTSUPP;
+	}
+}
+
+static int eswin_fan_control_read_pwm(struct device *dev, u32 attr, long *val)
+{
+	struct eswin_fan_control_data *ctl = dev_get_drvdata(dev);
+
+	switch (attr) {
+	case hwmon_pwm_input:
+		*val = eswin_fan_control_get_pwm_duty(ctl);
+		return 0;
+	default:
+		return -ENOTSUPP;
+	}
+}
+
+static int eswin_fan_control_set_pwm_duty(const long val, struct eswin_fan_control_data *ctl)
+{
+	struct pwm_state state;
+
+	pwm_get_state(ctl->pwm, &state);
+	pwm_set_relative_duty_cycle(&state, val, 256);
+	pwm_apply_might_sleep(ctl->pwm, &state);
+
+	return 0;
+}
+
+static int eswin_fan_control_write_pwm(struct device *dev, u32 attr, long val)
+{
+	struct eswin_fan_control_data *ctl = dev_get_drvdata(dev);
+
+	switch (attr) {
+		case hwmon_pwm_input:
+	if((val < 25) || (val > 255))
+	{
+		dev_err(dev,"pwm range is form 25 to 255\n");
+		return -EINVAL;
+	}
+	else
+		return eswin_fan_control_set_pwm_duty(val, ctl);
+	default:
+		return -ENOTSUPP;
+	}
+
+	return 0;
+}
+
+static int eswin_fan_control_read_labels(struct device *dev,
+					enum hwmon_sensor_types type,
+					u32 attr, int channel, const char **str)
+{
+	switch (type) {
+	case hwmon_fan:
+		*str = "FAN";
+		return 0;
+	default:
+		return -ENOTSUPP;
+	}
+}
+
+static int eswin_fan_control_read(struct device *dev,
+				enum hwmon_sensor_types type,
+				u32 attr, int channel, long *val)
+{
+	switch (type) {
+	case hwmon_fan:
+		return eswin_fan_control_read_fan(dev, attr, val);
+	case hwmon_pwm:
+		return eswin_fan_control_read_pwm(dev, attr, val);
+	default:
+		return -ENOTSUPP;
+	}
+}
+
+static int eswin_fan_control_write(struct device *dev,
+				 enum hwmon_sensor_types type,
+				 u32 attr, int channel, long val)
+{
+	switch (type) {
+	case hwmon_pwm:
+		return eswin_fan_control_write_pwm(dev, attr, val);
+	default:
+		return -ENOTSUPP;
+	}
+}
+
+static umode_t eswin_fan_control_fan_is_visible(const u32 attr)
+{
+	switch (attr) {
+	case hwmon_fan_input:
+	case hwmon_fan_label:
+		return 0444;
+	default:
+		return 0;
+	}
+}
+
+static umode_t eswin_fan_control_pwm_is_visible(const u32 attr)
+{
+	switch (attr) {
+	case hwmon_pwm_input:
+		return 0644;
+	default:
+		return 0;
+	}
+}
+
+static umode_t eswin_fan_control_is_visible(const void *data,
+					enum hwmon_sensor_types type,
+					u32 attr, int channel)
+{
+	switch (type) {
+	case hwmon_fan:
+		return eswin_fan_control_fan_is_visible(attr);
+	case hwmon_pwm:
+		return eswin_fan_control_pwm_is_visible(attr);
+	default:
+		return 0;
+	}
+}
+
+static irqreturn_t eswin_fan_control_irq_handler(int irq, void *data)
+{
+	struct eswin_fan_control_data *ctl = (struct eswin_fan_control_data *)data;
+	u32 status = 0;
+
+	status = fan_ioread(REG_FAN_INT, ctl);
+	if (0x3 == (status & 0x3)){
+		ctl->rpm = fan_ioread(REG_FAN_RPM, ctl);
+
+		/* clear interrupt */
+		fan_iowrite(0x5, REG_FAN_INT, ctl);
+
+		/* wake up fan_rpm read */
+		ctl->wait_flag = true;
+		wake_up_interruptible(&ctl->wq);
+	}
+
+	return IRQ_HANDLED;
+}
+
+static int eswin_fan_control_init(struct eswin_fan_control_data *ctl,
+				const struct device_node *np)
+{
+	int ret;
+	/* get fan pulses per revolution */
+	ret = of_property_read_u32(np, "pulses-per-revolution", &ctl->ppr);
+	if (ret)
+		return ret;
+
+	/* 1, 2 and 4 are the typical and accepted values */
+	if (ctl->ppr != 1 && ctl->ppr != 2 && ctl->ppr != 4)
+		return -EINVAL;
+
+	/* get pwm minimum period */
+	ret = of_property_read_u32(np, "pwm-minimum-period", &ctl->min_period);
+	if (ret)
+		return ret;
+
+	return ret;
+}
+
+static void eswin_fan_control_remove(void *data)
+{
+	int ret;
+	struct eswin_fan_control_data *ctl = data;
+	pwm_put(ctl->pwm);
+	ret = reset_control_assert(ctl->fan_rst);
+	WARN_ON(0 != ret);
+	clk_disable_unprepare(ctl->clk);
+}
+
+static const struct hwmon_channel_info *eswin_fan_control_info[] = {
+	HWMON_CHANNEL_INFO(pwm, HWMON_PWM_INPUT),
+	HWMON_CHANNEL_INFO(fan, HWMON_F_INPUT | HWMON_F_LABEL),
+	NULL
+};
+
+static const struct hwmon_ops eswin_fan_control_hwmon_ops = {
+	.is_visible = eswin_fan_control_is_visible,
+	.read = eswin_fan_control_read,
+	.write = eswin_fan_control_write,
+	.read_string = eswin_fan_control_read_labels,
+};
+
+static const struct hwmon_chip_info eswin_chip_info = {
+	.ops = &eswin_fan_control_hwmon_ops,
+	.info = eswin_fan_control_info,
+};
+
+static SENSOR_DEVICE_ATTR_RW(fan_pwm_duty,   eswin_fan_pwm_ctl,    FAN_PWM_DUTY);
+static SENSOR_DEVICE_ATTR_RW(fan_pwm_period, eswin_fan_pwm_ctl,    FAN_PWM_PERIOD);
+static SENSOR_DEVICE_ATTR_WO(fan_pwm_free,   eswin_fan_pwm_free,   FAN_PWM_FREE);
+
+static struct attribute *eswin_fan_control_attrs[] = {
+	&sensor_dev_attr_fan_pwm_duty.dev_attr.attr,
+	&sensor_dev_attr_fan_pwm_period.dev_attr.attr,
+	&sensor_dev_attr_fan_pwm_free.dev_attr.attr,
+	NULL,
+};
+ATTRIBUTE_GROUPS(eswin_fan_control);
+
+static const struct of_device_id eswin_fan_control_of_match[] = {
+	{ .compatible = "eswin-fan-control"},
+	{}
+};
+MODULE_DEVICE_TABLE(of, eswin_fan_control_of_match);
+
+static int eswin_fan_control_probe(struct platform_device *pdev)
+{
+	struct eswin_fan_control_data *ctl;
+	const struct of_device_id *id;
+	const char *name = "eswin_fan_control";
+	struct pwm_state state;
+	struct pwm_args pwm_args;
+	int ret;
+
+	id = of_match_node(eswin_fan_control_of_match, pdev->dev.of_node);
+	if (!id)
+		return -EINVAL;
+
+	ctl = devm_kzalloc(&pdev->dev, sizeof(*ctl), GFP_KERNEL);
+	if (!ctl)
+		return -ENOMEM;
+
+	ctl->base = devm_platform_ioremap_resource(pdev, 0);
+
+	if (IS_ERR(ctl->base))
+		return PTR_ERR(ctl->base);
+
+	ctl->clk = devm_clk_get(&pdev->dev, "pclk");
+	if (IS_ERR(ctl->clk)) {
+		dev_err(&pdev->dev, "Couldn't get the clock for fan-controller\n");
+		return -ENODEV;
+	}
+
+	ret = clk_prepare_enable(ctl->clk);
+	if (ret) {
+		dev_err(&pdev->dev, "Failed to enable clock for fan-controller\n");
+		return ret;
+	}
+
+	ctl->clk_rate = clk_get_rate(ctl->clk);
+	if (!ctl->clk_rate)
+		return -EINVAL;
+
+	ctl->fan_rst = devm_reset_control_get_optional(&pdev->dev, "fan_rst");
+	if (IS_ERR_OR_NULL(ctl->fan_rst)) {
+		dev_err(&pdev->dev, "Failed to get fan_rst reset handle\n");
+		return -EFAULT;
+	}
+	ret = reset_control_reset(ctl->fan_rst);
+	WARN_ON(0 != ret);
+
+	init_waitqueue_head(&ctl->wq);
+
+	ctl->irq = platform_get_irq(pdev, 0);
+	if (ctl->irq < 0)
+		return ctl->irq;
+
+	ret = devm_request_threaded_irq(&pdev->dev, ctl->irq,
+					eswin_fan_control_irq_handler, NULL,
+					IRQF_ONESHOT | IRQF_TRIGGER_HIGH,
+					pdev->driver_override, ctl);
+	if (ret) {
+		dev_err(&pdev->dev, "Failed to request an irq, %d", ret);
+		return ret;
+	}
+
+	ret = eswin_fan_control_init(ctl, pdev->dev.of_node);
+	if (ret) {
+		dev_err(&pdev->dev, "Failed to initialize device\n");
+		return ret;
+	}
+
+	ctl->pwm = pwm_get(&pdev->dev, NULL);
+	if (IS_ERR(ctl->pwm)) {
+		ret = PTR_ERR(ctl->pwm);
+		dev_err(&pdev->dev, "Failed to request pwm device: %d\n", ret);
+		return ret;
+	}
+
+	pwm_get_state(ctl->pwm, &state);
+
+	/* Then fill it with the reference config */
+	pwm_get_args(ctl->pwm, &pwm_args);
+
+	state.period = pwm_args.period;
+	state.duty_cycle = state.period * 255 / 256; /* default set max speed */
+
+	dev_info(&pdev->dev, "state.period: %lld state.duty_cycle: %lld\n",
+			state.period,state.duty_cycle);
+
+	ret = pwm_apply_might_sleep(ctl->pwm, &state);
+	if (ret) {
+		dev_err(&pdev->dev, "failed to apply initial PWM state: %d\n",
+			ret);
+	}
+	pwm_enable(ctl->pwm);
+
+	ret = devm_add_action_or_reset(&pdev->dev, eswin_fan_control_remove, ctl);
+	if (ret)
+		return ret;
+
+	ctl->hdev = devm_hwmon_device_register_with_info(&pdev->dev,
+							 name,
+							 ctl,
+							 &eswin_chip_info,
+							 eswin_fan_control_groups);
+	dev_info(&pdev->dev, "eswin fan control init done\n");
+	return PTR_ERR_OR_ZERO(ctl->hdev);
+}
+
+static struct platform_driver eswin_fan_control_driver = {
+	.driver = {
+		.name = "eswin_fan_control_driver",
+		.of_match_table = eswin_fan_control_of_match,
+	},
+	.probe = eswin_fan_control_probe,
+};
+module_platform_driver(eswin_fan_control_driver);
+
+MODULE_AUTHOR("Han Min <hanmin@eswincomputing.com>");
+MODULE_DESCRIPTION("ESWIN Fan Control CORE driver");
+MODULE_LICENSE("GPL");
diff --git a/drivers/hwmon/eswin_pvt.c b/drivers/hwmon/eswin_pvt.c
new file mode 100644
index 000000000000..6436330fde1c
--- /dev/null
+++ b/drivers/hwmon/eswin_pvt.c
@@ -0,0 +1,874 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * ESWIN PVT Device Driver
+ *
+ * Copyright 2024, Beijing ESWIN Computing Technology Co., Ltd.. All rights reserved.
+ * SPDX-License-Identifier: GPL-2.0
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, version 2.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <https://www.gnu.org/licenses/>.
+ *
+ * Authors: Bingzheng Yu <yubingzheng@eswincomputing.com>
+ */
+
+#include <linux/bitfield.h>
+#include <linux/bitops.h>
+#include <linux/clk.h>
+#include <linux/reset.h>
+#include <linux/completion.h>
+#include <linux/delay.h>
+#include <linux/device.h>
+#include <linux/hwmon-sysfs.h>
+#include <linux/hwmon.h>
+#include <linux/interrupt.h>
+#include <linux/io.h>
+#include <linux/kernel.h>
+#include <linux/ktime.h>
+#include <linux/limits.h>
+#include <linux/module.h>
+#include <linux/mutex.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+#include <linux/seqlock.h>
+#include <linux/sysfs.h>
+#include <linux/types.h>
+#include "eswin_pvt.h"
+
+/*
+ * For the sake of the code simplification we created the sensors info table
+ * with the sensor names, activation modes, threshold registers base address
+ * and the thresholds bit fields.
+ */
+static const struct pvt_sensor_info pvt_info[] = {
+	PVT_SENSOR_INFO(0, "CPU Core Temperature", hwmon_temp, TEMP, TTHRES),
+	PVT_SENSOR_INFO(0, "CPU Core Voltage", hwmon_in, VOLT, VTHRES),
+	PVT_SENSOR_INFO(1, "CPU Core Low-Vt", hwmon_in, LVT, LTHRES),
+	PVT_SENSOR_INFO(2, "CPU Core UltraLow-Vt", hwmon_in, ULVT, ULTHRES),
+	PVT_SENSOR_INFO(3, "CPU Core Standard-Vt", hwmon_in, SVT, STHRES),
+};
+
+/*
+ * The original translation formulae of the temperature (in degrees of Celsius)
+ * to PVT data and vice-versa are following:
+ * N = 6.0818e-8*(T^4) +1.2873e-5*(T^3) + 7.2244e-3*(T^2) + 3.6484*(T^1) +
+ *     1.6198e2,
+ * T = -1.8439e-11*(N^4) + 8.0705e-8*(N^3) + -1.8501e-4*(N^2) +
+ *     3.2843e-1*(N^1) - 4.8690e1,
+ * where T = [-40, 125]C and N = [27, 771].
+ * They must be accordingly altered to be suitable for the integer arithmetics.
+ * The technique is called 'factor redistribution', which just makes sure the
+ * multiplications and divisions are made so to have a result of the operations
+ * within the integer numbers limit. In addition we need to translate the
+ * formulae to accept millidegrees of Celsius. Here what they look like after
+ * the alterations:
+ * N = (60818e-20*(T^4) + 12873e-14*(T^3) + 72244e-9*(T^2) + 36484e-3*T +
+ *     16198e2) / 1e4,
+ * T = -18439e-12*(N^4) + 80705e-9*(N^3) - 185010e-6*(N^2) + 328430e-3*N -
+ *     48690,
+ * where T = [-40000, 125000] mC and N = [27, 771].
+ */
+static const struct pvt_poly __maybe_unused poly_temp_to_N = {
+	.total_divider = 10000,
+	.terms = {
+		{4, 60818, 10000, 10000},
+		{3, 12873, 10000, 100},
+		{2, 72244, 10000, 10},
+		{1, 36484, 1000, 1},
+		{0, 1619800, 1, 1}
+	}
+};
+
+static const struct pvt_poly poly_N_to_temp = {
+	.total_divider = 1,
+	.terms = {
+		{4, -18439, 1000, 1},
+		{3, 80705, 1000, 1},
+		{2, -185010, 1000, 1},
+		{1, 328430, 1000, 1},
+		{0, -48690, 1, 1}
+	}
+};
+
+/*
+ * Similar alterations are performed for the voltage conversion equations.
+ * The original formulae are:
+ * N = 1.3905e3*V - 5.7685e2,
+ * V = (N + 5.7685e2) / 1.3905e3,
+ * where V = [0.72, 0.88] V and N = [424, 646].
+ * After the optimization they looks as follows:
+ * N = (13905e-3*V - 5768.5) / 10,
+ * V = (N * 10^5 / 13905 + 57685 * 10^3 / 13905) / 10.
+ * where V = [720, 880] mV and N = [424, 646].
+ */
+static const struct pvt_poly __maybe_unused poly_volt_to_N = {
+	.total_divider = 10,
+	.terms = {
+		{1, 13905, 1000, 1},
+		{0, -57685, 1, 10}
+	}
+};
+
+static const struct pvt_poly poly_N_to_volt = {
+	.total_divider = 10,
+	.terms = {
+		{1, 100000, 13905, 1},
+		{0, 57685000, 1, 13905}
+	}
+};
+
+/*
+ * Here is the polynomial calculation function, which performs the
+ * redistributed terms calculations. It's pretty straightforward. We walk
+ * over each degree term up to the free one, and perform the redistributed
+ * multiplication of the term coefficient, its divider (as for the rationale
+ * fraction representation), data power and the rational fraction divider
+ * leftover. Then all of this is collected in a total sum variable, which
+ * value is normalized by the total divider before being returned.
+ */
+static long eswin_pvt_calc_poly(const struct pvt_poly *poly, long data)
+{
+	const struct pvt_poly_term *term = poly->terms;
+	long tmp, ret = 0;
+	int deg;
+	do {
+		tmp = term->coef;
+		for (deg = 0; deg < term->deg; ++deg)
+			tmp = mult_frac(tmp, data, term->divider);
+		ret += tmp / term->divider_leftover;
+	} while ((term++)->deg);
+
+	return ret / poly->total_divider;
+}
+
+static inline u32 eswin_pvt_update(void __iomem *reg, u32 mask, u32 data)
+{
+	u32 old;
+
+	old = readl_relaxed(reg);
+	writel((old & ~mask) | (data & mask), reg);
+
+	return old & mask;
+}
+
+static inline void eswin_pvt_set_mode(struct pvt_hwmon *pvt, u32 mode)
+{
+	u32 old;
+
+	mode = FIELD_PREP(PVT_MODE_MASK, mode);
+
+	old = eswin_pvt_update(pvt->regs + PVT_ENA, PVT_ENA_EN, 0);
+	eswin_pvt_update(pvt->regs + PVT_MODE, PVT_MODE_MASK, mode);
+	eswin_pvt_update(pvt->regs + PVT_ENA, PVT_ENA_EN, old);
+}
+
+static inline u32 eswin_pvt_calc_trim(long temp)
+{
+	temp = clamp_val(temp, 0, PVT_TRIM_TEMP);
+
+	return DIV_ROUND_UP(temp, PVT_TRIM_STEP);
+}
+
+static inline void eswin_pvt_set_trim(struct pvt_hwmon *pvt, u32 val)
+{
+	u32 old;
+
+	old = eswin_pvt_update(pvt->regs + PVT_ENA, PVT_ENA_EN, 0);
+	writel(val, pvt->regs + PVT_TRIM);
+	eswin_pvt_update(pvt->regs + PVT_ENA, PVT_ENA_EN, old);
+}
+
+static irqreturn_t eswin_pvt_hard_isr(int irq, void *data)
+{
+	struct pvt_hwmon *pvt = data;
+	struct pvt_cache *cache;
+	u32 val;
+
+	eswin_pvt_update(pvt->regs + PVT_INT, PVT_INT_CLR, PVT_INT_CLR);
+
+	/*
+	 * Nothing special for alarm-less driver. Just read the data, update
+	 * the cache and notify a waiter of this event.
+	 */
+
+	val = readl(pvt->regs + PVT_DATA);
+
+	cache = &pvt->cache[pvt->sensor];
+
+	WRITE_ONCE(cache->data, FIELD_GET(PVT_DATA_OUT, val));
+
+	complete(&cache->conversion);
+
+	return IRQ_HANDLED;
+}
+
+static inline umode_t eswin_pvt_limit_is_visible(enum pvt_sensor_type type)
+{
+	return 0;
+}
+
+static inline umode_t eswin_pvt_pvt_alarm_is_visible(enum pvt_sensor_type type)
+{
+	return 0;
+}
+
+static int eswin_pvt_read_data(struct pvt_hwmon *pvt, enum pvt_sensor_type type,
+			 long *val)
+{
+	struct pvt_cache *cache = &pvt->cache[type];
+	unsigned long timeout;
+	u32 data;
+	int ret;
+
+	/*
+	 * Lock PVT conversion interface until data cache is updated. The
+	 * data read procedure is following: set the requested PVT sensor
+	 * mode, enable IRQ and conversion, wait until conversion is finished,
+	 * then disable conversion and IRQ, and read the cached data.
+	 */
+	ret = mutex_lock_interruptible(&pvt->iface_mtx);
+	if (ret)
+		return ret;
+
+	pvt->sensor = type;
+	eswin_pvt_set_mode(pvt, pvt_info[type].mode);
+
+	eswin_pvt_update(pvt->regs + PVT_ENA, PVT_ENA_EN, PVT_ENA_EN);
+
+	/*
+	 * Wait with timeout since in case if the sensor is suddenly powered
+	 * down the request won't be completed and the caller will hang up on
+	 * this procedure until the power is back up again. Multiply the
+	 * timeout by the factor of two to prevent a false timeout.
+	 */
+	timeout = 2 * usecs_to_jiffies(ktime_to_us(pvt->timeout));
+	if(type==PVT_TEMP){
+		timeout = 20 * usecs_to_jiffies(ktime_to_us(pvt->timeout));
+	}
+	ret = wait_for_completion_timeout(&cache->conversion, timeout);
+
+	eswin_pvt_update(pvt->regs + PVT_ENA, PVT_ENA_EN, 0);
+	eswin_pvt_update(pvt->regs + PVT_INT, PVT_INT_CLR, PVT_INT_CLR);
+
+	data = READ_ONCE(cache->data);
+
+	mutex_unlock(&pvt->iface_mtx);
+
+	if (!ret)
+		return -ETIMEDOUT;
+
+	if (type == PVT_TEMP)
+		*val = eswin_pvt_calc_poly(&poly_N_to_temp, data);
+	else if (type == PVT_VOLT)
+		*val = eswin_pvt_calc_poly(&poly_N_to_volt, data);
+	else
+		*val = data;
+
+	return 0;
+}
+
+static int eswin_pvt_read_limit(struct pvt_hwmon *pvt, enum pvt_sensor_type type,
+			  bool is_low, long *val)
+{
+	return -EOPNOTSUPP;
+}
+
+static int eswin_pvt_write_limit(struct pvt_hwmon *pvt, enum pvt_sensor_type type,
+			   bool is_low, long val)
+{
+	return -EOPNOTSUPP;
+}
+
+static int eswin_pvt_read_alarm(struct pvt_hwmon *pvt, enum pvt_sensor_type type,
+			  bool is_low, long *val)
+{
+	return -EOPNOTSUPP;
+}
+
+static const struct hwmon_channel_info *pvt_channel_info[] = {
+	HWMON_CHANNEL_INFO(chip,
+			   HWMON_C_REGISTER_TZ | HWMON_C_UPDATE_INTERVAL),
+	HWMON_CHANNEL_INFO(temp,
+			   HWMON_T_INPUT | HWMON_T_TYPE | HWMON_T_LABEL |
+			   HWMON_T_OFFSET),
+	HWMON_CHANNEL_INFO(in,
+			   HWMON_I_INPUT | HWMON_I_LABEL,
+			   HWMON_I_INPUT | HWMON_I_LABEL,
+			   HWMON_I_INPUT | HWMON_I_LABEL,
+			   HWMON_I_INPUT | HWMON_I_LABEL),
+	NULL
+};
+
+static inline bool eswin_pvt_hwmon_channel_is_valid(enum hwmon_sensor_types type,
+					      int ch)
+{
+	switch (type) {
+	case hwmon_temp:
+		if (ch < 0 || ch >= PVT_TEMP_CHS)
+			return false;
+		break;
+	case hwmon_in:
+		if (ch < 0 || ch >= PVT_VOLT_CHS)
+			return false;
+		break;
+	default:
+		break;
+	}
+
+	/* The rest of the types are independent from the channel number. */
+	return true;
+}
+
+static umode_t eswin_pvt_hwmon_is_visible(const void *data,
+				    enum hwmon_sensor_types type,
+				    u32 attr, int ch)
+{
+	if (!eswin_pvt_hwmon_channel_is_valid(type, ch))
+		return 0;
+
+	switch (type) {
+	case hwmon_chip:
+		switch (attr) {
+		case hwmon_chip_update_interval:
+			return 0644;
+		}
+		break;
+	case hwmon_temp:
+		switch (attr) {
+		case hwmon_temp_input:
+		case hwmon_temp_type:
+		case hwmon_temp_label:
+			return 0444;
+		case hwmon_temp_min:
+		case hwmon_temp_max:
+			return eswin_pvt_limit_is_visible(ch);
+		case hwmon_temp_min_alarm:
+		case hwmon_temp_max_alarm:
+			return eswin_pvt_pvt_alarm_is_visible(ch);
+		case hwmon_temp_offset:
+			return 0644;
+		}
+		break;
+	case hwmon_in:
+		switch (attr) {
+		case hwmon_in_input:
+		case hwmon_in_label:
+			return 0444;
+		case hwmon_in_min:
+		case hwmon_in_max:
+			return eswin_pvt_limit_is_visible(PVT_VOLT + ch);
+		case hwmon_in_min_alarm:
+		case hwmon_in_max_alarm:
+			return eswin_pvt_pvt_alarm_is_visible(PVT_VOLT + ch);
+		}
+		break;
+	default:
+		break;
+	}
+
+	return 0;
+}
+
+static int eswin_pvt_read_trim(struct pvt_hwmon *pvt, long *val)
+{
+	u32 data;
+
+	data = readl(pvt->regs + PVT_TRIM);
+	*val = data;
+
+	return 0;
+}
+
+static int eswin_pvt_write_trim(struct pvt_hwmon *pvt, long val)
+{
+	int ret;
+	/*
+	 * Serialize trim update, since a part of the register is changed and
+	 * the controller is supposed to be disabled during this operation.
+	 */
+	ret = mutex_lock_interruptible(&pvt->iface_mtx);
+	if (ret)
+		return ret;
+
+	eswin_pvt_set_trim(pvt, val);
+
+	mutex_unlock(&pvt->iface_mtx);
+
+	return 0;
+}
+
+static int eswin_pvt_read_timeout(struct pvt_hwmon *pvt, long *val)
+{
+	int ret;
+
+	ret = mutex_lock_interruptible(&pvt->iface_mtx);
+	if (ret)
+		return ret;
+
+	/* Return the result in msec as hwmon sysfs interface requires. */
+	*val = ktime_to_ms(pvt->timeout);
+
+	mutex_unlock(&pvt->iface_mtx);
+
+	return 0;
+}
+
+static int eswin_pvt_write_timeout(struct pvt_hwmon *pvt, long val)
+{
+	unsigned long rate;
+	ktime_t kt, cache;
+	u32 data;
+	int ret;
+
+	rate = clk_get_rate(pvt->clk);
+	if (!rate)
+		return -ENODEV;
+
+	/*
+	 * If alarms are enabled, the requested timeout must be divided
+	 * between all available sensors to have the requested delay
+	 * applicable to each individual sensor.
+	 */
+	cache = kt = ms_to_ktime(val);
+
+	/*
+	 * Subtract a constant lag, which always persists due to the limited
+	 * PVT sampling rate. Make sure the timeout is not negative.
+	 */
+	kt = ktime_sub_ns(kt, PVT_TOUT_MIN);
+	if (ktime_to_ns(kt) < 0)
+		kt = ktime_set(0, 0);
+
+	/*
+	 * Finally recalculate the timeout in terms of the reference clock
+	 * period.
+	 */
+	data = ktime_divns(kt * rate, NSEC_PER_SEC);
+
+	/*
+	 * Update the measurements delay, but lock the interface first, since
+	 * we have to disable PVT in order to have the new delay actually
+	 * updated.
+	 */
+	ret = mutex_lock_interruptible(&pvt->iface_mtx);
+	if (ret)
+		return ret;
+
+	pvt->timeout = cache;
+
+	mutex_unlock(&pvt->iface_mtx);
+
+	return 0;
+}
+
+static int eswin_pvt_hwmon_read(struct device *dev, enum hwmon_sensor_types type,
+			  u32 attr, int ch, long *val)
+{
+	struct pvt_hwmon *pvt = dev_get_drvdata(dev);
+
+	if (!eswin_pvt_hwmon_channel_is_valid(type, ch))
+		return -EINVAL;
+
+	switch (type) {
+	case hwmon_chip:
+		switch (attr) {
+		case hwmon_chip_update_interval:
+			return eswin_pvt_read_timeout(pvt, val);
+		}
+		break;
+	case hwmon_temp:
+		switch (attr) {
+		case hwmon_temp_input:
+			return eswin_pvt_read_data(pvt, ch, val);
+		case hwmon_temp_type:
+			*val = 1;
+			return 0;
+		case hwmon_temp_min:
+			return eswin_pvt_read_limit(pvt, ch, true, val);
+		case hwmon_temp_max:
+			return eswin_pvt_read_limit(pvt, ch, false, val);
+		case hwmon_temp_min_alarm:
+			return eswin_pvt_read_alarm(pvt, ch, true, val);
+		case hwmon_temp_max_alarm:
+			return eswin_pvt_read_alarm(pvt, ch, false, val);
+		case hwmon_temp_offset:
+			return eswin_pvt_read_trim(pvt, val);
+		}
+		break;
+	case hwmon_in:
+		switch (attr) {
+		case hwmon_in_input:
+			return eswin_pvt_read_data(pvt, PVT_VOLT + ch, val);
+		case hwmon_in_min:
+			return eswin_pvt_read_limit(pvt, PVT_VOLT + ch, true, val);
+		case hwmon_in_max:
+			return eswin_pvt_read_limit(pvt, PVT_VOLT + ch, false, val);
+		case hwmon_in_min_alarm:
+			return eswin_pvt_read_alarm(pvt, PVT_VOLT + ch, true, val);
+		case hwmon_in_max_alarm:
+			return eswin_pvt_read_alarm(pvt, PVT_VOLT + ch, false, val);
+		}
+		break;
+	default:
+		break;
+	}
+
+	return -EOPNOTSUPP;
+}
+
+static int eswin_pvt_hwmon_read_string(struct device *dev,
+				 enum hwmon_sensor_types type,
+				 u32 attr, int ch, const char **str)
+{
+	if (!eswin_pvt_hwmon_channel_is_valid(type, ch))
+		return -EINVAL;
+
+	switch (type) {
+	case hwmon_temp:
+		switch (attr) {
+		case hwmon_temp_label:
+			*str = pvt_info[ch].label;
+			return 0;
+		}
+		break;
+	case hwmon_in:
+		switch (attr) {
+		case hwmon_in_label:
+			*str = pvt_info[PVT_VOLT + ch].label;
+			return 0;
+		}
+		break;
+	default:
+		break;
+	}
+
+	return -EOPNOTSUPP;
+}
+
+static int eswin_pvt_hwmon_write(struct device *dev, enum hwmon_sensor_types type,
+			   u32 attr, int ch, long val)
+{
+	struct pvt_hwmon *pvt = dev_get_drvdata(dev);
+
+	if (!eswin_pvt_hwmon_channel_is_valid(type, ch))
+		return -EINVAL;
+
+	switch (type) {
+	case hwmon_chip:
+		switch (attr) {
+		case hwmon_chip_update_interval:
+			return eswin_pvt_write_timeout(pvt, val);
+		}
+		break;
+	case hwmon_temp:
+		switch (attr) {
+		case hwmon_temp_min:
+			return eswin_pvt_write_limit(pvt, ch, true, val);
+		case hwmon_temp_max:
+			return eswin_pvt_write_limit(pvt, ch, false, val);
+		case hwmon_temp_offset:
+			return eswin_pvt_write_trim(pvt, val);
+		}
+		break;
+	case hwmon_in:
+		switch (attr) {
+		case hwmon_in_min:
+			return eswin_pvt_write_limit(pvt, PVT_VOLT + ch, true, val);
+		case hwmon_in_max:
+			return eswin_pvt_write_limit(pvt, PVT_VOLT + ch, false, val);
+		}
+		break;
+	default:
+		break;
+	}
+
+	return -EOPNOTSUPP;
+}
+
+static const struct hwmon_ops pvt_hwmon_ops = {
+	.is_visible = eswin_pvt_hwmon_is_visible,
+	.read = eswin_pvt_hwmon_read,
+	.read_string = eswin_pvt_hwmon_read_string,
+	.write = eswin_pvt_hwmon_write
+};
+
+static const struct hwmon_chip_info pvt_hwmon_info = {
+	.ops = &pvt_hwmon_ops,
+	.info = pvt_channel_info
+};
+
+static void pvt_clear_data(void *data)
+{
+	struct pvt_hwmon *pvt = data;
+	int idx;
+
+	for (idx = 0; idx < PVT_SENSORS_NUM; ++idx)
+		complete_all(&pvt->cache[idx].conversion);
+
+	mutex_destroy(&pvt->iface_mtx);
+}
+
+static struct pvt_hwmon *eswin_pvt_create_data(struct platform_device *pdev)
+{
+	struct device *dev = &pdev->dev;
+	struct pvt_hwmon *pvt;
+	int ret, idx;
+
+	pvt = devm_kzalloc(dev, sizeof(*pvt), GFP_KERNEL);
+	if (!pvt)
+		return ERR_PTR(-ENOMEM);
+
+	ret = devm_add_action(dev, pvt_clear_data, pvt);
+	if (ret) {
+		dev_err(dev, "Can't add PVT data clear action\n");
+		return ERR_PTR(ret);
+	}
+
+	pvt->dev = dev;
+	pvt->sensor = PVT_SENSOR_FIRST;
+	mutex_init(&pvt->iface_mtx);
+
+	for (idx = 0; idx < PVT_SENSORS_NUM; ++idx)
+		init_completion(&pvt->cache[idx].conversion);
+
+	return pvt;
+}
+
+static int eswin_pvt_request_regs(struct pvt_hwmon *pvt)
+{
+	struct platform_device *pdev = to_platform_device(pvt->dev);
+	struct resource *res;
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	if (!res) {
+		dev_err(pvt->dev, "Couldn't find PVT memresource\n");
+		return -EINVAL;
+	}
+
+	pvt->regs = devm_ioremap_resource(pvt->dev, res);
+	if (IS_ERR(pvt->regs))
+		return PTR_ERR(pvt->regs);
+
+	return 0;
+}
+
+static void eswin_pvt_remove(void *data)
+{
+	int ret;
+	struct pvt_hwmon *pvt = data;
+	ret = reset_control_assert(pvt->pvt_rst);
+	WARN_ON(0 != ret);
+	clk_disable_unprepare(pvt->clk);
+}
+
+static int eswin_pvt_request_clks(struct pvt_hwmon *pvt)
+{
+	int ret;
+
+	pvt->clk = devm_clk_get(pvt->dev, "pvt_clk");
+	if (IS_ERR(pvt->clk)) {
+		dev_err(pvt->dev, "Couldn't get PVT clock\n");
+		return -ENODEV;
+	}
+
+	ret = clk_prepare_enable(pvt->clk);
+	if (ret) {
+		dev_err(pvt->dev, "Couldn't enable the PVT clocks\n");
+		return ret;
+	}
+
+	return 0;
+}
+
+static int eswin_pvt_request_rst(struct pvt_hwmon *pvt)
+{
+	int ret;
+	pvt->pvt_rst = devm_reset_control_get_optional(pvt->dev, "pvt_rst");
+	if(IS_ERR_OR_NULL(pvt->pvt_rst)){
+		dev_err(pvt->dev, "Couldn't get PVT reset\n");
+	}
+	ret = reset_control_reset(pvt->pvt_rst);
+	WARN_ON(0 != ret);
+	return 0;
+}
+
+static int eswin_pvt_check_pwr(struct pvt_hwmon *pvt)
+{
+	unsigned long tout;
+	int ret = 0;
+	u32 data;
+
+	/*
+	 * Test out the sensor conversion functionality. If it is not done on
+	 * time then the domain must have been unpowered and we won't be able
+	 * to use the device later in this driver.
+	 * Note If the power source is lost during the normal driver work the
+	 * data read procedure will either return -ETIMEDOUT (for the
+	 * alarm-less driver configuration) or just stop the repeated
+	 * conversion. In the later case alas we won't be able to detect the
+	 * problem.
+	 */
+
+	eswin_pvt_update(pvt->regs + PVT_ENA, PVT_ENA_EN, PVT_ENA_EN);
+	readl(pvt->regs + PVT_DATA);
+
+	tout = PVT_TOUT_MIN / NSEC_PER_USEC;
+	usleep_range(tout, 2 * tout);
+
+	data = readl(pvt->regs + PVT_DATA);
+
+	eswin_pvt_update(pvt->regs + PVT_ENA, PVT_ENA_EN, 0);
+	eswin_pvt_update(pvt->regs + PVT_INT, PVT_INT_CLR, PVT_INT_CLR);
+
+	return ret;
+}
+
+static int eswin_pvt_init_iface(struct pvt_hwmon *pvt)
+{
+	unsigned long rate;
+
+	rate = clk_get_rate(pvt->clk);
+	if (!rate) {
+		dev_err(pvt->dev, "Invalid reference clock rate\n");
+		return -ENODEV;
+	}
+
+	/*
+	 * Make sure all interrupts and controller are disabled so not to
+	 * accidentally have ISR executed before the driver data is fully
+	 * initialized. Clear the IRQ status as well.
+	 */
+	eswin_pvt_update(pvt->regs + PVT_ENA, PVT_ENA_EN, 0);
+	eswin_pvt_update(pvt->regs + PVT_INT, PVT_INT_CLR, PVT_INT_CLR);
+
+	readl(pvt->regs + PVT_DATA);
+
+	/* Setup default sensor mode, timeout and temperature trim. */
+	eswin_pvt_set_mode(pvt, pvt_info[pvt->sensor].mode);
+
+	/*
+	 * Preserve the current ref-clock based delay (Ttotal) between the
+	 * sensors data samples in the driver data so not to recalculate it
+	 * each time on the data requests and timeout reads. It consists of the
+	 * delay introduced by the internal ref-clock timer (N / Fclk) and the
+	 * constant timeout caused by each conversion latency (Tmin):
+	 *   Ttotal = N / Fclk + Tmin
+	 * If alarms are enabled the sensors are polled one after another and
+	 * in order to get the next measurement of a particular sensor the
+	 * caller will have to wait for at most until all the others are
+	 * polled. In that case the formulae will look a bit different:
+	 *   Ttotal = 5 * (N / Fclk + Tmin)
+	 */
+
+	pvt->timeout = ktime_set(PVT_TOUT_DEF, 0);
+	pvt->timeout = ktime_divns(pvt->timeout, rate);
+	pvt->timeout = ktime_add_ns(pvt->timeout, PVT_TOUT_MIN);
+
+	return 0;
+}
+
+static int eswin_pvt_request_irq(struct pvt_hwmon *pvt)
+{
+	struct platform_device *pdev = to_platform_device(pvt->dev);
+	int ret;
+
+	pvt->irq = platform_get_irq(pdev, 0);
+	if (pvt->irq < 0)
+		return pvt->irq;
+
+	ret = devm_request_threaded_irq(pvt->dev, pvt->irq,
+					eswin_pvt_hard_isr, NULL,
+					IRQF_SHARED | IRQF_TRIGGER_HIGH,
+					"pvt", pvt);
+	if (ret) {
+		dev_err(pvt->dev, "Couldn't request PVT IRQ\n");
+		return ret;
+	}
+
+	return 0;
+}
+
+static int eswin_pvt_create_hwmon(struct pvt_hwmon *pvt)
+{
+	pvt->hwmon = devm_hwmon_device_register_with_info(pvt->dev, "pvt", pvt,
+		&pvt_hwmon_info, NULL);
+	if (IS_ERR(pvt->hwmon)) {
+		dev_err(pvt->dev, "Couldn't create hwmon device\n");
+		return PTR_ERR(pvt->hwmon);
+	}
+
+	return 0;
+}
+
+static int eswin_pvt_probe(struct platform_device *pdev)
+{
+	struct pvt_hwmon *pvt;
+	int ret;
+
+	pvt = eswin_pvt_create_data(pdev);
+	if (IS_ERR(pvt))
+		return PTR_ERR(pvt);
+
+	ret = eswin_pvt_request_regs(pvt);
+	if (ret)
+		return ret;
+
+	ret = eswin_pvt_request_clks(pvt);
+	if (ret)
+		return ret;
+
+	ret = eswin_pvt_request_rst(pvt);
+	if (ret)
+		return ret;
+
+	ret = eswin_pvt_check_pwr(pvt);
+	if (ret)
+		return ret;
+
+	ret = eswin_pvt_init_iface(pvt);
+	if (ret)
+		return ret;
+
+	ret = eswin_pvt_request_irq(pvt);
+	if (ret)
+		return ret;
+
+	ret = eswin_pvt_create_hwmon(pvt);
+	if (ret)
+		return ret;
+
+	ret = devm_add_action_or_reset(pvt->dev, eswin_pvt_remove, pvt);
+	if (ret) {
+		dev_err(pvt->dev, "Can't add PVT clocks disable action\n");
+		return ret;
+	}
+
+	return 0;
+}
+
+static const struct of_device_id pvt_of_match[] = {
+	{ .compatible = "eswin,eswin-pvt" },
+	{ }
+};
+MODULE_DEVICE_TABLE(of, pvt_of_match);
+
+static struct platform_driver pvt_driver = {
+	.probe = eswin_pvt_probe,
+	.driver = {
+		.name = "eswin-pvt",
+		.of_match_table = pvt_of_match
+	},
+};
+module_platform_driver(pvt_driver);
+
+MODULE_DESCRIPTION("Eswin PVT driver");
+MODULE_AUTHOR("Yu Bingzheng <yubingzheng@eswincomputing.com>");
+MODULE_LICENSE("GPL v2");
diff --git a/drivers/hwmon/eswin_pvt.h b/drivers/hwmon/eswin_pvt.h
new file mode 100644
index 000000000000..f321d44a123d
--- /dev/null
+++ b/drivers/hwmon/eswin_pvt.h
@@ -0,0 +1,226 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (C) ESWIN Electronics Co.Ltd
+ *
+ * Eswin Process, Voltage, Temperature sensor driver
+ */
+#ifndef __HWMON_ESWIN_PVT_H__
+#define __HWMON_ESWIN_PVT_H__
+
+#include <linux/completion.h>
+#include <linux/hwmon.h>
+#include <linux/kernel.h>
+#include <linux/ktime.h>
+#include <linux/mutex.h>
+#include <linux/seqlock.h>
+
+/* Eswin PVT registers and their bitfields */
+#define PVT_DIV               0x00
+#define PVT_TRIM              0x04
+#define PVT_TRIM_G            GENMASK(4,0)
+#define PVT_TRIM_O            GENMASK(13,8)
+#define PVT_MODE              0x08
+#define PVT_MODE_MASK         GENMASK(2, 0)
+#define PVT_CTRL_MODE_TEMP    0x0
+#define PVT_CTRL_MODE_VOLT    0x4
+#define PVT_CTRL_MODE_LVT     0x1
+#define PVT_CTRL_MODE_ULVT    0x2
+#define PVT_CTRL_MODE_SVT     0x3
+#define PVT_MODE_PSAMPLE_0    BIT(0)
+#define PVT_MODE_PSAMPLE_1    BIT(1)
+#define PVT_MODE_VSAMPLE      BIT(2)
+#define PVT_ENA               0x0c
+#define PVT_ENA_EN            BIT(0)
+#define PVT_INT               0x10
+#define PVT_INT_CLR           BIT(1)
+#define PVT_DATA              0x14
+#define PVT_DATA_OUT          GENMASK(9,0)
+
+/* alarm related */
+#define PVT_TTHRES			0x08
+#define PVT_VTHRES			0x0C
+#define PVT_LTHRES			0x10
+#define PVT_ULTHRES			0x14
+#define PVT_STHRES			0x18
+#define PVT_INTR_DVALID			BIT(0)
+#define PVT_INTR_TTHRES_LO		BIT(1)
+#define PVT_INTR_TTHRES_HI		BIT(2)
+#define PVT_INTR_VTHRES_LO		BIT(3)
+#define PVT_INTR_VTHRES_HI		BIT(4)
+#define PVT_INTR_LTHRES_LO		BIT(5)
+#define PVT_INTR_LTHRES_HI		BIT(6)
+#define PVT_INTR_ULTHRES_LO		BIT(7)
+#define PVT_INTR_ULTHRES_HI		BIT(8)
+#define PVT_INTR_STHRES_LO		BIT(9)
+#define PVT_INTR_STHRES_HI		BIT(10)
+
+/*
+ * PVT sensors-related limits and default values
+ * @PVT_TEMP_MIN: Minimal temperature in millidegrees of Celsius.
+ * @PVT_TEMP_MAX: Maximal temperature in millidegrees of Celsius.
+ * @PVT_TEMP_CHS: Number of temperature hwmon channels.
+ * @PVT_VOLT_MIN: Minimal voltage in mV.
+ * @PVT_VOLT_MAX: Maximal voltage in mV.
+ * @PVT_VOLT_CHS: Number of voltage hwmon channels.
+ * @PVT_DATA_MIN: Minimal PVT raw data value.
+ * @PVT_DATA_MAX: Maximal PVT raw data value.
+ * @PVT_TRIM_MIN: Minimal temperature sensor trim value.
+ * @PVT_TRIM_MAX: Maximal temperature sensor trim value.
+ * @PVT_TRIM_DEF: Default temperature sensor trim value (set a proper value
+ *		  when one is determined for ESWIN SoC).
+ * @PVT_TRIM_TEMP: Maximum temperature encoded by the trim factor.
+ * @PVT_TRIM_STEP: Temperature stride corresponding to the trim value.
+ * @PVT_TOUT_MIN: Minimal timeout between samples in nanoseconds.
+ * @PVT_TOUT_DEF: Default data measurements timeout. In case if alarms are
+ *		  activated the PVT IRQ is enabled to be raised after each
+ *		  conversion in order to have the thresholds checked and the
+ *		  converted value cached. Too frequent conversions may cause
+ *		  the system CPU overload. Lets set the 50ms delay between
+ *		  them by default to prevent this.
+ */
+#define PVT_TEMP_MIN		-40000L
+#define PVT_TEMP_MAX		125000L
+#define PVT_TEMP_CHS		1
+#define PVT_VOLT_MIN		720L
+#define PVT_VOLT_MAX		880L
+#define PVT_VOLT_CHS		4
+#define PVT_DATA_MIN		0
+#define PVT_DATA_DATA_FLD       0
+#define PVT_CTRL_TRIM_FLD       4
+#define PVT_CTRL_TRIM_MASK      GENMASK(8,4)
+#define PVT_DATA_MAX		(PVT_DATA_DATA_MASK >> PVT_DATA_DATA_FLD)
+#define PVT_TRIM_MIN		0
+#define PVT_TRIM_MAX		(PVT_CTRL_TRIM_MASK >> PVT_CTRL_TRIM_FLD)
+#define PVT_TRIM_TEMP		7130
+#define PVT_TRIM_STEP		(PVT_TRIM_TEMP / PVT_TRIM_MAX)
+#define PVT_TRIM_DEF		0
+#define PVT_TOUT_MIN		(NSEC_PER_SEC / 3000)
+# define PVT_TOUT_DEF		0
+
+/*
+ * enum pvt_sensor_type - ESWIN PVT sensor types (correspond to each PVT
+ *			  sampling mode)
+ * @PVT_SENSOR*: helpers to traverse the sensors in loops.
+ * @PVT_TEMP: PVT Temperature sensor.
+ * @PVT_VOLT: PVT Voltage sensor.
+ * @PVT_LVT: PVT Low-Voltage threshold sensor.
+ * @PVT_HVT: PVT High-Voltage threshold sensor.
+ * @PVT_SVT: PVT Standard-Voltage threshold sensor.
+ */
+enum pvt_sensor_type {
+	PVT_SENSOR_FIRST,
+	PVT_TEMP = PVT_SENSOR_FIRST,
+	PVT_VOLT,
+	PVT_LVT,
+	PVT_ULVT,
+	PVT_SVT,
+	PVT_SENSOR_LAST = PVT_SVT,
+	PVT_SENSORS_NUM
+};
+
+/*
+ * struct pvt_sensor_info - ESWIN PVT sensor informational structure
+ * @channel: Sensor channel ID.
+ * @label: hwmon sensor label.
+ * @mode: PVT mode corresponding to the channel.
+ * @thres_base: upper and lower threshold values of the sensor.
+ * @thres_sts_lo: low threshold status bitfield.
+ * @thres_sts_hi: high threshold status bitfield.
+ * @type: Sensor type.
+ * @attr_min_alarm: Min alarm attribute ID.
+ * @attr_min_alarm: Max alarm attribute ID.
+ */
+struct pvt_sensor_info {
+	int channel;
+	const char *label;
+	u32 mode;
+	unsigned long thres_base;
+	u32 thres_sts_lo;
+	u32 thres_sts_hi;
+	enum hwmon_sensor_types type;
+	u32 attr_min_alarm;
+	u32 attr_max_alarm;
+};
+
+#define PVT_SENSOR_INFO(_ch, _label, _type, _mode, _thres)	\
+	{							\
+		.channel = _ch,					\
+		.label = _label,				\
+		.mode = PVT_CTRL_MODE_ ##_mode,			\
+		.thres_base = PVT_ ##_thres,			\
+		.thres_sts_lo = PVT_INTR_ ##_thres## _LO,	\
+		.thres_sts_hi = PVT_INTR_ ##_thres## _HI,	\
+		.type = _type,					\
+		.attr_min_alarm = _type## _min,			\
+		.attr_max_alarm = _type## _max,			\
+	}
+
+/*
+ * struct pvt_cache - PVT sensors data cache
+ * @data: data cache in raw format.
+ * @thres_sts_lo: low threshold status saved on the previous data conversion.
+ * @thres_sts_hi: high threshold status saved on the previous data conversion.
+ * @data_seqlock: cached data seq-lock.
+ * @conversion: data conversion completion.
+ */
+struct pvt_cache {
+	u32 data;
+	struct completion conversion;
+};
+
+/*
+ * struct pvt_hwmon - Eswin PVT private data
+ * @dev: device structure of the PVT platform device.
+ * @hwmon: hwmon device structure.
+ * @regs: pointer to the Eswin PVT registers region.
+ * @irq: PVT events IRQ number.
+ * @clk: PVT core clock (1.2MHz).
+ * @pvt_rst: pointer to the reset descriptor.
+ * @iface_mtx: Generic interface mutex (used to lock the alarm registers
+ *	       when the alarms enabled, or the data conversion interface
+ *	       if alarms are disabled).
+ * @sensor: current PVT sensor the data conversion is being performed for.
+ * @cache: data cache descriptor.
+ * @timeout: conversion timeout cache.
+ */
+struct pvt_hwmon {
+	struct device *dev;
+	struct device *hwmon;
+
+	void __iomem *regs;
+	int irq;
+
+	struct clk *clk;
+	struct reset_control *pvt_rst;
+	struct mutex iface_mtx;
+	enum pvt_sensor_type sensor;
+	struct pvt_cache cache[PVT_SENSORS_NUM];
+	ktime_t timeout;
+};
+
+/*
+ * struct pvt_poly_term - a term descriptor of the PVT data translation
+ *			  polynomial
+ * @deg: degree of the term.
+ * @coef: multiplication factor of the term.
+ * @divider: distributed divider per each degree.
+ * @divider_leftover: divider leftover, which couldn't be redistributed.
+ */
+struct pvt_poly_term {
+	unsigned int deg;
+	long coef;
+	long divider;
+	long divider_leftover;
+};
+
+/*
+ * struct pvt_poly - PVT data translation polynomial descriptor
+ * @total_divider: total data divider.
+ * @terms: polynomial terms up to a free one.
+ */
+struct pvt_poly {
+	long total_divider;
+	struct pvt_poly_term terms[];
+};
+
+#endif /* __HWMON_ESWIN_PVT_H__ */
diff --git a/drivers/hwmon/pac193x.c b/drivers/hwmon/pac193x.c
new file mode 100644
index 000000000000..5ca189d72474
--- /dev/null
+++ b/drivers/hwmon/pac193x.c
@@ -0,0 +1,818 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ *  Driver for microchip  pac1931,pac1932,pac1933,pac1934 power monitor chips
+ *
+ * Copyright 2024, Beijing ESWIN Computing Technology Co., Ltd.. All rights reserved.
+ * SPDX-License-Identifier: GPL-2.0
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, version 2.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <https://www.gnu.org/licenses/>.
+ *
+ * Authors: Yang Wei <yangwei1@eswincomputing.com>
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/err.h>
+#include <linux/slab.h>
+#include <linux/i2c.h>
+#include <linux/hwmon.h>
+#include <linux/hwmon-sysfs.h>
+#include <linux/jiffies.h>
+#include <linux/of_device.h>
+#include <linux/of.h>
+#include <linux/delay.h>
+#include <linux/util_macros.h>
+
+#define PAC193X_MAX_CHAN_CNT 4
+
+#define PAC193X_REGISTERS 0x27
+#define PAC193X_VPOWERN_ACC_LEN 6
+#define PAC193X_VOLT_VALUE_LEN 2
+#define PAC193X_VPOWERN_VALUE_LEN 4
+#define PAC193X_ACC_COUNT_LEN 3
+
+#define PAC193X_CMD_REFRESH 0x0
+#define PAC193X_CMD_CTRL 0x1
+#define PAC193X_CMD_ACC_COUNT 0x2
+#define PAC193X_CMD_VPOWER1_ACC 0x3
+#define PAC193X_CMD_VPOWER2_ACC 0x4
+#define PAC193X_CMD_VPOWER3_ACC 0x5
+#define PAC193X_CMD_VPOWER4_ACC 0x6
+#define PAC193X_CMD_VBUS1 0x7
+#define PAC193X_CMD_VBUS2 0x8
+#define PAC193X_CMD_VBUS3 0x9
+#define PAC193X_CMD_VBUS4 0xa
+#define PAC193X_CMD_VSENSE1 0xb
+#define PAC193X_CMD_VSENSE2 0xc
+#define PAC193X_CMD_VSENSE3 0xd
+#define PAC193X_CMD_VSENSE4 0xe
+#define PAC193X_CMD_VBUS1_AVG 0xf
+#define PAC193X_CMD_VBUS2_AVG 0x10
+#define PAC193X_CMD_VBUS3_AVG 0x11
+#define PAC193X_CMD_VBUS4_AVG 0x12
+#define PAC193X_CMD_VSENSE1_AVG 0x13
+#define PAC193X_CMD_VSENSE2_AVG 0x14
+#define PAC193X_CMD_VSENSE3_AVG 0x15
+#define PAC193X_CMD_VSENSE4_AVG 0x16
+#define PAC193X_CMD_VPOWER1 0x17
+#define PAC193X_CMD_VPOWER2 0x18
+#define PAC193X_CMD_VPOWER3 0x19
+#define PAC193X_CMD_VPOWER4 0x1a
+#define PAC193X_CMD_CHANNEL_SMBUS 0x1c
+#define PAC193X_CMD_NEG_PWR 0x1D
+#define PAC193X_CMD_REFRESH_G 0x1E
+#define PAC193X_CMD_REFRESH_V 0x1F
+#define PAC193X_CMD_SLOW 0x20
+#define PAC193X_CMD_CTRL_ACT 0x21
+#define PAC193X_CMD_DIS_ACT 0x22
+#define PAC193X_CMD_NEG_PWR_ACT 0x23
+#define PAC193X_CMD_CTRL_LAT 0x24
+#define PAC193X_CMD_DIS_LAT 0x25
+#define PAC193X_CMD_NEG_PWR_LAT 0x26
+#define PAC193X_CMD_PID 0xFD
+#define PAC193X_CMD_MID 0xFE
+#define PAC193X_CMD_REVERSION_ID 0xFF
+
+#define PAC1932X_COSTANT_PWR_M 3200000000ull /* 3.2V^2*1000mO*/
+#define PAC1932X_COSTANT_CURRENT_M 100000 /* 100mv*1000mO*/
+
+struct pac193x_data {
+	struct mutex config_lock;
+	struct i2c_client *client;
+	u32 update_time_ms;
+	u32 energy_acc_count;
+	struct workqueue_struct *update_workqueue;
+	struct delayed_work update_work;
+	u32 vbus_denominator[PAC193X_MAX_CHAN_CNT];
+	u32 vsense_denominator[PAC193X_MAX_CHAN_CNT];
+	u32 vpower_denominator[PAC193X_MAX_CHAN_CNT];
+	u32 sense_resistances[PAC193X_MAX_CHAN_CNT];
+	u32 sample_rate;
+};
+
+enum PAC193X_CHAN_INDEX {
+	pac1931_index = 0,
+	pac1932_index,
+	pac1933_index,
+	pac1934_index
+};
+
+static int pac193x_get_energy(struct device *dev, u8 commmd, u8 chan, long *val)
+{
+	struct pac193x_data *data = dev_get_drvdata(dev);
+	int ret;
+	u64 cache = 0;
+	u8 *pcache = (u8 *)&cache;
+	u64 energy_value = 0;
+
+	commmd = commmd + chan;
+	dev_dbg(dev, "%s.%d,chan:%d,commad:%d,LEN:%ld\n", __FUNCTION__,
+		__LINE__, chan, commmd, sizeof(cache));
+	mutex_lock(&data->config_lock);
+	ret = i2c_smbus_read_i2c_block_data(data->client, commmd,
+					    PAC193X_VPOWERN_ACC_LEN, pcache);
+	mutex_unlock(&data->config_lock);
+
+	energy_value = ((cache & 0xff) << 40) | (((cache >> 8) & 0xff) << 32) |
+		       (((cache >> 16) & 0xff) << 24) |
+		       (((cache >> 24) & 0xff) << 16) |
+		       (((cache >> 32) & 0xff) << 8) | (((cache >> 40) & 0xff));
+	energy_value = energy_value & 0xffffffffffffULL;
+	dev_dbg(dev,
+		"%s.%d,commd:0x%x,value:%lld,ret:%d,resistances:%u,denominator:%u,sample_rate:%u\n",
+		__FUNCTION__, __LINE__, commmd, energy_value, ret,
+		data->sense_resistances[chan], data->vpower_denominator[chan],
+		data->sample_rate);
+
+	/* energy=3200000*Vpower/(Rsense*denominator*sample_rate) */
+	energy_value = ((energy_value / (u64)data->vpower_denominator[chan]) *
+			(PAC1932X_COSTANT_PWR_M /
+			 (data->sense_resistances[chan] * data->sample_rate)));
+
+	*val = energy_value;
+
+	return 0;
+}
+
+static u16 pac193x_get_word(struct pac193x_data *data, u8 commmd)
+{
+	int ret;
+	u16 cache = 0;
+
+	mutex_lock(&data->config_lock);
+	ret = i2c_smbus_read_word_data(data->client, commmd);
+	mutex_unlock(&data->config_lock);
+	cache = ((ret & 0xff) << 8) | ((ret >> 8) & 0xff);
+	dev_dbg(&data->client->dev, "%s.%d,commd:0x%x,value:0x%x,ret:0x%x\n",
+		__FUNCTION__, __LINE__, commmd, cache, ret);
+
+	return cache;
+}
+
+static int pac193x_get_volt(struct device *dev, u8 commmd, u8 chan, long *val)
+{
+	struct pac193x_data *data = dev_get_drvdata(dev);
+	u16 cache = 0;
+
+	commmd = commmd + chan;
+	dev_dbg(dev, "%s.%d,commd:0x%x,chan:%d,vbus_denominator:%d\n",
+		__FUNCTION__, __LINE__, commmd, chan,
+		data->vbus_denominator[chan]);
+	cache = pac193x_get_word(data, commmd);
+	/*to mV*/
+	cache = cache * 1000 / data->vbus_denominator[chan];
+	*val = cache;
+	return 0;
+}
+
+static int pac193x_get_current(struct device *dev, u8 commmd, u8 chan,
+			       long *val)
+{
+	struct pac193x_data *data = dev_get_drvdata(dev);
+	u16 cache = 0;
+
+	commmd = commmd + chan;
+	dev_dbg(dev,
+		"%s.%d,commd:0x%x,chan:%d,vbus_denominator:%d,resistances:%d\n",
+		__FUNCTION__, __LINE__, commmd, chan,
+		data->vsense_denominator[chan], data->sense_resistances[chan]);
+	cache = pac193x_get_word(data, commmd);
+	/* I=Vsense*100/(Rsense*denominator)	*/
+	cache = cache * PAC1932X_COSTANT_CURRENT_M /
+		(data->vsense_denominator[chan] *
+		 data->sense_resistances[chan]);
+	*val = cache;
+	return 0;
+}
+
+static int pac193x_get_power(struct device *dev, u8 commmd, u8 chan, long *val)
+{
+	struct pac193x_data *data = dev_get_drvdata(dev);
+	int ret;
+	u32 cache = 0;
+	u8 *pcache = (u8 *)&cache;
+	u64 pwr_value = 0;
+
+	commmd = commmd + chan;
+	mutex_lock(&data->config_lock);
+	ret = i2c_smbus_read_i2c_block_data(data->client, commmd,
+					    PAC193X_VPOWERN_VALUE_LEN, pcache);
+	mutex_unlock(&data->config_lock);
+	pwr_value = ((cache & 0xff) << 24) | (((cache >> 8) & 0xff) << 16) |
+		    (((cache >> 16) & 0xff) << 8) | ((cache >> 24) & 0xff);
+	pwr_value = pwr_value >> 4;
+	dev_dbg(dev,
+		"%s.%d,commd:0x%x,chan:%d,value:0x%x,pwr_value:0x%llx,%llu,ret:%d,resistances:%u,denominator:%u\n",
+		__FUNCTION__, __LINE__, commmd, chan, cache, pwr_value,
+		pwr_value, ret, data->sense_resistances[chan],
+		data->vpower_denominator[chan]);
+	/* pwr=3200000*Vpower/Rsense*denominator */
+	pwr_value = pwr_value * PAC1932X_COSTANT_PWR_M /
+		    ((u64)data->sense_resistances[chan] *
+		     (u64)data->vpower_denominator[chan]);
+	*val = pwr_value;
+	return 0;
+}
+
+static int pac193x_send_refresh_cmd(struct pac193x_data *data, u8 command)
+{
+	int ret = 0;
+
+	mutex_lock(&data->config_lock);
+	ret = i2c_smbus_write_byte(data->client, command);
+	mutex_unlock(&data->config_lock);
+	dev_dbg(&data->client->dev, "%s.%d,commd:0x%x,ret:%d\n", __FUNCTION__,
+		__LINE__, command, ret);
+	return ret;
+}
+
+static ssize_t pac193x_refresh_store(struct device *dev,
+				     struct device_attribute *da,
+				     const char *buf, size_t count)
+{
+	struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(da);
+	struct pac193x_data *data = dev_get_drvdata(dev);
+
+	pac193x_send_refresh_cmd(data, (u8)sensor_attr->index);
+	return count;
+}
+
+static struct sensor_device_attribute pac1934_refreshs[] = {
+	SENSOR_ATTR_WO(refresh_clear_acc, pac193x_refresh, PAC193X_CMD_REFRESH),
+	SENSOR_ATTR_WO(refresh_all_193x, pac193x_refresh,
+		       PAC193X_CMD_REFRESH_G),
+	SENSOR_ATTR_WO(refresh_updata_value, pac193x_refresh,
+		       PAC193X_CMD_REFRESH_V),
+};
+
+static u8 pac193x_read_byte_data(struct pac193x_data *data, u8 command)
+{
+	int cache = 0;
+	int cnt = 0;
+	while (1) {
+		mutex_lock(&data->config_lock);
+		cache = i2c_smbus_read_byte_data(data->client, command);
+		mutex_unlock(&data->config_lock);
+		if (0xff != cache) {
+			break;
+		}
+		cnt++;
+		if (cnt > 100) {
+			dev_err(&data->client->dev,
+				"get command:%d value error\n", command);
+			return 0xff;
+		}
+	}
+	return (u8)cache;
+}
+
+static ssize_t pac193x_ctrl_show(struct device *dev,
+				 struct device_attribute *attr, char *buf)
+{
+	struct pac193x_data *data = dev_get_drvdata(dev);
+	u8 set_val = 0, act_val = 0, lat_val = 0;
+
+	set_val = pac193x_read_byte_data(data, PAC193X_CMD_CTRL);
+	act_val = pac193x_read_byte_data(data, PAC193X_CMD_CTRL_ACT);
+	lat_val = pac193x_read_byte_data(data, PAC193X_CMD_CTRL_LAT);
+
+	return sprintf(buf,
+		       "%16s:%6s,%6s,%6s\n"
+		       "%16s:%6d,%6d,%6d\n"
+		       "%16s:%6d,%6d,%6d\n"
+		       "%16s:%6d,%6d,%6d\n"
+		       "%16s:%6d,%6d,%6d\n"
+		       "%16s:%6d,%6d,%6d\n"
+		       "%16s:%6d,%6d,%6d\n"
+		       "%16s:%6d,%6d,%6d\n",
+		       "", "set", "act", "latch",
+			   "sample_rate",(set_val >> 6) & 0x3, (act_val >> 6) & 0x3, (lat_val >> 6) & 0x3,
+			   "SLEEP", (set_val >> 5) & 0x1,(act_val >> 5) & 0x1, (lat_val >> 5) & 0x1,
+			   "SING", (set_val >> 4) & 0x1, (act_val >> 4) & 0x1, (lat_val >> 4) & 0x1,
+			   "ALERT_PIN", (set_val >> 3) & 0x1, (act_val >> 3) & 0x1, (lat_val >> 3) & 0x1,
+			   "ALERT_CC", (set_val >> 2) & 0x1, (act_val >> 2) & 0x1, (lat_val >> 2) & 0x1,
+			   "OVF ALERT", (set_val >> 1) & 0x1, (act_val >> 1) & 0x1, (lat_val >> 1) & 0x1,
+			   "OVF", (set_val >> 0) & 0x1, (act_val >> 0) & 0x1, (lat_val >> 0) & 0x1);
+}
+
+static int pac193x_common_reg_set(struct device *dev, const char *buf, u8 commad)
+{
+	struct pac193x_data *data = dev_get_drvdata(dev);
+	unsigned long val;
+	int status;
+	int ret = 0;
+
+	status = kstrtoul(buf, 10, &val);
+	if (status < 0)
+		return status;
+	mutex_lock(&data->config_lock);
+	ret = i2c_smbus_write_byte_data(data->client, commad, (u8)val);
+	mutex_unlock(&data->config_lock);
+	return ret;
+}
+
+static ssize_t pac193x_ctrl_store(struct device *dev,
+				  struct device_attribute *attr,
+				  const char *buf, size_t count)
+{
+	return pac193x_common_reg_set(dev, buf, PAC193X_CMD_CTRL);
+}
+
+DEVICE_ATTR(control, S_IWUSR | S_IRUGO, pac193x_ctrl_show, pac193x_ctrl_store);
+
+static ssize_t pac193x_acc_count_show(struct device *dev,
+				      struct device_attribute *attr, char *buf)
+{
+	struct pac193x_data *data = dev_get_drvdata(dev);
+	int ret;
+	u32 cache = 0;
+	u8 *pcache = (u8 *)&cache;
+	u32 acc_cnt = 0;
+	mutex_lock(&data->config_lock);
+	ret = i2c_smbus_read_i2c_block_data(data->client, PAC193X_CMD_ACC_COUNT,
+					    PAC193X_ACC_COUNT_LEN, pcache);
+	mutex_unlock(&data->config_lock);
+
+	acc_cnt = ((cache & 0xff) << 16) | (((cache >> 8) & 0xff) << 8) |
+		  ((cache >> 16) & 0xff);
+	acc_cnt = acc_cnt & 0xffffff;
+
+	ret = sysfs_emit(buf, "%u\n", acc_cnt);
+	return ret;
+}
+
+DEVICE_ATTR(acc_count, 0400, pac193x_acc_count_show, NULL);
+
+static ssize_t pac193x_dis_show(struct device *dev,
+				struct device_attribute *attr, char *buf)
+{
+	struct pac193x_data *data = dev_get_drvdata(dev);
+	u8 set_val = 0, act_val = 0, lat_val = 0;
+
+	set_val = pac193x_read_byte_data(data, PAC193X_CMD_CHANNEL_SMBUS);
+	act_val = pac193x_read_byte_data(data, PAC193X_CMD_DIS_ACT);
+	lat_val = pac193x_read_byte_data(data, PAC193X_CMD_DIS_LAT);
+
+	return sprintf(buf,
+		       "%16s:%6s,%6s,%6s\n"
+		       "%16s:%6d,%6d,%6d\n"
+		       "%16s:%6d,%6d,%6d\n"
+		       "%16s:%6d,%6d,%6d\n"
+		       "%16s:%6d,%6d,%6d\n"
+		       "%16s:%6d,%6d,%6d\n"
+		       "%16s:%6d,%6d,%6d\n"
+		       "%16s:%6d,%6d,%6d\n",
+		       "", "set", "act", "latch",
+			   "CH1_OFF", (set_val >> 7) & 0x1, (act_val >> 7) & 0x1, (lat_val >> 7) & 0x1,
+			   "CH2_OFF", (set_val >> 6) & 0x1, (act_val >> 6) & 0x1, (lat_val >> 6) & 0x1,
+			   "CH3_OFF", (set_val >> 5) & 0x1, (act_val >> 5) & 0x1, (lat_val >> 5) & 0x1,
+			   "CH4_OFF", (set_val >> 4) & 0x1, (act_val >> 4) & 0x1, (lat_val >> 4) & 0x1,
+			   "TIMEOUT", (set_val >> 3) & 0x1, (act_val >> 3) & 0x1, (lat_val >> 3) & 0x1,
+			   "BYTE COUNT", (set_val >> 2) & 0x1, (act_val >> 2) & 0x1, (lat_val >> 2) & 0x1,
+			   "NO SKIP", (set_val >> 1) & 0x1, (act_val >> 1) & 0x1, (lat_val >> 1) & 0x1);
+}
+
+static ssize_t pac193x_dis_store(struct device *dev,
+				 struct device_attribute *attr, const char *buf,
+				 size_t count)
+{
+	return pac193x_common_reg_set(dev, buf, PAC193X_CMD_CHANNEL_SMBUS);
+}
+
+DEVICE_ATTR(disable_chan_pmbus, S_IWUSR | S_IRUGO, pac193x_dis_show,
+	    pac193x_dis_store);
+
+static ssize_t pac193x_neg_pwr_show(struct device *dev,
+				    struct device_attribute *attr, char *buf)
+{
+	struct pac193x_data *data = dev_get_drvdata(dev);
+	u8 set_val = 0, act_val = 0, lat_val = 0;
+
+	set_val = pac193x_read_byte_data(data, PAC193X_CMD_NEG_PWR);
+	act_val = pac193x_read_byte_data(data, PAC193X_CMD_NEG_PWR_ACT);
+	lat_val = pac193x_read_byte_data(data, PAC193X_CMD_NEG_PWR_LAT);
+
+	return sprintf(buf,
+		       "%16s:%6s,%6s,%6s\n"
+		       "%16s:%6d,%6d,%6d\n"
+		       "%16s:%6d,%6d,%6d\n"
+		       "%16s:%6d,%6d,%6d\n"
+		       "%16s:%6d,%6d,%6d\n"
+		       "%16s:%6d,%6d,%6d\n"
+		       "%16s:%6d,%6d,%6d\n"
+		       "%16s:%6d,%6d,%6d\n"
+		       "%16s:%6d,%6d,%6d\n",
+		       "", "set", "act", "latch",
+			   "CH1_BIDI", (set_val >> 7) & 0x1, (act_val >> 7) & 0x1, (lat_val >> 7) & 0x1,
+			   "CH2_BIDI", (set_val >> 6) & 0x1, (act_val >> 6) & 0x1, (lat_val >> 6) & 0x1,
+			   "CH3_BIDI", (set_val >> 5) & 0x1, (act_val >> 5) & 0x1, (lat_val >> 5) & 0x1,
+			   "CH4_BIDI", (set_val >> 4) & 0x1, (act_val >> 4) & 0x1, (lat_val >> 5) & 0x1,
+			   "CH1_BIDV", (set_val >> 3) & 0x1, (act_val >> 3) & 0x1, (lat_val >> 3) & 0x1,
+			   "CH2_BIDV", (set_val >> 2) & 0x1, (act_val >> 2) & 0x1, (lat_val >> 2) & 0x1,
+			   "CH3_BIDV", (set_val >> 1) & 0x1, (act_val >> 1) & 0x1, (lat_val >> 1) & 0x1,
+			   "CH4_BIDV", (set_val >> 0) & 0x1, (act_val >> 0) & 0x1, (lat_val >> 0) & 0x1);
+}
+
+static ssize_t pac193x_neg_pwr_store(struct device *dev,
+				     struct device_attribute *attr,
+				     const char *buf, size_t count)
+{
+	return pac193x_common_reg_set(dev, buf, PAC193X_CMD_NEG_PWR);
+}
+
+DEVICE_ATTR(neg_pwr, S_IWUSR | S_IRUGO, pac193x_neg_pwr_show,
+	    pac193x_neg_pwr_store);
+
+static ssize_t pac193x_slow_show(struct device *dev,
+				 struct device_attribute *attr, char *buf)
+{
+	struct pac193x_data *data = dev_get_drvdata(dev);
+	u8 set_val = 0;
+
+	set_val = pac193x_read_byte_data(data, PAC193X_CMD_SLOW);
+
+	return sprintf(buf,
+		       "SLOW:%d,SLOW-LH:%d,SLOW-HL:%d, R_RISE:%d,"
+		       "R_V_RISE:%d,R_FALL:%d,R_V_FALL:%d,POR:%d\n",
+		       (set_val >> 7) & 0x1, (set_val >> 6) & 0x1,
+		       (set_val >> 5) & 0x1, (set_val >> 4) & 0x1,
+		       (set_val >> 3) & 0x1, (set_val >> 2) & 0x1,
+		       (set_val >> 1) & 0x1, (set_val >> 0) & 0x1);
+}
+
+static ssize_t pac193x_slow_store(struct device *dev,
+				  struct device_attribute *attr,
+				  const char *buf, size_t count)
+{
+	return pac193x_common_reg_set(dev, buf, PAC193X_CMD_SLOW);
+}
+
+DEVICE_ATTR(slow_ctrl, S_IWUSR | S_IRUGO, pac193x_slow_show,
+	    pac193x_slow_store);
+
+static ssize_t pac193x_version_show(struct device *dev,
+				    struct device_attribute *attr, char *buf)
+{
+	struct pac193x_data *data = dev_get_drvdata(dev);
+	int ret;
+	u8 pid = 0, mid = 0, rid = 0;
+
+	pid = pac193x_read_byte_data(data, PAC193X_CMD_PID);
+	mid = pac193x_read_byte_data(data, PAC193X_CMD_MID);
+	rid = pac193x_read_byte_data(data, PAC193X_CMD_REVERSION_ID);
+
+	ret = sysfs_emit(buf, "PID:0x%x,MID:0x%x,RID:0x%x\n", pid, mid, rid);
+	return ret;
+}
+DEVICE_ATTR(pac193x_version, 0400, pac193x_version_show, NULL);
+
+static struct attribute *pac193x_attrs[] = {
+	&dev_attr_control.attr,
+	&dev_attr_acc_count.attr,
+	&dev_attr_neg_pwr.attr,
+	&dev_attr_disable_chan_pmbus.attr,
+	&dev_attr_slow_ctrl.attr,
+	&dev_attr_pac193x_version.attr,
+	&pac1934_refreshs[0].dev_attr.attr,
+	&pac1934_refreshs[1].dev_attr.attr,
+	&pac1934_refreshs[2].dev_attr.attr,
+	NULL,
+};
+
+ATTRIBUTE_GROUPS(pac193x);
+
+static const struct hwmon_channel_info *pac1931_info[] = {
+	HWMON_CHANNEL_INFO(in, HWMON_I_INPUT | HWMON_I_AVERAGE,
+			    HWMON_I_INPUT | HWMON_I_AVERAGE),
+	HWMON_CHANNEL_INFO(curr, HWMON_C_INPUT | HWMON_C_AVERAGE),
+	HWMON_CHANNEL_INFO(power, HWMON_P_INPUT),
+	HWMON_CHANNEL_INFO(energy, HWMON_E_INPUT), NULL
+};
+static const struct hwmon_channel_info *pac1932_info[] = {
+	HWMON_CHANNEL_INFO(in, HWMON_I_INPUT | HWMON_I_AVERAGE,
+			   HWMON_I_INPUT | HWMON_I_AVERAGE,
+			   HWMON_I_INPUT | HWMON_I_AVERAGE),
+	HWMON_CHANNEL_INFO(curr, HWMON_C_INPUT | HWMON_C_AVERAGE,
+			   HWMON_C_INPUT | HWMON_C_AVERAGE),
+	HWMON_CHANNEL_INFO(power, HWMON_P_INPUT, HWMON_P_INPUT),
+	HWMON_CHANNEL_INFO(energy, HWMON_E_INPUT, HWMON_E_INPUT), NULL
+};
+static const struct hwmon_channel_info *pac1933_info[] = {
+	HWMON_CHANNEL_INFO(in, HWMON_I_INPUT | HWMON_I_AVERAGE,
+			   HWMON_I_INPUT | HWMON_I_AVERAGE,
+			   HWMON_I_INPUT | HWMON_I_AVERAGE,
+			   HWMON_I_INPUT | HWMON_I_AVERAGE),
+	HWMON_CHANNEL_INFO(curr, HWMON_C_INPUT | HWMON_C_AVERAGE,
+			   HWMON_C_INPUT | HWMON_C_AVERAGE,
+			   HWMON_C_INPUT | HWMON_C_AVERAGE),
+	HWMON_CHANNEL_INFO(power, HWMON_P_INPUT, HWMON_P_INPUT, HWMON_P_INPUT),
+	HWMON_CHANNEL_INFO(energy, HWMON_E_INPUT, HWMON_E_INPUT, HWMON_E_INPUT),
+	NULL
+};
+static const struct hwmon_channel_info *pac1934_info[] = {
+	HWMON_CHANNEL_INFO(in,
+			   HWMON_I_INPUT | HWMON_I_AVERAGE,
+			   HWMON_I_INPUT | HWMON_I_AVERAGE,
+			   HWMON_I_INPUT | HWMON_I_AVERAGE,
+			   HWMON_I_INPUT | HWMON_I_AVERAGE,
+			   HWMON_I_INPUT | HWMON_I_AVERAGE),
+	HWMON_CHANNEL_INFO(curr,
+			   HWMON_C_INPUT | HWMON_C_AVERAGE,
+			   HWMON_C_INPUT | HWMON_C_AVERAGE,
+			   HWMON_C_INPUT | HWMON_C_AVERAGE,
+			   HWMON_C_INPUT | HWMON_C_AVERAGE),
+	HWMON_CHANNEL_INFO(power, HWMON_P_INPUT, HWMON_P_INPUT, HWMON_P_INPUT,
+			   HWMON_P_INPUT),
+	HWMON_CHANNEL_INFO(energy, HWMON_E_INPUT, HWMON_E_INPUT, HWMON_E_INPUT,
+			   HWMON_E_INPUT),
+	NULL
+};
+
+static umode_t pac1934x_is_visible(const void *_data,
+				   enum hwmon_sensor_types type, u32 attr,
+				   int channel)
+{
+	switch (type) {
+	case hwmon_in:
+		switch (attr) {
+		case hwmon_in_input:
+		case hwmon_in_average:
+			if(channel == 0)
+			{
+				return 0;
+			}
+			else
+			{
+				return S_IRUGO;
+			}
+		}
+		break;
+	case hwmon_curr:
+		switch (attr) {
+		case hwmon_curr_input:
+		case hwmon_curr_average:
+			return S_IRUGO;
+		}
+		break;
+	case hwmon_power:
+		switch (attr) {
+		case hwmon_power_input:
+			return S_IRUGO;
+		}
+		break;
+	case hwmon_energy:
+		switch (attr) {
+		case hwmon_energy_input:
+			return S_IRUGO;
+		}
+		break;
+	default:
+		break;
+	}
+	return 0;
+}
+
+static int pac193x_read(struct device *dev, enum hwmon_sensor_types type,
+			u32 attr, int channel, long *val)
+{
+	switch (type) {
+	case hwmon_in:
+		switch (attr) {
+		case hwmon_in_input:
+			return pac193x_get_volt(dev, PAC193X_CMD_VBUS1, channel - 1,
+						val);
+		case hwmon_in_average:
+			return pac193x_get_volt(dev, PAC193X_CMD_VBUS1_AVG,
+						channel - 1, val);
+		}
+		break;
+	case hwmon_curr:
+		switch (attr) {
+		case hwmon_curr_input:
+			return pac193x_get_current(dev, PAC193X_CMD_VSENSE1,
+						   channel, val);
+		case hwmon_curr_average:
+			return pac193x_get_current(dev, PAC193X_CMD_VSENSE1_AVG,
+						   channel, val);
+		}
+		break;
+	case hwmon_power:
+		switch (attr) {
+		case hwmon_power_input:
+			return pac193x_get_power(dev, PAC193X_CMD_VPOWER1,
+						 channel, val);
+		}
+		break;
+	case hwmon_energy:
+		switch (attr) {
+		case hwmon_energy_input:
+			return pac193x_get_energy(dev, PAC193X_CMD_VPOWER1_ACC,
+						  channel, val);
+		}
+		break;
+	default:
+		break;
+	}
+	return 0;
+}
+
+static const struct hwmon_ops pac193x_hwmon_ops = {
+	.is_visible = pac1934x_is_visible,
+	.read = pac193x_read,
+};
+
+static struct hwmon_chip_info pac193x_chip_info = {
+	.ops = &pac193x_hwmon_ops,
+	.info = NULL,
+};
+
+static void update_reg_data(struct work_struct *work)
+{
+	static u32 updata_cnt = 0;
+	struct pac193x_data *data;
+	int act_val = 0, ctrl_val = 0, slow_val = 0;
+	int num = 0;
+	bool is_neg = false;
+
+	data = container_of(work, struct pac193x_data, update_work.work);
+	if ((data->energy_acc_count == 0)||(updata_cnt < data->energy_acc_count)) {
+		pac193x_send_refresh_cmd(data, PAC193X_CMD_REFRESH_V);
+		updata_cnt++;
+	} else {
+		pac193x_send_refresh_cmd(data, PAC193X_CMD_REFRESH);
+		updata_cnt = 0;
+	}
+
+	act_val = pac193x_read_byte_data(data, PAC193X_CMD_NEG_PWR_ACT);
+
+	for (num = 0; num < PAC193X_MAX_CHAN_CNT; num++) {
+		is_neg = false;
+		if (0x1 == ((act_val >> num) & 0x1)) {
+			/* Vsource=32*Vbus/2^15 = Vbus/2^10=Vbus/1024  */
+			data->vbus_denominator[3 - num] = 1024;
+			is_neg = true;
+		} else {
+			/* Vsource=32*Vbus/2^16 = Vbus/2^10=Vbus/1024  */
+			data->vbus_denominator[3 - num] = 2048;
+		}
+
+		if (0x1 == ((act_val >> (num + 4)) & 0x1)) {
+			/* 2^15  */
+			data->vsense_denominator[3 - num] = 32768;
+			is_neg = true;
+		} else {
+			/*2^16 */
+			data->vsense_denominator[3 - num] = 65536;
+		}
+		if (true == is_neg) {
+			/* 2^28  */
+			data->vpower_denominator[3 - num] = 134217728;
+		} else {
+			/* 2^29  */
+			data->vpower_denominator[3 - num] = 268435456;
+		}
+	}
+
+	slow_val = pac193x_read_byte_data(data, PAC193X_CMD_SLOW);
+	ctrl_val = pac193x_read_byte_data(data, PAC193X_CMD_CTRL_ACT);
+	if ((0x1 == ((slow_val >> 7) & 0x1)) &&
+	    (0x0 == ((ctrl_val >> 3) & 0x1))) {
+		data->sample_rate = 8;
+	} else {
+		switch ((ctrl_val >> 6) & 0x3) {
+		case 0:
+			data->sample_rate = 1024;
+			break;
+		case 1:
+			data->sample_rate = 256;
+			break;
+		case 2:
+			data->sample_rate = 64;
+			break;
+		case 3:
+			data->sample_rate = 8;
+			break;
+		default:
+			break;
+		}
+	}
+	queue_delayed_work(data->update_workqueue, &data->update_work,
+			   msecs_to_jiffies(data->update_time_ms));
+}
+
+static int pac193x_probe(struct i2c_client *client)
+{
+	struct device *dev = &client->dev;
+	struct pac193x_data *data;
+	struct device *hwmon_dev;
+	int ret = 0;
+	int num = 0;
+	enum PAC193X_CHAN_INDEX chan_index =
+		(enum PAC193X_CHAN_INDEX)of_device_get_match_data(&client->dev);
+
+	switch (chan_index) {
+	case pac1931_index:
+		pac193x_chip_info.info = pac1931_info;
+		break;
+	case pac1932_index:
+		pac193x_chip_info.info = pac1932_info;
+		break;
+	case pac1933_index:
+		pac193x_chip_info.info = pac1933_info;
+		break;
+	case pac1934_index:
+		pac193x_chip_info.info = pac1934_info;
+		break;
+	default:
+		break;
+	}
+
+	data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
+	if (!data)
+		return -ENOMEM;
+
+	for (num = 0; num < PAC193X_MAX_CHAN_CNT; num++) {
+		data->vbus_denominator[num] = 1;
+		data->vsense_denominator[num] = 1;
+		data->sense_resistances[num] = 1;
+	}
+
+	ret = of_property_read_u32(dev->of_node, "update_time_ms",
+				   &data->update_time_ms);
+	if (0 != ret) {
+		dev_err(dev, "can not get update_time_ms:%d\n", ret);
+		data->update_time_ms = 100;
+	}
+
+	ret = of_property_read_u32(dev->of_node, "energy_acc_count",
+				   &data->energy_acc_count);
+	if (0 != ret) {
+		dev_err(dev, "can not get energy_acc_count:%d\n", ret);
+		data->energy_acc_count = 0;
+	}
+	ret = of_property_read_u32_array(dev->of_node, "shunt_resistors",
+					 data->sense_resistances,
+					 PAC193X_MAX_CHAN_CNT);
+	if (0 != ret) {
+		dev_err(dev, "can not get sense_resistances:%d\n", ret);
+	}
+
+	dev_info(dev,
+		"update_time:%d,energy_acc_count:%d,resistances:%d,%d,%d,%dmOhm\n",
+		data->update_time_ms, data->energy_acc_count,
+		data->sense_resistances[0], data->sense_resistances[1],
+		data->sense_resistances[2], data->sense_resistances[3]);
+	mutex_init(&data->config_lock);
+	data->client = client;
+	mutex_lock(&data->config_lock);
+	i2c_smbus_write_byte_data(data->client, PAC193X_CMD_CTRL, 0x8);
+	mutex_unlock(&data->config_lock);
+	pac193x_send_refresh_cmd(data, PAC193X_CMD_REFRESH);
+
+	hwmon_dev = devm_hwmon_device_register_with_info(
+		dev, client->name, data, &pac193x_chip_info, pac193x_groups);
+	if (IS_ERR(hwmon_dev))
+		return PTR_ERR(hwmon_dev);
+
+	data->update_workqueue = create_workqueue("update_workqueue");
+
+	INIT_DELAYED_WORK(&data->update_work, update_reg_data);
+	queue_delayed_work(data->update_workqueue, &data->update_work,
+			   msecs_to_jiffies(0));
+
+	return 0;
+}
+
+static const struct of_device_id __maybe_unused pac193x_of_match[] = {
+	{ .compatible = "microchip,pac1931", .data = (void *)pac1931_index },
+	{ .compatible = "microchip,pac1932", .data = (void *)pac1932_index },
+	{ .compatible = "microchip,pac1933", .data = (void *)pac1933_index },
+	{ .compatible = "microchip,pac1934", .data = (void *)pac1934_index },
+	{},
+};
+MODULE_DEVICE_TABLE(of, pac193x_of_match);
+
+static struct i2c_driver pac193x_driver = {
+	.driver = {
+		.name	= "pac193x",
+		.of_match_table = of_match_ptr(pac193x_of_match),
+	},
+	.probe = pac193x_probe,
+};
+
+module_i2c_driver(pac193x_driver);
+
+MODULE_AUTHOR("Yang Wei <yangwei1@eswincomputing.com");
+MODULE_DESCRIPTION("pac193x driver");
+MODULE_LICENSE("GPL");
diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig
index c3f0f41a426d..32941e199ad7 100644
--- a/drivers/mmc/host/Kconfig
+++ b/drivers/mmc/host/Kconfig
@@ -288,6 +288,34 @@ config MMC_SDHCI_OF_MA35D1
 
 	  If unsure, say N.
 
+config MMC_SDHCI_OF_ESWIN
+	tristate "SDHCI OF support for the Eswin SDHCI controllers"
+	depends on MMC_SDHCI_PLTFM
+	depends on OF
+	depends on COMMON_CLK
+	select MMC_CQHCI
+	help
+	  This selects the Eswin Secure Digital Host Controller Interface
+	  (SDHCI).
+
+	  If you have a controller with this interface, say Y or M here.
+
+	  If unsure, say N.
+
+config MMC_SDHCI_OF_SDIO_ESWIN
+	tristate "SDHCI OF SDIO support for the Eswin SDHCI controllers"
+	depends on MMC_SDHCI_PLTFM
+	depends on OF
+	depends on COMMON_CLK
+	select MMC_CQHCI
+	help
+	  This selects the Eswin Secure Digital Host Controller Interface
+	  (SDHCI-SDIO).
+
+	  If you have a controller with this interface, say Y or M here.
+
+	  If unsure, say N.
+
 config MMC_SDHCI_CADENCE
 	tristate "SDHCI support for the Cadence SD/SDIO/eMMC controller"
 	depends on MMC_SDHCI_PLTFM
diff --git a/drivers/mmc/host/Makefile b/drivers/mmc/host/Makefile
index 75bafc7b162b..d69f39eb7240 100644
--- a/drivers/mmc/host/Makefile
+++ b/drivers/mmc/host/Makefile
@@ -91,6 +91,10 @@ obj-$(CONFIG_MMC_SDHCI_OF_DWCMSHC)	+= sdhci-of-dwcmshc.o
 obj-$(CONFIG_MMC_SDHCI_OF_K1)		+= sdhci-of-k1.o
 obj-$(CONFIG_MMC_SDHCI_OF_SPARX5)	+= sdhci-of-sparx5.o
 obj-$(CONFIG_MMC_SDHCI_OF_MA35D1)	+= sdhci-of-ma35d1.o
+eswin-sdhci-emmc-objs  	:= sdhci-of-eswin.o sdhci-eswin.o
+obj-$(CONFIG_MMC_SDHCI_OF_ESWIN)	+= eswin-sdhci-emmc.o
+eswin-sdhci-sdio-objs  	:= sdhci-of-eswin-sdio.o sdhci-eswin.o
+obj-$(CONFIG_MMC_SDHCI_OF_SDIO_ESWIN)	+= eswin-sdhci-sdio.o
 obj-$(CONFIG_MMC_SDHCI_BCM_KONA)	+= sdhci-bcm-kona.o
 obj-$(CONFIG_MMC_SDHCI_IPROC)		+= sdhci-iproc.o
 obj-$(CONFIG_MMC_SDHCI_NPCM)		+= sdhci-npcm.o
diff --git a/drivers/mmc/host/sdhci-eswin.c b/drivers/mmc/host/sdhci-eswin.c
new file mode 100644
index 000000000000..eb35b0a441c9
--- /dev/null
+++ b/drivers/mmc/host/sdhci-eswin.c
@@ -0,0 +1,301 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * ESWIN Emmc Driver
+ *
+ * Copyright 2024, Beijing ESWIN Computing Technology Co., Ltd.. All rights reserved.
+ * SPDX-License-Identifier: GPL-2.0
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, version 2.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <https://www.gnu.org/licenses/>.
+ *
+ * Authors: Shuang Liang <liangshuang@eswincomputing.com>
+ */
+#include <linux/delay.h>
+#include <linux/reset.h>
+#include "sdhci-eswin.h"
+
+static void eswin_mshc_coreclk_config(struct sdhci_host *host, uint16_t divisor,
+					unsigned int flag_sel)
+{
+	struct sdhci_pltfm_host *pltfm_host;
+	struct eswin_sdhci_data *eswin_sdhci;
+	u32 val = 0;
+	u32 delay = 0xfffff;
+
+	pltfm_host = sdhci_priv(host);
+	eswin_sdhci = sdhci_pltfm_priv(pltfm_host);
+
+	val = readl(eswin_sdhci->core_clk_reg);
+	val &= ~MSHC_CORE_CLK_ENABLE;
+	writel(val, eswin_sdhci->core_clk_reg);
+	while (delay--)
+		;
+	val &= ~(MSHC_CORE_CLK_FREQ_BIT_MASK << MSHC_CORE_CLK_FREQ_BIT_SHIFT);
+	val |= (divisor & MSHC_CORE_CLK_FREQ_BIT_MASK)
+	       << MSHC_CORE_CLK_FREQ_BIT_SHIFT;
+	val &= ~(MSHC_CORE_CLK_SEL_BIT);
+	val |= flag_sel;
+	writel(val, eswin_sdhci->core_clk_reg);
+
+	udelay(100);
+	val |= MSHC_CORE_CLK_ENABLE;
+	writel(val, eswin_sdhci->core_clk_reg);
+	mdelay(1);
+}
+
+static void eswin_mshc_coreclk_disable(struct sdhci_host *host)
+{
+	struct sdhci_pltfm_host *pltfm_host;
+	struct eswin_sdhci_data *eswin_sdhci;
+	u32 val = 0;
+
+	pltfm_host = sdhci_priv(host);
+	eswin_sdhci = sdhci_pltfm_priv(pltfm_host);
+
+	val = readl(eswin_sdhci->core_clk_reg);
+	val &= ~MSHC_CORE_CLK_ENABLE;
+	writel(val, eswin_sdhci->core_clk_reg);
+}
+
+void eswin_sdhci_disable_card_clk(struct sdhci_host *host)
+{
+	unsigned int clk;
+
+	/* Reset SD Clock Enable */
+	clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
+	clk &= ~SDHCI_CLOCK_CARD_EN;
+	sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
+}
+
+void eswin_sdhci_enable_card_clk(struct sdhci_host *host)
+{
+	ktime_t timeout;
+	unsigned int clk;
+
+	clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
+
+	clk |= SDHCI_CLOCK_INT_EN;
+	sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
+
+	/* Wait max 150 ms */
+	timeout = ktime_add_ms(ktime_get(), 150);
+	while (1) {
+		bool timedout = ktime_after(ktime_get(), timeout);
+		clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
+		if (clk & SDHCI_CLOCK_INT_STABLE)
+			break;
+		if (timedout) {
+			pr_err("%s: Internal clock never stabilised.\n",
+					mmc_hostname(host->mmc));
+			return;
+		}
+		udelay(10);
+	}
+
+	clk |= SDHCI_CLOCK_CARD_EN;
+	sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
+	mdelay(1);
+}
+
+void eswin_sdhci_set_core_clock(struct sdhci_host *host,
+				       unsigned int clock)
+{
+	unsigned int div, divide;
+	unsigned int flag_sel, max_clk;
+
+	if (clock == 0) {
+		eswin_mshc_coreclk_disable(host);
+		return;
+	}
+
+	if (SDHCI_CLK_208M % clock == 0) {
+		flag_sel = 1;
+		max_clk = SDHCI_CLK_208M;
+	} else {
+		flag_sel = 0;
+		max_clk = SDHCI_CLK_200M;
+	}
+
+	for (div = 1; div <= MAX_CORE_CLK_DIV; div++) {
+		if ((max_clk / div) <= clock)
+			break;
+	}
+	div--;
+
+	if (div == 0 || div == 1) {
+		divide = 2;
+	} else {
+		divide = (div + 1) * 2;
+	}
+	pr_debug("%s: clock:%d timing:%d\n", mmc_hostname(host->mmc), clock, host->timing);
+
+	eswin_sdhci_disable_card_clk(host);
+	eswin_mshc_coreclk_config(host, divide, flag_sel);
+	eswin_sdhci_enable_card_clk(host);
+	mdelay(2);
+}
+
+static void eswin_sdhci_set_clk_delays(struct sdhci_host *host)
+{
+	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
+	struct eswin_sdhci_data *eswin_sdhci = sdhci_pltfm_priv(pltfm_host);
+	struct eswin_sdhci_clk_data *clk_data = &eswin_sdhci->clk_data;
+
+	clk_set_phase(clk_data->sampleclk,
+			clk_data->clk_phase_in[host->timing]);
+	clk_set_phase(clk_data->sdcardclk,
+			clk_data->clk_phase_out[host->timing]);
+}
+
+static void eswin_sdhci_dt_read_clk_phase(struct device *dev,
+					struct eswin_sdhci_clk_data *clk_data,
+					unsigned int timing, const char *prop)
+{
+	struct device_node *np = dev->of_node;
+
+	int clk_phase[2] = { 0 };
+
+	/*
+	 * Read Tap Delay values from DT, if the DT does not contain the
+	 * Tap Values then use the pre-defined values.
+	 */
+	if (of_property_read_variable_u32_array(np, prop, &clk_phase[0], 2,
+						0)) {
+		dev_dbg(dev, "Using predefined clock phase for %s = %d %d\n",
+			prop, clk_data->clk_phase_in[timing],
+			clk_data->clk_phase_out[timing]);
+		return;
+	}
+
+	/* The values read are Input and Output Clock Delays in order */
+	clk_data->clk_phase_in[timing] = clk_phase[0];
+	clk_data->clk_phase_out[timing] = clk_phase[1];
+}
+
+/**
+ * eswin_dt_parse_clk_phases - Read Clock Delay values from DT
+ *
+ * @dev:        Pointer to our struct device.
+ * @clk_data:       Pointer to the Clock Data structure
+ *
+ * Called at initialization to parse the values of Clock Delays.
+ */
+void eswin_sdhci_dt_parse_clk_phases(struct device *dev,
+				struct eswin_sdhci_clk_data *clk_data)
+{
+	clk_data->set_clk_delays = eswin_sdhci_set_clk_delays;
+
+	eswin_sdhci_dt_read_clk_phase(dev, clk_data, MMC_TIMING_LEGACY,
+				      "clk-phase-legacy");
+	eswin_sdhci_dt_read_clk_phase(dev, clk_data, MMC_TIMING_MMC_HS,
+				      "clk-phase-mmc-hs");
+	eswin_sdhci_dt_read_clk_phase(dev, clk_data, MMC_TIMING_SD_HS,
+				      "clk-phase-sd-hs");
+	eswin_sdhci_dt_read_clk_phase(dev, clk_data, MMC_TIMING_UHS_SDR12,
+				      "clk-phase-uhs-sdr12");
+	eswin_sdhci_dt_read_clk_phase(dev, clk_data, MMC_TIMING_UHS_SDR25,
+				      "clk-phase-uhs-sdr25");
+	eswin_sdhci_dt_read_clk_phase(dev, clk_data, MMC_TIMING_UHS_SDR50,
+				      "clk-phase-uhs-sdr50");
+	eswin_sdhci_dt_read_clk_phase(dev, clk_data, MMC_TIMING_UHS_SDR104,
+				      "clk-phase-uhs-sdr104");
+	eswin_sdhci_dt_read_clk_phase(dev, clk_data, MMC_TIMING_UHS_DDR50,
+				      "clk-phase-uhs-ddr50");
+	eswin_sdhci_dt_read_clk_phase(dev, clk_data, MMC_TIMING_MMC_DDR52,
+				      "clk-phase-mmc-ddr52");
+	eswin_sdhci_dt_read_clk_phase(dev, clk_data, MMC_TIMING_MMC_HS200,
+				      "clk-phase-mmc-hs200");
+	eswin_sdhci_dt_read_clk_phase(dev, clk_data, MMC_TIMING_MMC_HS400,
+				      "clk-phase-mmc-hs400");
+}
+
+unsigned int eswin_convert_drive_impedance_ohm(struct platform_device *pdev,
+					     unsigned int dr_ohm)
+{
+	switch (dr_ohm) {
+	case 100:
+		return PHYCTRL_DR_100OHM;
+	case 66:
+		return PHYCTRL_DR_66OHM;
+	case 50:
+		return PHYCTRL_DR_50OHM;
+	case 40:
+		return PHYCTRL_DR_40OHM;
+	case 33:
+		return PHYCTRL_DR_33OHM;
+	}
+
+	dev_warn(&pdev->dev, "Invalid value %u for drive-impedance-ohm.\n",
+		 dr_ohm);
+	return PHYCTRL_DR_50OHM;
+}
+
+static void eswin_sdhci_do_reset(struct eswin_sdhci_data *eswin_sdhci)
+{
+	int ret;
+
+	ret = reset_control_assert(eswin_sdhci->txrx_rst);
+	WARN_ON(0 != ret);
+	ret = reset_control_assert(eswin_sdhci->phy_rst);
+	WARN_ON(0 != ret);
+	ret = reset_control_assert(eswin_sdhci->prstn);
+	WARN_ON(0 != ret);
+	ret = reset_control_assert(eswin_sdhci->arstn);
+	WARN_ON(0 != ret);
+
+	mdelay(2);
+
+	ret = reset_control_deassert(eswin_sdhci->txrx_rst);
+	WARN_ON(0 != ret);
+	ret = reset_control_deassert(eswin_sdhci->phy_rst);
+	WARN_ON(0 != ret);
+	ret = reset_control_deassert(eswin_sdhci->prstn);
+	WARN_ON(0 != ret);
+	ret = reset_control_deassert(eswin_sdhci->arstn);
+	WARN_ON(0 != ret);
+}
+
+int eswin_sdhci_reset_init(struct device *dev,
+				 struct eswin_sdhci_data *eswin_sdhci)
+{
+	int ret = 0;
+	eswin_sdhci->txrx_rst = devm_reset_control_get_optional(dev, "txrx_rst");
+	if (IS_ERR_OR_NULL(eswin_sdhci->txrx_rst)) {
+		dev_err_probe(dev, PTR_ERR(eswin_sdhci->txrx_rst),
+			      "txrx_rst reset not found.\n");
+		return -EFAULT;
+	}
+
+	eswin_sdhci->phy_rst = devm_reset_control_get_optional(dev, "phy_rst");
+	if (IS_ERR_OR_NULL(eswin_sdhci->phy_rst)) {
+		dev_err_probe(dev, PTR_ERR(eswin_sdhci->phy_rst),
+			      "phy_rst reset not found.\n");
+		return -EFAULT;
+	}
+
+	eswin_sdhci->prstn = devm_reset_control_get_optional(dev, "prstn");
+	if (IS_ERR_OR_NULL(eswin_sdhci->prstn)) {
+		dev_err_probe(dev, PTR_ERR(eswin_sdhci->prstn),
+			      "prstn reset not found.\n");
+		return -EFAULT;
+	}
+
+	eswin_sdhci->arstn = devm_reset_control_get_optional(dev, "arstn");
+	if (IS_ERR_OR_NULL(eswin_sdhci->arstn)) {
+		dev_err_probe(dev, PTR_ERR(eswin_sdhci->arstn),
+			      "arstn reset not found.\n");
+		return -EFAULT;
+	}
+	eswin_sdhci_do_reset(eswin_sdhci);
+
+	return ret;
+}
diff --git a/drivers/mmc/host/sdhci-eswin.h b/drivers/mmc/host/sdhci-eswin.h
new file mode 100644
index 000000000000..3bdefb0f4d1f
--- /dev/null
+++ b/drivers/mmc/host/sdhci-eswin.h
@@ -0,0 +1,232 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * ESWIN SDHCI Driver
+ *
+ * Copyright 2024, Beijing ESWIN Computing Technology Co., Ltd.. All rights reserved.
+ * SPDX-License-Identifier: GPL-2.0
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, version 2.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <https://www.gnu.org/licenses/>.
+ *
+ * Authors: Shuang Liang <liangshuang@eswincomputing.com>
+ */
+#ifndef _DRIVERS_MMC_SDHCI_ESWIN_H
+#define _DRIVERS_MMC_SDHCI_ESWIN_H
+
+#include <linux/reset.h>
+#include <linux/clk-provider.h>
+#include "sdhci-pltfm.h"
+
+#define MSHC_CARD_CLK_STABLE BIT(28)
+#define MSHC_INT_BCLK_STABLE BIT(16)
+#define MSHC_INT_ACLK_STABLE BIT(8)
+#define MSHC_INT_TMCLK_STABLE BIT(0)
+#define MSHC_INT_CLK_STABLE                             \
+	(MSHC_CARD_CLK_STABLE | MSHC_INT_ACLK_STABLE | \
+	 MSHC_INT_BCLK_STABLE | MSHC_INT_TMCLK_STABLE)
+#define MSHC_HOST_VAL_STABLE BIT(0)
+#define EMMC0_CARD_DETECT BIT(9)
+#define EMMC0_CARD_WRITE_PROT BIT(8)
+
+#define MSHC_CORE_CLK_ENABLE BIT(16)
+#define MSHC_CORE_CLK_FREQ_BIT_SHIFT 4
+#define MSHC_CORE_CLK_FREQ_BIT_MASK 0xfffu
+#define MSHC_CORE_CLK_SEL_BIT BIT(0)
+
+/* Controller does not have CD wired and will not function normally without */
+#define SDHCI_ESWIN_QUIRK_FORCE_CDTEST BIT(0)
+/* Controller immediately reports SDHCI_CLOCK_INT_STABLE after enabling the
+ * internal clock even when the clock isn't stable */
+#define SDHCI_ESWIN_QUIRK_CLOCK_UNSTABLE BIT(1)
+
+#define ESWIN_SDHCI_CTRL_HS400 0x0007 // Non-standard, for eswin,these bits are 0x7
+
+#define SDHCI_CLK_208M   208000000
+#define SDHCI_CLK_200M   200000000
+
+/* DWC_mshc_map/DWC_mshc_phy_block register */
+#define DWC_MSHC_PTR_PHY_R 0x300
+#define PHY_CNFG_R (DWC_MSHC_PTR_PHY_R + 0x00)
+#define PHY_CMDPAD_CNFG_R (DWC_MSHC_PTR_PHY_R + 0x04)
+#define PHY_DATAPAD_CNFG_R (DWC_MSHC_PTR_PHY_R + 0x06)
+#define PHY_CLKPAD_CNFG_R (DWC_MSHC_PTR_PHY_R + 0x08)
+#define PHY_STBPAD_CNFG_R (DWC_MSHC_PTR_PHY_R + 0x0a)
+#define PHY_RSTNPAD_CNFG_R (DWC_MSHC_PTR_PHY_R + 0x0c)
+#define PHY_PADTEST_CNFG_R (DWC_MSHC_PTR_PHY_R + 0x0e)
+#define PHY_PADTEST_OUT_R (DWC_MSHC_PTR_PHY_R + 0x10)
+#define PHY_PADTEST_IN_R (DWC_MSHC_PTR_PHY_R + 0x12)
+#define PHY_PRBS_CNFG_R (DWC_MSHC_PTR_PHY_R + 0x18)
+#define PHY_PHYLBK_CNFG_R (DWC_MSHC_PTR_PHY_R + 0x1a)
+#define PHY_COMMDL_CNFG_R (DWC_MSHC_PTR_PHY_R + 0x1c)
+#define PHY_SDCLKDL_CNFG_R (DWC_MSHC_PTR_PHY_R + 0x1d)
+#define PHY_SDCLKDL_DC_R (DWC_MSHC_PTR_PHY_R + 0x1e)
+#define PHY_SMPLDL_CNFG_R (DWC_MSHC_PTR_PHY_R + 0x20)
+#define PHY_ATDL_CNFG_R (DWC_MSHC_PTR_PHY_R + 0x21)
+#define PHY_DLL_CTRL_R (DWC_MSHC_PTR_PHY_R + 0x24)
+#define PHY_DLL_CNFG1_R (DWC_MSHC_PTR_PHY_R + 0x25)
+#define PHY_DLL_CNFG2_R (DWC_MSHC_PTR_PHY_R + 0x26)
+#define PHY_DLLDL_CNFG_R (DWC_MSHC_PTR_PHY_R + 0x28)
+#define PHY_DLL_OFFST_R (DWC_MSHC_PTR_PHY_R + 0x29)
+#define PHY_DLLMST_TSTDC_R (DWC_MSHC_PTR_PHY_R + 0x2a)
+#define PHY_DLLBT_CNFG_R (DWC_MSHC_PTR_PHY_R + 0x2c)
+#define PHY_DLL_STATUS_R (DWC_MSHC_PTR_PHY_R + 0x2e)
+#define PHY_DLLDBG_MLKDC_R (DWC_MSHC_PTR_PHY_R + 0x30)
+#define PHY_DLLDBG_SLKDC_R (DWC_MSHC_PTR_PHY_R + 0x32)
+
+#define ENABLE 1
+#define DISABLE 0
+/* strength definition */
+#define PHYCTRL_DR_33OHM 0xee
+#define PHYCTRL_DR_40OHM 0xcc
+#define PHYCTRL_DR_50OHM 0x88
+#define PHYCTRL_DR_66OHM 0x44
+#define PHYCTRL_DR_100OHM 0x00
+
+#define PHY_PAD_MAX_DRIVE_STRENGTH 0xf
+#define PHY_CLK_MAX_DELAY_MASK 0x7f
+#define PHY_PAD_SP_DRIVE_SHIF 16
+#define PHY_PAD_SN_DRIVE_SHIF 20
+
+#define PHY_RSTN BIT(0)
+#define PHY_UPDATE_DELAY_CODE BIT(4)
+
+#define VENDOR_EMMC_CTRL_R 0x52c
+#define EMMC_CRAD_PRESENT BIT(0)
+#define EMMC_RST_N_OE BIT(3)
+#define EMMC_RST_N  BIT(2)
+
+#define PHY_SLEW_0 0x0
+#define PHY_SLEW_1 0x1
+#define PHY_SLEW_2 0x2
+#define PHY_SLEW_3 0x3
+#define PHY_TX_SLEW_CTRL_P_BIT_SHIFT 5
+#define PHY_TX_SLEW_CTRL_N_BIT_SHIFT 9
+
+#define PHY_PULL_BIT_SHIF 0x3
+#define PHY_PULL_DISABLED 0x0
+#define PHY_PULL_UP 0x1
+#define PHY_PULL_DOWN 0x2
+#define PHY_PULL_MASK 0x3
+
+#define PHY_PAD_RXSEL_0 0x0
+#define PHY_PAD_RXSEL_1 0x1
+
+#define VENDOR_AT_CTRL_R 0x540
+#define LATENCY_LT_BIT_OFFSET 19
+#define LATENCY_LT_MASK 0x3
+
+#define LATENCY_LT_1 0x0
+#define LATENCY_LT_2 0x1
+#define LATENCY_LT_3 0x2
+#define LATENCY_LT_4 0x3
+#define SW_TUNE_ENABLE BIT(4)
+
+#define VENDOR_AT_SATA_R 0x544
+#define MAX_PHASE_CODE 0xff
+
+#define DLL_ENABEL BIT(0)
+#define DLL_LOCK_STS BIT(0)
+#define DLL_ERROR_STS BIT(1)
+#define PHY_DELAY_CODE_MASK 0x7f
+#define PHY_DELAY_CODE_MAX 0x7f
+
+#define MAX_CORE_CLK_DIV 0xfff
+
+/**
+ * struct eswin_sdhci_clk_ops - Clock Operations for eswin SD controller
+ *
+ * @sdcardclk_ops:  The output clock related operations
+ * @sampleclk_ops:  The sample clock related operations
+ */
+struct eswin_sdhci_clk_ops {
+	const struct clk_ops *sdcardclk_ops;
+	const struct clk_ops *sampleclk_ops;
+};
+
+/**
+ * struct eswin_sdhci_clk_data - ESWIN Controller Clock Data.
+ *
+ * @sdcardclk_hw:   Struct for the clock we might provide to a PHY.
+ * @sdcardclk:      Pointer to normal 'struct clock' for sdcardclk_hw.
+ * @sampleclk_hw:   Struct for the clock we might provide to a PHY.
+ * @sampleclk:      Pointer to normal 'struct clock' for sampleclk_hw.
+ * @clk_phase_in:   Array of Input Clock Phase Delays for all speed modes
+ * @clk_phase_out:  Array of Output Clock Phase Delays for all speed modes
+ * @set_clk_delays: Function pointer for setting Clock Delays
+ * @clk_of_data:    Platform specific runtime clock data storage pointer
+ */
+struct eswin_sdhci_clk_data {
+	struct clk_hw sdcardclk_hw;
+	struct clk *sdcardclk;
+	struct clk_hw sampleclk_hw;
+	struct clk *sampleclk;
+	int clk_phase_in[MMC_TIMING_MMC_HS400 + 1];
+	int clk_phase_out[MMC_TIMING_MMC_HS400 + 1];
+	void (*set_clk_delays)(struct sdhci_host *host);
+	void *clk_of_data;
+};
+
+struct eswin_sdhci_phy_data {
+	unsigned int drive_impedance;
+	unsigned int enable_strobe_pulldown;
+	unsigned int enable_data_pullup;
+	unsigned int enable_cmd_pullup;
+	unsigned int delay_code;
+};
+
+/**
+ * struct eswin_sdhci_data - ESWIN Controller Data
+ *
+ * @host:       Pointer to the main SDHCI host structure.
+ * @clk_ahb:        Pointer to the AHB clock
+ * @has_cqe:        True if controller has command queuing engine.
+ * @clk_data:       Struct for the ESWIN Controller Clock Data.
+ * @clk_ops:        Struct for the ESWIN Controller Clock Operations.
+ * @soc_ctl_base:   Pointer to regmap for syscon for soc_ctl registers.
+ * @soc_ctl_map:    Map to get offsets into soc_ctl registers.
+ * @quirks:     ESWIN deviations from spec.
+ * @phy:        ESWIN sdhci phy configs.
+ * @private:    private for spec driver.
+ */
+struct eswin_sdhci_data {
+	struct sdhci_host *host;
+	struct clk *clk_ahb;
+	bool has_cqe;
+	struct eswin_sdhci_clk_data clk_data;
+	const struct eswin_sdhci_clk_ops *clk_ops;
+	unsigned int quirks;
+	void __iomem *core_clk_reg;
+	struct reset_control *txrx_rst;
+	struct reset_control *phy_rst;
+	struct reset_control *prstn;
+	struct reset_control *arstn;
+	struct eswin_sdhci_phy_data phy;
+	unsigned long private[] ____cacheline_aligned;
+};
+
+struct eswin_sdhci_of_data {
+	const struct sdhci_pltfm_data *pdata;
+	const struct eswin_sdhci_clk_ops *clk_ops;
+};
+
+void eswin_sdhci_set_core_clock(struct sdhci_host *host,
+		unsigned int clock);
+void eswin_sdhci_disable_card_clk(struct sdhci_host *host);
+void eswin_sdhci_enable_card_clk(struct sdhci_host *host);
+void eswin_sdhci_dt_parse_clk_phases(struct device *dev,
+		struct eswin_sdhci_clk_data *clk_data);
+unsigned int eswin_convert_drive_impedance_ohm(struct platform_device *pdev,
+		unsigned int dr_ohm);
+int eswin_sdhci_reset_init(struct device *dev,
+		struct eswin_sdhci_data *eswin_sdhci);
+
+#endif /* _DRIVERS_MMC_SDHCI_ESWIN_H */
diff --git a/drivers/mmc/host/sdhci-of-eswin-sdio.c b/drivers/mmc/host/sdhci-of-eswin-sdio.c
new file mode 100644
index 000000000000..d7af7b4a6511
--- /dev/null
+++ b/drivers/mmc/host/sdhci-of-eswin-sdio.c
@@ -0,0 +1,1017 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * ESWIN sdio Driver
+ *
+ * Copyright 2024, Beijing ESWIN Computing Technology Co., Ltd.. All rights reserved.
+ * SPDX-License-Identifier: GPL-2.0
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, version 2.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <https://www.gnu.org/licenses/>.
+ *
+ * Authors: Shuang Liang <liangshuang@eswincomputing.com>
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/mfd/syscon.h>
+#include <linux/module.h>
+#include <linux/of_device.h>
+#include <linux/phy/phy.h>
+#include <linux/regmap.h>
+#include <linux/of.h>
+#include <linux/reset.h>
+#include "cqhci.h"
+#include "sdhci-pltfm.h"
+#include <linux/bitfield.h>
+#include "sdhci-eswin.h"
+
+
+#define ESWIN_SDHCI_SD_CQE_BASE_ADDR 0x180
+#define ESWIN_SDHCI_SD0_INT_STATUS 0x608
+#define ESWIN_SDHCI_SD0_PWR_CTRL 0x60c
+#define ESWIN_SDHCI_SD1_INT_STATUS 0x708
+#define ESWIN_SDHCI_SD1_PWR_CTRL 0x70c
+
+#define DELAY_RANGE_THRESHOLD   20
+
+struct eswin_sdio_private {
+	int phase_code;
+	unsigned int enable_sw_tuning;
+};
+
+static inline void *sdhci_sdio_priv(struct eswin_sdhci_data *sdio)
+{
+	return sdio->private;
+}
+
+static void eswin_sdhci_sdio_set_clock(struct sdhci_host *host,
+				       unsigned int clock)
+{
+	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
+	struct eswin_sdhci_data *eswin_sdhci_sdio =
+		sdhci_pltfm_priv(pltfm_host);
+	struct eswin_sdhci_clk_data *clk_data =
+		&eswin_sdhci_sdio->clk_data;
+
+	/* Set the Input and Output Clock Phase Delays */
+	if (clk_data->set_clk_delays) {
+		clk_data->set_clk_delays(host);
+	}
+
+	eswin_sdhci_set_core_clock(host, clock);
+	sdhci_set_clock(host, clock);
+
+	if (eswin_sdhci_sdio->quirks & SDHCI_ESWIN_QUIRK_CLOCK_UNSTABLE)
+		/*
+                 * Some controllers immediately report SDHCI_CLOCK_INT_STABLE
+                 * after enabling the clock even though the clock is not
+                 * stable. Trying to use a clock without waiting here results
+                 * in EILSEQ while detecting some older/slower cards. The
+                 * chosen delay is the maximum delay from sdhci_set_clock.
+                 */
+		msleep(20);
+}
+
+static void eswin_sdhci_sdio_config_phy_delay(struct sdhci_host *host,
+					      int delay)
+{
+	delay &= PHY_CLK_MAX_DELAY_MASK;
+
+	/*phy clk delay line config*/
+	sdhci_writeb(host, PHY_UPDATE_DELAY_CODE, PHY_SDCLKDL_CNFG_R);
+	sdhci_writeb(host, delay, PHY_SDCLKDL_DC_R);
+	sdhci_writeb(host, 0x0, PHY_SDCLKDL_CNFG_R);
+}
+
+static void eswin_sdhci_sdio_config_phy(struct sdhci_host *host)
+{
+	unsigned int val = 0;
+	unsigned int drv = 0;
+	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
+	struct eswin_sdhci_data *eswin_sdhci =
+		sdhci_pltfm_priv(pltfm_host);
+	struct eswin_sdhci_phy_data *phy = &eswin_sdhci->phy;
+
+	drv = phy->drive_impedance << PHY_PAD_SP_DRIVE_SHIF;
+	pr_debug("%s: phy drv=0x%x \n",mmc_hostname(host->mmc), drv);
+
+	eswin_sdhci_disable_card_clk(host);
+
+	/* reset phy,config phy's pad */
+	sdhci_writel(host, drv | (~PHY_RSTN), PHY_CNFG_R);
+	/*CMDPAD_CNFS*/
+	val = (PHY_SLEW_2 << PHY_TX_SLEW_CTRL_P_BIT_SHIFT) |
+	      (PHY_SLEW_2 << PHY_TX_SLEW_CTRL_N_BIT_SHIFT) |
+	      (phy->enable_cmd_pullup << PHY_PULL_BIT_SHIF) | PHY_PAD_RXSEL_1;
+	sdhci_writew(host, val, PHY_CMDPAD_CNFG_R);
+	pr_debug("%s: phy cmd=0x%x\n",mmc_hostname(host->mmc), val);
+
+	/*DATA PAD CNFG*/
+	val = (PHY_SLEW_2 << PHY_TX_SLEW_CTRL_P_BIT_SHIFT) |
+	      (PHY_SLEW_2 << PHY_TX_SLEW_CTRL_N_BIT_SHIFT) |
+	      (phy->enable_data_pullup << PHY_PULL_BIT_SHIF) | PHY_PAD_RXSEL_1;
+	sdhci_writew(host, val, PHY_DATAPAD_CNFG_R);
+	pr_debug("%s: phy data=0x%x\n",mmc_hostname(host->mmc), val);
+
+	/*Clock PAD Setting*/
+	val = (PHY_SLEW_2 << PHY_TX_SLEW_CTRL_P_BIT_SHIFT) |
+	      (PHY_SLEW_2 << PHY_TX_SLEW_CTRL_N_BIT_SHIFT) | PHY_PAD_RXSEL_0;
+	sdhci_writew(host, val, PHY_CLKPAD_CNFG_R);
+	pr_debug("%s: phy clk=0x%x\n",mmc_hostname(host->mmc), val);
+	mdelay(2);
+
+	/*PHY RSTN PAD setting*/
+	val = (PHY_SLEW_2 << PHY_TX_SLEW_CTRL_P_BIT_SHIFT) |
+	      (PHY_SLEW_2 << PHY_TX_SLEW_CTRL_N_BIT_SHIFT) |
+	      (PHY_PULL_UP << PHY_PULL_BIT_SHIF) | PHY_PAD_RXSEL_1;
+	sdhci_writew(host, val, PHY_RSTNPAD_CNFG_R);
+
+	sdhci_writel(host, drv | PHY_RSTN, PHY_CNFG_R);
+
+	eswin_sdhci_sdio_config_phy_delay(host, phy->delay_code);
+
+	eswin_sdhci_enable_card_clk(host);
+}
+
+static void eswin_sdhci_sdio_reset(struct sdhci_host *host, u8 mask)
+{
+	u8 ctrl;
+	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
+	struct eswin_sdhci_data *eswin_sdhci_sdio =
+		sdhci_pltfm_priv(pltfm_host);
+
+	/* Disable signal and interrupts before resetting the phy.
+	 * Doing this avoids ISR to serve any undesired interrupts during
+	 * reset and avoid producing the fake register dump during probe.
+	 */
+	sdhci_writel(host, 0, SDHCI_INT_ENABLE);
+	sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
+	sdhci_reset(host, mask);
+	sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
+	sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
+
+	if (eswin_sdhci_sdio->quirks & SDHCI_ESWIN_QUIRK_FORCE_CDTEST) {
+		ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
+		ctrl |= SDHCI_CTRL_CDTEST_INS | SDHCI_CTRL_CDTEST_EN;
+		sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
+	}
+	if (mask == SDHCI_RESET_ALL) {	// after reset all,the phy`s config will be clear.
+		eswin_sdhci_sdio_config_phy(host);
+	}
+}
+
+static int eswin_sdhci_sdio_delay_tuning(struct sdhci_host *host, u32 opcode)
+{
+	int ret;
+	int delay = -1;
+	int i = 0;
+	int delay_min = -1;
+	int delay_max = -1;
+	int delay_range = -1;
+
+	int cmd_error = 0;
+	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
+	struct eswin_sdhci_data *eswin_sdhci =
+		sdhci_pltfm_priv(pltfm_host);
+
+	for (i = 0; i <= PHY_DELAY_CODE_MAX; i++) {
+		eswin_sdhci_disable_card_clk(host);
+		eswin_sdhci_sdio_config_phy_delay(host, i);
+		eswin_sdhci_enable_card_clk(host);
+		ret = mmc_send_tuning(host->mmc, opcode, &cmd_error);
+		if (ret) {
+			host->ops->reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
+			udelay(200);
+			if (delay_min != -1 && delay_max != -1) {
+				if (delay_max - delay_min > delay_range) {
+					delay_range = delay_max - delay_min;
+					delay = (delay_min + delay_max) / 2;
+					if (delay_range > DELAY_RANGE_THRESHOLD)
+						break;
+				}
+				delay_min = -1;
+				delay_max = -1;
+			}
+		} else {
+			if (delay_min == -1) {
+				delay_min = i;
+				continue;
+			} else {
+				delay_max = i;
+				continue;
+			}
+		}
+	}
+	if (delay == -1) {
+		pr_err("%s: delay code tuning failed!\n",
+		       mmc_hostname(host->mmc));
+		eswin_sdhci_disable_card_clk(host);
+		eswin_sdhci_sdio_config_phy_delay(host,
+						  eswin_sdhci->phy.delay_code);
+		eswin_sdhci_enable_card_clk(host);
+
+		return ret;
+	}
+
+	pr_info("%s: set delay:0x%x\n", mmc_hostname(host->mmc), delay);
+	eswin_sdhci_disable_card_clk(host);
+	eswin_sdhci_sdio_config_phy_delay(host, delay);
+	eswin_sdhci_enable_card_clk(host);
+
+	return 0;
+}
+
+static int eswin_sdhci_sdio_phase_code_tuning(struct sdhci_host *host,
+					      u32 opcode)
+{
+	int cmd_error = 0;
+	int ret = 0;
+	int phase_code = 0;
+	int code_min = -1;
+	int code_max = -1;
+
+	for (phase_code = 0; phase_code <= MAX_PHASE_CODE; phase_code++) {
+		eswin_sdhci_disable_card_clk(host);
+		sdhci_writew(host, phase_code, VENDOR_AT_SATA_R);
+		eswin_sdhci_enable_card_clk(host);
+
+		ret = mmc_send_tuning(host->mmc, opcode, &cmd_error);
+		if (ret) {
+			host->ops->reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
+			udelay(200);
+			if (code_min != -1 && code_max != -1)
+				break;
+		} else {
+			if (code_min == -1) {
+				code_min = phase_code;
+				continue;
+			} else {
+				code_max = phase_code;
+				continue;
+			}
+		}
+	}
+	if (code_min == -1 && code_max == -1) {
+		pr_err("%s: phase code tuning failed!\n",
+		       mmc_hostname(host->mmc));
+		eswin_sdhci_disable_card_clk(host);
+		sdhci_writew(host, 0, VENDOR_AT_SATA_R);
+		eswin_sdhci_enable_card_clk(host);
+		return -EIO;
+	}
+
+	phase_code = (code_min + code_max) / 2;
+	pr_info("%s: set phase_code:0x%x\n", mmc_hostname(host->mmc), phase_code);
+
+	eswin_sdhci_disable_card_clk(host);
+	sdhci_writew(host, phase_code, VENDOR_AT_SATA_R);
+	eswin_sdhci_enable_card_clk(host);
+
+	return 0;
+}
+
+static int eswin_sdhci_sdio_executing_tuning(struct sdhci_host *host,
+					     u32 opcode)
+{
+	u32 ctrl;
+	u32 val;
+	int ret = 0;
+	struct sdhci_pltfm_host *pltfm_host;
+	struct eswin_sdhci_data *eswin_sdhci_sdio;
+	struct eswin_sdio_private *eswin_sdio_priv;
+
+	pltfm_host = sdhci_priv(host);
+	eswin_sdhci_sdio = sdhci_pltfm_priv(pltfm_host);
+	eswin_sdio_priv = sdhci_sdio_priv(eswin_sdhci_sdio);
+
+	if (!eswin_sdio_priv->enable_sw_tuning) {
+		if (eswin_sdio_priv->phase_code != -1) {
+			eswin_sdhci_disable_card_clk(host);
+			sdhci_writew(host, eswin_sdio_priv->phase_code, VENDOR_AT_SATA_R);
+			eswin_sdhci_enable_card_clk(host);
+		}
+		return 0;
+	}
+
+	eswin_sdhci_disable_card_clk(host);
+
+	ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
+	ctrl &= ~SDHCI_CTRL_TUNED_CLK;
+	sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
+
+	val = sdhci_readl(host, VENDOR_AT_CTRL_R);
+	val |= SW_TUNE_ENABLE;
+	sdhci_writew(host, val, VENDOR_AT_CTRL_R);
+	sdhci_writew(host, 0, VENDOR_AT_SATA_R);
+
+	eswin_sdhci_enable_card_clk(host);
+
+	sdhci_writew(host, 0x0, SDHCI_CMD_DATA);
+
+	ret = eswin_sdhci_sdio_delay_tuning(host, opcode);
+	if (ret < 0) {
+		return ret;
+	}
+
+	ret = eswin_sdhci_sdio_phase_code_tuning(host, opcode);
+	if (ret < 0) {
+		return ret;
+	}
+
+	return 0;
+}
+
+static u32 eswin_sdhci_sdio_cqhci_irq(struct sdhci_host *host, u32 intmask)
+{
+	int cmd_error = 0;
+	int data_error = 0;
+
+	if (!sdhci_cqe_irq(host, intmask, &cmd_error, &data_error))
+		return intmask;
+
+	cqhci_irq(host->mmc, intmask, cmd_error, data_error);
+
+	return 0;
+}
+
+static void eswin_sdhci_sdio_dumpregs(struct mmc_host *mmc)
+{
+	sdhci_dumpregs(mmc_priv(mmc));
+}
+
+static void eswin_sdhci_sdio_cqe_enable(struct mmc_host *mmc)
+{
+	struct sdhci_host *host = mmc_priv(mmc);
+	u32 reg;
+
+	reg = sdhci_readl(host, SDHCI_PRESENT_STATE);
+	while (reg & SDHCI_DATA_AVAILABLE) {
+		sdhci_readl(host, SDHCI_BUFFER);
+		reg = sdhci_readl(host, SDHCI_PRESENT_STATE);
+	}
+
+	sdhci_cqe_enable(mmc);
+}
+
+static const struct cqhci_host_ops eswin_sdhci_sdio_cqhci_ops = {
+	.enable = eswin_sdhci_sdio_cqe_enable,
+	.disable = sdhci_cqe_disable,
+	.dumpregs = eswin_sdhci_sdio_dumpregs,
+};
+
+static const struct sdhci_ops eswin_sdhci_sdio_cqe_ops = {
+	.set_clock = eswin_sdhci_sdio_set_clock,
+	.get_max_clock = sdhci_pltfm_clk_get_max_clock,
+	.get_timeout_clock = sdhci_pltfm_clk_get_max_clock,
+	.set_bus_width = sdhci_set_bus_width,
+	.reset = eswin_sdhci_sdio_reset,
+	.set_uhs_signaling = sdhci_set_uhs_signaling,
+	.set_power = sdhci_set_power_and_bus_voltage,
+	.irq = eswin_sdhci_sdio_cqhci_irq,
+	.platform_execute_tuning = eswin_sdhci_sdio_executing_tuning,
+
+};
+
+static const struct sdhci_pltfm_data eswin_sdhci_sdio_cqe_pdata = {
+	.ops = &eswin_sdhci_sdio_cqe_ops,
+	.quirks = SDHCI_QUIRK_BROKEN_CQE | SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
+	.quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
+		   SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN,
+};
+
+#ifdef CONFIG_PM_SLEEP
+/**
+ * eswin_sdhci_sdio_suspend- Suspend method for the driver
+ * @dev:        Address of the device structure
+ *
+ * Put the device in a low power state.
+ *
+ * Return: 0 on success and error value on error
+ */
+static int eswin_sdhci_sdio_suspend(struct device *dev)
+{
+	struct sdhci_host *host = dev_get_drvdata(dev);
+	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
+	struct eswin_sdhci_data *eswin_sdhci_sdio =
+		sdhci_pltfm_priv(pltfm_host);
+	int ret;
+
+	if (host->tuning_mode != SDHCI_TUNING_MODE_3)
+		mmc_retune_needed(host->mmc);
+
+	if (eswin_sdhci_sdio->has_cqe) {
+		ret = cqhci_suspend(host->mmc);
+		if (ret)
+			return ret;
+	}
+
+	ret = sdhci_suspend_host(host);
+	if (ret)
+		return ret;
+
+	clk_disable(pltfm_host->clk);
+	clk_disable(eswin_sdhci_sdio->clk_ahb);
+
+	return 0;
+}
+
+/**
+ * eswin_sdhci_sdio_resume- Resume method for the driver
+ * @dev:        Address of the device structure
+ *
+ * Resume operation after suspend
+ *
+ * Return: 0 on success and error value on error
+ */
+static int eswin_sdhci_sdio_resume(struct device *dev)
+{
+	struct sdhci_host *host = dev_get_drvdata(dev);
+	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
+	struct eswin_sdhci_data *eswin_sdhci_sdio =
+		sdhci_pltfm_priv(pltfm_host);
+	int ret;
+
+	ret = clk_enable(eswin_sdhci_sdio->clk_ahb);
+	if (ret) {
+		dev_err(dev, "Cannot enable AHB clock.\n");
+		return ret;
+	}
+
+	ret = clk_enable(pltfm_host->clk);
+	if (ret) {
+		dev_err(dev, "Cannot enable SD clock.\n");
+		return ret;
+	}
+
+	ret = sdhci_resume_host(host);
+	if (ret) {
+		dev_err(dev, "Cannot resume host.\n");
+		return ret;
+	}
+
+	if (eswin_sdhci_sdio->has_cqe)
+		return cqhci_resume(host->mmc);
+
+	return 0;
+}
+#endif /* ! CONFIG_PM_SLEEP */
+
+static SIMPLE_DEV_PM_OPS(eswin_sdhci_sdio_dev_pm_ops, eswin_sdhci_sdio_suspend,
+			 eswin_sdhci_sdio_resume);
+
+/**
+ * eswin_sdhci_sdio_sdcardclk_recalc_rate- Return the card clock rate
+ *
+ * @hw:                 Pointer to the hardware clock structure.
+ * @parent_rate:                The parent rate (should be rate of clk_xin).
+ *
+ * Return the current actual rate of the SD card clock.  This can be used
+ * to communicate with out PHY.
+ *
+ * Return: The card clock rate.
+ */
+static unsigned long
+eswin_sdhci_sdio_sdcardclk_recalc_rate(struct clk_hw *hw,
+				       unsigned long parent_rate)
+{
+	struct eswin_sdhci_clk_data *clk_data = container_of(
+		hw, struct eswin_sdhci_clk_data, sdcardclk_hw);
+	struct eswin_sdhci_data *eswin_sdhci_sdio =
+		container_of(clk_data, struct eswin_sdhci_data, clk_data);
+	struct sdhci_host *host = eswin_sdhci_sdio->host;
+
+	return host->mmc->actual_clock;
+}
+
+static const struct clk_ops eswin_sdio_sdcardclk_ops = {
+	.recalc_rate = eswin_sdhci_sdio_sdcardclk_recalc_rate,
+};
+
+/**
+ * eswin_sdhci_sdio_sampleclk_recalc_rate- Return the sampling clock rate
+ *
+ * @hw:                 Pointer to the hardware clock structure.
+ * @parent_rate:                The parent rate (should be rate of clk_xin).
+ *
+ * Return the current actual rate of the sampling clock.  This can be used
+ * to communicate with out PHY.
+ *
+ * Return: The sample clock rate.
+ */
+static unsigned long
+eswin_sdhci_sdio_sampleclk_recalc_rate(struct clk_hw *hw,
+				       unsigned long parent_rate)
+{
+	struct eswin_sdhci_clk_data *clk_data = container_of(
+		hw, struct eswin_sdhci_clk_data, sampleclk_hw);
+	struct eswin_sdhci_data *eswin_sdhci_sdio =
+		container_of(clk_data, struct eswin_sdhci_data, clk_data);
+	struct sdhci_host *host = eswin_sdhci_sdio->host;
+
+	return host->mmc->actual_clock;
+}
+
+static const struct clk_ops eswin_sdio_sampleclk_ops = {
+	.recalc_rate = eswin_sdhci_sdio_sampleclk_recalc_rate,
+};
+
+static const struct eswin_sdhci_clk_ops eswin_sdio_clk_ops = {
+	.sdcardclk_ops = &eswin_sdio_sdcardclk_ops,
+	.sampleclk_ops = &eswin_sdio_sampleclk_ops,
+};
+
+static struct eswin_sdhci_of_data eswin_sdhci_fu800_sdio_data = {
+	.pdata = &eswin_sdhci_sdio_cqe_pdata,
+	.clk_ops = &eswin_sdio_clk_ops,
+};
+
+static const struct of_device_id eswin_sdhci_sdio_of_match[] = {
+	/* SoC-specific compatible strings*/
+	{
+		.compatible = "eswin,sdhci-sdio",
+		.data = &eswin_sdhci_fu800_sdio_data,
+	},
+	{ /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, eswin_sdhci_sdio_of_match);
+
+/**
+ * eswin_sdhci_sdio_register_sdcardclk- Register the sdcardclk for a PHY to use
+ *
+ * @sdhci_arasan:       Our private data structure.
+ * @clk_xin:            Pointer to the functional clock
+ * @dev:                Pointer to our struct device.
+ *
+ * Some PHY devices need to know what the actual card clock is.  In order for
+ * them to find out, we'll provide a clock through the common clock framework
+ * for them to query.
+ *
+ * Return: 0 on success and error value on error
+ */
+static int eswin_sdhci_sdio_register_sdcardclk(
+	struct eswin_sdhci_data *eswin_sdhci_sdio, struct clk *clk_xin,
+	struct device *dev)
+{
+	struct eswin_sdhci_clk_data *clk_data =
+		&eswin_sdhci_sdio->clk_data;
+	struct device_node *np = dev->of_node;
+	struct clk_init_data sdcardclk_init;
+	const char *parent_clk_name;
+	int ret;
+
+	ret = of_property_read_string_index(np, "clock-output-names", 0,
+					    &sdcardclk_init.name);
+	if (ret) {
+		dev_err(dev, "DT has #clock-cells but no clock-output-names\n");
+		return ret;
+	}
+
+	parent_clk_name = __clk_get_name(clk_xin);
+	sdcardclk_init.parent_names = &parent_clk_name;
+	sdcardclk_init.num_parents = 1;
+	sdcardclk_init.flags = CLK_GET_RATE_NOCACHE;
+	sdcardclk_init.ops = eswin_sdhci_sdio->clk_ops->sdcardclk_ops;
+
+	clk_data->sdcardclk_hw.init = &sdcardclk_init;
+	clk_data->sdcardclk = devm_clk_register(dev, &clk_data->sdcardclk_hw);
+	if (IS_ERR(clk_data->sdcardclk))
+		return PTR_ERR(clk_data->sdcardclk);
+	clk_data->sdcardclk_hw.init = NULL;
+
+	ret = of_clk_add_provider(np, of_clk_src_simple_get,
+				  clk_data->sdcardclk);
+	if (ret)
+		dev_err(dev, "Failed to add sdcard clock provider\n");
+
+	return ret;
+}
+
+/**
+ * eswin_sdhci_sdio_register_sampleclk - Register the sampleclk for a PHY to use
+ *
+ * @sdhci_arasan:       Our private data structure.
+ * @clk_xin:            Pointer to the functional clock
+ * @dev:                Pointer to our struct device.
+ *
+ * Some PHY devices need to know what the actual card clock is.  In order for
+ * them to find out, we'll provide a clock through the common clock framework
+ * for them to query.
+ *
+ * Return: 0 on success and error value on error
+ */
+static int eswin_sdhci_sdio_register_sampleclk(
+	struct eswin_sdhci_data *eswin_sdhci_sdio, struct clk *clk_xin,
+	struct device *dev)
+{
+	struct eswin_sdhci_clk_data *clk_data =
+		&eswin_sdhci_sdio->clk_data;
+	struct device_node *np = dev->of_node;
+	struct clk_init_data sampleclk_init;
+	const char *parent_clk_name;
+	int ret;
+
+	ret = of_property_read_string_index(np, "clock-output-names", 1,
+					    &sampleclk_init.name);
+	if (ret) {
+		dev_err(dev, "DT has #clock-cells but no clock-output-names\n");
+		return ret;
+	}
+
+	parent_clk_name = __clk_get_name(clk_xin);
+	sampleclk_init.parent_names = &parent_clk_name;
+	sampleclk_init.num_parents = 1;
+	sampleclk_init.flags = CLK_GET_RATE_NOCACHE;
+	sampleclk_init.ops = eswin_sdhci_sdio->clk_ops->sampleclk_ops;
+
+	clk_data->sampleclk_hw.init = &sampleclk_init;
+	clk_data->sampleclk = devm_clk_register(dev, &clk_data->sampleclk_hw);
+	if (IS_ERR(clk_data->sampleclk))
+		return PTR_ERR(clk_data->sampleclk);
+	clk_data->sampleclk_hw.init = NULL;
+
+	ret = of_clk_add_provider(np, of_clk_src_simple_get,
+				  clk_data->sampleclk);
+	if (ret)
+		dev_err(dev, "Failed to add sample clock provider\n");
+
+	return ret;
+}
+
+/**
+ * eswin_sdhci_sdio_unregister_sdclk- Undoes sdhci_arasan_register_sdclk()
+ *
+ * @dev:                Pointer to our struct device.
+ *
+ * Should be called any time we're exiting and sdhci_arasan_register_sdclk()
+ * returned success.
+ */
+static void eswin_sdhci_sdio_unregister_sdclk(struct device *dev)
+{
+	struct device_node *np = dev->of_node;
+
+	if (!of_find_property(np, "#clock-cells", NULL))
+		return;
+
+	of_clk_del_provider(dev->of_node);
+}
+
+/**
+ * eswin_sdhci_sdio_register_sdclk- Register the sdcardclk for a PHY to use
+ *
+ * @eswin_sdhci_sdio:   Our private data structure.
+ * @clk_xin:            Pointer to the functional clock
+ * @dev:                Pointer to our struct device.
+ *
+ * Some PHY devices need to know what the actual card clock is.  In order for
+ * them to find out, we'll provide a clock through the common clock framework
+ * for them to query.
+ *
+ * Note: without seriously re-architecting SDHCI's clock code and testing on
+ * all platforms, there's no way to create a totally beautiful clock here
+ * with all clock ops implemented.      Instead, we'll just create a clock that can
+ * be queried and set the CLK_GET_RATE_NOCACHE attribute to tell common clock
+ * framework that we're doing things behind its back.  This should be sufficient
+ * to create nice clean device tree bindings and later (if needed) we can try
+ * re-architecting SDHCI if we see some benefit to it.
+ *
+ * Return: 0 on success and error value on error
+ */
+static int
+eswin_sdhci_sdio_register_sdclk(struct eswin_sdhci_data *eswin_sdhci_sdio,
+				struct clk *clk_xin, struct device *dev)
+{
+	struct device_node *np = dev->of_node;
+	u32 num_clks = 0;
+	int ret;
+
+	/* Providing a clock to the PHY is optional; no error if missing */
+	if (of_property_read_u32(np, "#clock-cells", &num_clks) < 0)
+		return 0;
+
+	ret = eswin_sdhci_sdio_register_sdcardclk(eswin_sdhci_sdio, clk_xin,
+						  dev);
+	if (ret)
+		return ret;
+
+	if (num_clks) {
+		ret = eswin_sdhci_sdio_register_sampleclk(eswin_sdhci_sdio,
+							  clk_xin, dev);
+		if (ret) {
+			eswin_sdhci_sdio_unregister_sdclk(dev);
+			return ret;
+		}
+	}
+
+	return 0;
+}
+
+static int
+eswin_sdhci_sdio_add_host(struct eswin_sdhci_data *eswin_sdhci_sdio)
+{
+	struct sdhci_host *host = eswin_sdhci_sdio->host;
+	struct cqhci_host *cq_host;
+	bool dma64;
+	int ret;
+
+	if (!eswin_sdhci_sdio->has_cqe)
+		return sdhci_add_host(host);
+
+	ret = sdhci_setup_host(host);
+	if (ret)
+		return ret;
+
+	cq_host = devm_kzalloc(host->mmc->parent, sizeof(*cq_host), GFP_KERNEL);
+	if (!cq_host) {
+		ret = -ENOMEM;
+		goto cleanup;
+	}
+
+	cq_host->mmio = host->ioaddr + ESWIN_SDHCI_SD_CQE_BASE_ADDR;
+	cq_host->ops = &eswin_sdhci_sdio_cqhci_ops;
+
+	dma64 = host->flags & SDHCI_USE_64_BIT_DMA;
+	if (dma64)
+		cq_host->caps |= CQHCI_TASK_DESC_SZ_128;
+
+	ret = cqhci_init(cq_host, host->mmc, dma64);
+	if (ret)
+		goto cleanup;
+
+	ret = __sdhci_add_host(host);
+	if (ret)
+		goto cleanup;
+
+	return 0;
+
+cleanup:
+	sdhci_cleanup_host(host);
+	return ret;
+}
+
+static int eswin_sdhci_sdio_probe(struct platform_device *pdev)
+{
+	int ret;
+	struct clk *clk_xin;
+	struct clk *clk_spll2_fout3;
+	struct clk *clk_mux;
+	struct sdhci_host *host;
+	struct sdhci_pltfm_host *pltfm_host;
+	struct device *dev = &pdev->dev;
+	struct device_node *np = dev->of_node;
+	struct eswin_sdhci_data *eswin_sdhci_sdio;
+	struct eswin_sdio_private *eswin_sdio_priv;
+	struct regmap *regmap;
+	const struct eswin_sdhci_of_data *data;
+	unsigned int sdio_id = 0;
+	unsigned int val = 0;
+
+	data = of_device_get_match_data(dev);
+	host = sdhci_pltfm_init(pdev, data->pdata, sizeof(*eswin_sdhci_sdio) + sizeof(*eswin_sdio_priv));
+
+	if (IS_ERR(host))
+		return PTR_ERR(host);
+
+	pltfm_host = sdhci_priv(host);
+	eswin_sdhci_sdio = sdhci_pltfm_priv(pltfm_host);
+	eswin_sdhci_sdio->host = host;
+	eswin_sdhci_sdio->has_cqe = false;
+	eswin_sdio_priv = sdhci_sdio_priv(eswin_sdhci_sdio);
+
+	ret = of_property_read_u32(dev->of_node, "core-clk-reg", &val);
+	if (ret) {
+		dev_err(dev, "get core clk reg failed.\n");
+		goto err_pltfm_free;
+	}
+
+	eswin_sdhci_sdio->core_clk_reg = ioremap(val, 0x4);
+	if (!eswin_sdhci_sdio->core_clk_reg) {
+		dev_err(dev, "ioremap core clk reg failed.\n");
+		goto err_pltfm_free;
+	}
+
+	ret = of_property_read_u32(dev->of_node, "sdio-id", &sdio_id);
+	if (ret) {
+		dev_err(dev, "get sdio-id failed.\n");
+		goto err_pltfm_free;
+	}
+
+	sdhci_get_of_property(pdev);
+
+	eswin_sdhci_sdio->clk_ops = data->clk_ops;
+	eswin_sdhci_sdio->clk_ahb = devm_clk_get(dev, "clk_ahb");
+	if (IS_ERR(eswin_sdhci_sdio->clk_ahb)) {
+		ret = dev_err_probe(dev, PTR_ERR(eswin_sdhci_sdio->clk_ahb),
+				    "clk_ahb clock not found.\n");
+		goto err_pltfm_free;
+	}
+
+	clk_xin = devm_clk_get(dev, "clk_xin");
+	if (IS_ERR(clk_xin)) {
+		ret = dev_err_probe(dev, PTR_ERR(clk_xin),
+				    "clk_xin clock not found.\n");
+		goto err_pltfm_free;
+	}
+
+	clk_spll2_fout3 = devm_clk_get(dev, "clk_spll2_fout3");
+
+	if (IS_ERR(clk_spll2_fout3)) {
+		ret = dev_err_probe(dev, PTR_ERR(clk_spll2_fout3),
+				    "clk_spll2_fout3 clock not found.\n");
+		goto err_pltfm_free;
+	}
+
+	if (of_device_is_compatible(np, "eswin,sdhci-sdio")) {
+		clk_mux = devm_clk_get(dev, "clk_mux1_1");
+		if (IS_ERR(clk_mux)) {
+			ret = dev_err_probe(dev, PTR_ERR(clk_mux),
+					    "clk_mux1_1 clock not found.\n");
+			goto err_pltfm_free;
+		}
+		/*switch the core clk source*/
+		clk_set_parent(clk_mux, clk_spll2_fout3);
+	}
+
+	ret = clk_prepare_enable(eswin_sdhci_sdio->clk_ahb);
+	if (ret) {
+		dev_err(dev, "Unable to enable AHB clock.\n");
+		goto err_pltfm_free;
+	}
+	/* If clock-frequency property is set, use the provided value */
+	if (pltfm_host->clock && pltfm_host->clock != clk_get_rate(clk_xin)) {
+		ret = clk_set_rate(clk_xin, pltfm_host->clock);
+		if (ret) {
+			dev_err(&pdev->dev, "Failed to set SD clock rate\n");
+			goto clk_dis_ahb;
+		}
+	}
+
+	ret = clk_prepare_enable(clk_xin);
+	if (ret) {
+		dev_err(dev, "Unable to enable SD clock.\n");
+		goto clk_dis_ahb;
+	}
+
+	pltfm_host->clk = clk_xin;
+	ret = eswin_sdhci_sdio_register_sdclk(eswin_sdhci_sdio, clk_xin, dev);
+	if (ret)
+		goto clk_disable_all;
+
+	ret = eswin_sdhci_reset_init(dev, eswin_sdhci_sdio);
+	if (ret < 0) {
+		dev_err(dev, "failed to reset\n");
+		goto clk_disable_all;
+	}
+
+	regmap = syscon_regmap_lookup_by_phandle(dev->of_node,
+						 "eswin,hsp_sp_csr");
+	if (IS_ERR(regmap)) {
+		dev_dbg(dev, "No hsp_sp_csr phandle specified\n");
+		return 0;
+	}
+
+	if (sdio_id == 0) {
+		regmap_write(regmap, ESWIN_SDHCI_SD0_INT_STATUS,
+			     MSHC_INT_CLK_STABLE);
+		regmap_write(regmap, ESWIN_SDHCI_SD0_PWR_CTRL, MSHC_HOST_VAL_STABLE);
+	} else {
+		regmap_write(regmap, ESWIN_SDHCI_SD1_INT_STATUS,
+			     MSHC_INT_CLK_STABLE);
+		regmap_write(regmap, ESWIN_SDHCI_SD1_PWR_CTRL, MSHC_HOST_VAL_STABLE);
+	}
+
+	if (!of_property_read_u32(dev->of_node, "delay_code", &val)) {
+		eswin_sdhci_sdio->phy.delay_code = val;
+	}
+
+	if (!of_property_read_u32(dev->of_node, "drive-impedance-ohm", &val))
+		eswin_sdhci_sdio->phy.drive_impedance =
+			eswin_convert_drive_impedance_ohm(pdev, val);
+
+	if (of_property_read_bool(dev->of_node, "enable-cmd-pullup"))
+		eswin_sdhci_sdio->phy.enable_cmd_pullup = ENABLE;
+	else
+		eswin_sdhci_sdio->phy.enable_cmd_pullup = DISABLE;
+
+	if (of_property_read_bool(dev->of_node, "enable-data-pullup"))
+		eswin_sdhci_sdio->phy.enable_data_pullup = ENABLE;
+	else
+		eswin_sdhci_sdio->phy.enable_data_pullup = DISABLE;
+
+	if (of_property_read_bool(dev->of_node, "enable_sw_tuning"))
+		eswin_sdio_priv->enable_sw_tuning = ENABLE;
+	else
+		eswin_sdio_priv->enable_sw_tuning = DISABLE;
+
+	if (!of_property_read_u32(dev->of_node, "phase_code", &val)) {
+		eswin_sdio_priv->phase_code = val;
+	} else {
+		eswin_sdio_priv->phase_code = -1;
+	}
+
+	eswin_sdhci_dt_parse_clk_phases(dev, &eswin_sdhci_sdio->clk_data);
+	ret = mmc_of_parse(host->mmc);
+	if (ret) {
+		ret = dev_err_probe(dev, ret, "parsing dt failed.\n");
+		goto unreg_clk;
+	}
+
+	ret = eswin_sdhci_sdio_add_host(eswin_sdhci_sdio);
+	if (ret)
+		goto unreg_clk;
+
+	return 0;
+
+unreg_clk:
+	eswin_sdhci_sdio_unregister_sdclk(dev);
+clk_disable_all:
+	clk_disable_unprepare(clk_xin);
+clk_dis_ahb:
+	clk_disable_unprepare(eswin_sdhci_sdio->clk_ahb);
+err_pltfm_free:
+	if (eswin_sdhci_sdio->core_clk_reg)
+		iounmap(eswin_sdhci_sdio->core_clk_reg);
+
+	sdhci_pltfm_free(pdev);
+	return ret;
+}
+
+static void eswin_sdhci_sdio_remove(struct platform_device *pdev)
+{
+	int ret;
+	struct sdhci_host *host = platform_get_drvdata(pdev);
+	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
+	struct eswin_sdhci_data *eswin_sdhci_sdio =
+		sdhci_pltfm_priv(pltfm_host);
+	struct clk *clk_ahb = eswin_sdhci_sdio->clk_ahb;
+	void __iomem *core_clk_reg = eswin_sdhci_sdio->core_clk_reg;
+
+	sdhci_pltfm_remove(pdev);
+
+	if (eswin_sdhci_sdio->txrx_rst) {
+		ret = reset_control_assert(eswin_sdhci_sdio->txrx_rst);
+		WARN_ON(0 != ret);
+	}
+
+	if (eswin_sdhci_sdio->phy_rst) {
+		ret = reset_control_assert(eswin_sdhci_sdio->phy_rst);
+		WARN_ON(0 != ret);
+	}
+
+	if (eswin_sdhci_sdio->prstn) {
+		ret = reset_control_assert(eswin_sdhci_sdio->prstn);
+		WARN_ON(0 != ret);
+	}
+
+	if (eswin_sdhci_sdio->arstn) {
+		ret = reset_control_assert(eswin_sdhci_sdio->arstn);
+		WARN_ON(0 != ret);
+	}
+
+	eswin_sdhci_sdio_unregister_sdclk(&pdev->dev);
+	clk_disable_unprepare(clk_ahb);
+	iounmap(core_clk_reg);
+}
+
+static struct platform_driver eswin_sdhci_sdio_driver = {
+	.driver = {
+		.name = "eswin-sdhci-sdio",
+		.probe_type = PROBE_PREFER_ASYNCHRONOUS,
+		.of_match_table = eswin_sdhci_sdio_of_match,
+		.pm = &eswin_sdhci_sdio_dev_pm_ops,
+	},
+	.probe = eswin_sdhci_sdio_probe,
+	.remove = eswin_sdhci_sdio_remove,
+};
+
+static __init int eswin_sdhci_sdio_init(void)
+{
+	int ret;
+
+	ret = platform_driver_register(&eswin_sdhci_sdio_driver);
+	if (ret) {
+		pr_err("%s: failed to register platform driver\n", __func__);
+	}
+
+	return ret;
+}
+
+static void __exit eswin_sdhci_sdio_exit(void)
+{
+	platform_driver_unregister(&eswin_sdhci_sdio_driver);
+}
+
+/* Cause: EMMC is often used as a system disk(mmc0), we need the SD driver to run later than the EMMC driver */
+late_initcall(eswin_sdhci_sdio_init);
+module_exit(eswin_sdhci_sdio_exit);
+
+MODULE_DESCRIPTION("Driver for the Eswin SDHCI Controller");
+MODULE_AUTHOR("Eswin");
+MODULE_LICENSE("GPL");
diff --git a/drivers/mmc/host/sdhci-of-eswin.c b/drivers/mmc/host/sdhci-of-eswin.c
new file mode 100644
index 000000000000..7b5c2efd737e
--- /dev/null
+++ b/drivers/mmc/host/sdhci-of-eswin.c
@@ -0,0 +1,1035 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * ESWIN Emmc Driver
+ *
+ * Copyright 2024, Beijing ESWIN Computing Technology Co., Ltd.. All rights reserved.
+ * SPDX-License-Identifier: GPL-2.0
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, version 2.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <https://www.gnu.org/licenses/>.
+ *
+ * Authors: Shuang Liang <liangshuang@eswincomputing.com>
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/mfd/syscon.h>
+#include <linux/module.h>
+#include <linux/of_device.h>
+#include <linux/phy/phy.h>
+#include <linux/regmap.h>
+#include <linux/of.h>
+#include "cqhci.h"
+#include "sdhci-pltfm.h"
+#include <linux/reset.h>
+#include <linux/bitfield.h>
+#include <linux/regmap.h>
+#include "sdhci-eswin.h"
+
+#define SDHCI_EMMC0_INT_STATUS 0x508
+#define SDHCI_EMMC0_PWR_CLEAR 0x50c
+
+#define eswin_sdhci_VENDOR_REGISTER_BASEADDR 0x800
+#define eswin_sdhci_VENDOR_EMMC_CTRL_REGISTER 0x2c
+#define VENDOR_ENHANCED_STROBE BIT(8)
+
+#define eswin_sdhci_CQE_BASE_ADDR eswin_sdhci_VENDOR_REGISTER_BASEADDR
+
+/* Controller does not have CD wired and will not function normally without */
+#define eswin_sdhci_QUIRK_FORCE_CDTEST BIT(0)
+
+/* Controller immediately reports SDHCI_CLOCK_INT_STABLE after enabling the
+ * internal clock even when the clock isn't stable */
+#define eswin_sdhci_QUIRK_CLOCK_UNSTABLE BIT(1)
+
+/*
+ * On some SoCs the syscon area has a feature where the upper 16-bits of
+ * each 32-bit register act as a write mask for the lower 16-bits.  This allows
+ * atomic updates of the register without locking.  This macro is used on SoCs
+ * that have that feature.
+ */
+#define HIWORD_UPDATE(val, mask, shift) \
+	((val) << (shift) | (mask) << ((shift) + 16))
+
+#define ESWIN_EMMC_CORE_CLK_REG 0x51828160
+
+static void eswin_sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
+{
+	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
+	struct eswin_sdhci_data *eswin_sdhci = sdhci_pltfm_priv(pltfm_host);
+	struct eswin_sdhci_clk_data *clk_data = &eswin_sdhci->clk_data;
+
+	/* Set the Input and Output Clock Phase Delays */
+	if (clk_data->set_clk_delays)
+		clk_data->set_clk_delays(host);
+
+	eswin_sdhci_set_core_clock(host, clock);
+	sdhci_set_clock(host, clock);
+
+	/*
+	 * Some controllers immediately report SDHCI_CLOCK_INT_STABLE
+	 * after enabling the clock even though the clock is not
+	 * stable. Trying to use a clock without waiting here results
+	 * in EILSEQ while detecting some older/slower cards. The
+	 * chosen delay is the maximum delay from sdhci_set_clock.
+	 */
+	if (eswin_sdhci->quirks & SDHCI_ESWIN_QUIRK_CLOCK_UNSTABLE)
+		msleep(20);
+}
+
+static void eswin_sdhci_hs400_enhanced_strobe(struct mmc_host *mmc,
+					      struct mmc_ios *ios)
+{
+	u32 vendor;
+	struct sdhci_host *host = mmc_priv(mmc);
+
+	vendor = sdhci_readl(host, eswin_sdhci_VENDOR_EMMC_CTRL_REGISTER);
+	if (ios->enhanced_strobe)
+		vendor |= VENDOR_ENHANCED_STROBE;
+	else
+		vendor &= ~VENDOR_ENHANCED_STROBE;
+
+	sdhci_writel(host, vendor, eswin_sdhci_VENDOR_EMMC_CTRL_REGISTER);
+}
+
+static void eswin_sdhci_config_phy_delay(struct sdhci_host *host, int delay)
+{
+	delay &= PHY_CLK_MAX_DELAY_MASK;
+
+	/*phy clk delay line config*/
+	sdhci_writeb(host, PHY_UPDATE_DELAY_CODE, PHY_SDCLKDL_CNFG_R);
+	sdhci_writeb(host, delay, PHY_SDCLKDL_DC_R);
+	sdhci_writeb(host, 0x0, PHY_SDCLKDL_CNFG_R);
+}
+
+static void eswin_sdhci_config_phy(struct sdhci_host *host)
+{
+	unsigned int val = 0;
+	unsigned int drv = 0;
+	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
+	struct eswin_sdhci_data *eswin_sdhci = sdhci_pltfm_priv(pltfm_host);
+	struct eswin_sdhci_phy_data *phy = &eswin_sdhci->phy;
+
+	drv = phy->drive_impedance << PHY_PAD_SP_DRIVE_SHIF;
+
+	val = sdhci_readw(host, VENDOR_EMMC_CTRL_R);
+	val |= EMMC_CRAD_PRESENT;
+	sdhci_writew(host, val, VENDOR_EMMC_CTRL_R);
+
+	eswin_sdhci_disable_card_clk(host);
+
+	/* reset phy,config phy's pad */
+	sdhci_writel(host, drv | (~PHY_RSTN), PHY_CNFG_R);
+	/*CMDPAD_CNFS*/
+	val = (PHY_SLEW_2 << PHY_TX_SLEW_CTRL_P_BIT_SHIFT) |
+		(PHY_SLEW_2 << PHY_TX_SLEW_CTRL_N_BIT_SHIFT) |
+		(phy->enable_cmd_pullup << PHY_PULL_BIT_SHIF) | PHY_PAD_RXSEL_1;
+	sdhci_writew(host, val, PHY_CMDPAD_CNFG_R);
+
+	/*DATA PAD CNFG*/
+	val = (PHY_SLEW_2 << PHY_TX_SLEW_CTRL_P_BIT_SHIFT) |
+		(PHY_SLEW_2 << PHY_TX_SLEW_CTRL_N_BIT_SHIFT) |
+		(phy->enable_data_pullup << PHY_PULL_BIT_SHIF) | PHY_PAD_RXSEL_1;
+	sdhci_writew(host, val, PHY_DATAPAD_CNFG_R);
+
+	/*Clock PAD Setting*/
+	val = (PHY_SLEW_2 << PHY_TX_SLEW_CTRL_P_BIT_SHIFT) |
+		(PHY_SLEW_2 << PHY_TX_SLEW_CTRL_N_BIT_SHIFT) | PHY_PAD_RXSEL_0;
+	sdhci_writew(host, val, PHY_CLKPAD_CNFG_R);
+
+	/*PHY strobe PAD setting*/
+	val = (PHY_SLEW_2 << PHY_TX_SLEW_CTRL_P_BIT_SHIFT) |
+		(PHY_SLEW_2 << PHY_TX_SLEW_CTRL_N_BIT_SHIFT) |
+		((phy->enable_strobe_pulldown * PHY_PULL_DOWN) << PHY_PULL_BIT_SHIF) |
+		PHY_PAD_RXSEL_1;
+	sdhci_writew(host, val, PHY_STBPAD_CNFG_R);
+	mdelay(2);
+
+	/*PHY RSTN PAD setting*/
+	val = (PHY_SLEW_2 << PHY_TX_SLEW_CTRL_P_BIT_SHIFT) |
+		(PHY_SLEW_2 << PHY_TX_SLEW_CTRL_N_BIT_SHIFT) |
+		(PHY_PULL_UP << PHY_PULL_BIT_SHIF) | PHY_PAD_RXSEL_1;
+	sdhci_writew(host, val, PHY_RSTNPAD_CNFG_R);
+
+	sdhci_writel(host, drv | PHY_RSTN, PHY_CNFG_R);
+
+	eswin_sdhci_config_phy_delay(host, phy->delay_code);
+
+	eswin_sdhci_enable_card_clk(host);
+}
+
+static void eswin_sdhci_reset(struct sdhci_host *host, u8 mask)
+{
+	u8 ctrl;
+	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
+	struct eswin_sdhci_data *eswin_sdhci = sdhci_pltfm_priv(pltfm_host);
+
+	/* Disable signal and interrupts before resetting the phy.
+	 * Doing this avoids ISR to serve any undesired interrupts during
+	 * reset and avoid producing the fake register dump during probe.
+	 */
+	sdhci_writel(host, 0, SDHCI_INT_ENABLE);
+	sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
+	sdhci_reset(host, mask);
+	sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
+	sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
+
+	if (eswin_sdhci->quirks & SDHCI_ESWIN_QUIRK_FORCE_CDTEST) {
+		ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
+		ctrl |= SDHCI_CTRL_CDTEST_INS | SDHCI_CTRL_CDTEST_EN;
+		sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
+	}
+
+	if (mask == SDHCI_RESET_ALL) {
+		/* after reset all,the phy`s config will be clear. */
+		eswin_sdhci_config_phy(host);
+	}
+}
+
+static u32 eswin_sdhci_cqhci_irq(struct sdhci_host *host, u32 intmask)
+{
+	int cmd_error = 0;
+	int data_error = 0;
+
+	if (!sdhci_cqe_irq(host, intmask, &cmd_error, &data_error))
+		return intmask;
+
+	cqhci_irq(host->mmc, intmask, cmd_error, data_error);
+
+	return 0;
+}
+
+static void eswin_sdhci_dumpregs(struct mmc_host *mmc)
+{
+	sdhci_dumpregs(mmc_priv(mmc));
+}
+
+static void eswin_sdhci_cqe_enable(struct mmc_host *mmc)
+{
+	struct sdhci_host *host = mmc_priv(mmc);
+	u32 reg;
+
+	reg = sdhci_readl(host, SDHCI_PRESENT_STATE);
+	while (reg & SDHCI_DATA_AVAILABLE) {
+		sdhci_readl(host, SDHCI_BUFFER);
+		reg = sdhci_readl(host, SDHCI_PRESENT_STATE);
+	}
+
+	sdhci_cqe_enable(mmc);
+}
+
+static int eswin_sdhci_delay_tuning(struct sdhci_host *host, u32 opcode)
+{
+	int ret;
+	int delay = 0;
+	int i = 0;
+	int delay_min = -1;
+	int delay_max = -1;
+	int cmd_error = 0;
+	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
+	struct eswin_sdhci_data *eswin_sdhci = sdhci_pltfm_priv(pltfm_host);
+
+	for (i = 0; i <= PHY_DELAY_CODE_MAX; i++) {
+		eswin_sdhci_disable_card_clk(host);
+		eswin_sdhci_config_phy_delay(host, i);
+		eswin_sdhci_enable_card_clk(host);
+		ret = mmc_send_tuning(host->mmc, opcode, &cmd_error);
+		if (ret) {
+			host->ops->reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
+			udelay(200);
+			if (delay_min != -1 && delay_max != -1)
+				break;
+		} else {
+			if (delay_min == -1) {
+				delay_min = i;
+				continue;
+			} else {
+				delay_max = i;
+				continue;
+			}
+		}
+	}
+	if (delay_min == -1 && delay_max == -1) {
+		pr_err("%s: delay code tuning failed!\n",
+					mmc_hostname(host->mmc));
+		eswin_sdhci_disable_card_clk(host);
+		eswin_sdhci_config_phy_delay(host, eswin_sdhci->phy.delay_code);
+		eswin_sdhci_enable_card_clk(host);
+
+		return ret;
+	}
+
+	delay = (delay_min + delay_max) / 2;
+	pr_info("%s: set delay:0x%x\n", mmc_hostname(host->mmc), delay);
+	eswin_sdhci_disable_card_clk(host);
+	eswin_sdhci_config_phy_delay(host, delay);
+	eswin_sdhci_enable_card_clk(host);
+
+	return 0;
+}
+
+static int eswin_sdhci_phase_code_tuning(struct sdhci_host *host, u32 opcode)
+{
+	int cmd_error = 0;
+	int ret = 0;
+	int phase_code = 0;
+	int code_min = -1;
+	int code_max = -1;
+
+	for (phase_code = 0; phase_code <= MAX_PHASE_CODE; phase_code++) {
+		eswin_sdhci_disable_card_clk(host);
+		sdhci_writew(host, phase_code, VENDOR_AT_SATA_R);
+		eswin_sdhci_enable_card_clk(host);
+
+		ret = mmc_send_tuning(host->mmc, opcode, &cmd_error);
+		if (ret) {
+			host->ops->reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
+			udelay(200);
+			if (code_min != -1 && code_max != -1)
+				break;
+		} else {
+			if (code_min == -1) {
+				code_min = phase_code;
+				continue;
+			} else {
+				code_max = phase_code;
+				continue;
+			}
+		}
+	}
+	if (code_min == -1 && code_max == -1) {
+		pr_err("%s: phase code tuning failed!\n",
+					mmc_hostname(host->mmc));
+		eswin_sdhci_disable_card_clk(host);
+		sdhci_writew(host, 0, VENDOR_AT_SATA_R);
+		eswin_sdhci_enable_card_clk(host);
+		return -EIO;
+	}
+
+	phase_code = (code_min + code_max) / 2;
+	pr_info("%s: set phase_code:0x%x\n", mmc_hostname(host->mmc), phase_code);
+
+	eswin_sdhci_disable_card_clk(host);
+	sdhci_writew(host, phase_code, VENDOR_AT_SATA_R);
+	eswin_sdhci_enable_card_clk(host);
+
+	return 0;
+}
+
+static int eswin_sdhci_executing_tuning(struct sdhci_host *host, u32 opcode)
+{
+	u32 ctrl;
+	u32 val;
+	int ret = 0;
+
+	eswin_sdhci_disable_card_clk(host);
+
+	ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
+	ctrl &= ~SDHCI_CTRL_TUNED_CLK;
+	sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
+
+	val = sdhci_readl(host, VENDOR_AT_CTRL_R);
+	val |= SW_TUNE_ENABLE;
+	sdhci_writew(host, val, VENDOR_AT_CTRL_R);
+	sdhci_writew(host, 0, VENDOR_AT_SATA_R);
+
+	eswin_sdhci_enable_card_clk(host);
+
+	sdhci_writew(host, 0x0, SDHCI_CMD_DATA);
+
+	ret = eswin_sdhci_delay_tuning(host, opcode);
+	if (ret < 0) {
+		return ret;
+	}
+	ret = eswin_sdhci_phase_code_tuning(host, opcode);
+	if (ret < 0) {
+		return ret;
+	}
+
+	return 0;
+}
+
+static void eswin_sdhci_set_uhs_signaling(struct sdhci_host *host, unsigned timing)
+{
+	u32 val;
+	u32 status;
+	u32 timeout = 0;
+	u16 ctrl_2;
+
+	ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
+	/* Select Bus Speed Mode for host */
+	ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
+	if ((timing == MMC_TIMING_MMC_HS200) ||
+	    (timing == MMC_TIMING_UHS_SDR104))
+		ctrl_2 |= SDHCI_CTRL_UHS_SDR104;
+	else if (timing == MMC_TIMING_UHS_SDR12)
+		ctrl_2 |= SDHCI_CTRL_UHS_SDR12;
+	else if (timing == MMC_TIMING_UHS_SDR25)
+		ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
+	else if (timing == MMC_TIMING_UHS_SDR50)
+		ctrl_2 |= SDHCI_CTRL_UHS_SDR50;
+	else if ((timing == MMC_TIMING_UHS_DDR50) ||
+		 (timing == MMC_TIMING_MMC_DDR52))
+		ctrl_2 |= SDHCI_CTRL_UHS_DDR50;
+	else if (timing == MMC_TIMING_MMC_HS400)
+		ctrl_2 |= ESWIN_SDHCI_CTRL_HS400; /* Non-standard */
+	sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
+
+
+	/*
+	 * here need make dll locked when in hs400 at 200MHz
+	 */
+	if ((timing == MMC_TIMING_MMC_HS400) && (host->clock == 200000000)) {
+		eswin_sdhci_disable_card_clk(host);
+
+		val = sdhci_readl(host, VENDOR_AT_CTRL_R);
+		val &= ~(LATENCY_LT_MASK << LATENCY_LT_BIT_OFFSET);
+		val |= (LATENCY_LT_3 << LATENCY_LT_MASK);
+		sdhci_writel(host, val, VENDOR_AT_CTRL_R);
+
+		sdhci_writeb(host, 0x23, PHY_DLL_CNFG1_R);
+		sdhci_writeb(host, 0x02, PHY_DLL_CNFG2_R);
+		sdhci_writeb(host, 0x60, PHY_DLLDL_CNFG_R);
+		sdhci_writeb(host, 0x00, PHY_DLL_OFFST_R);
+		sdhci_writew(host, 0xffff, PHY_DLLBT_CNFG_R);
+
+		eswin_sdhci_enable_card_clk(host);
+		sdhci_writeb(host, DLL_ENABEL, PHY_DLL_CTRL_R);
+		udelay(100);
+
+		while (1) {
+			status = sdhci_readb(host, PHY_DLL_STATUS_R);
+			if (status & DLL_LOCK_STS) {
+				pr_debug("%s: locked status:0x%x\n", mmc_hostname(host->mmc), status);
+				break;
+			}
+			timeout++;
+			udelay(100);
+			if (timeout > 10000) {
+				pr_err("%s: DLL lock failed!status:0x%x\n",
+					mmc_hostname(host->mmc), status);
+				return;
+			}
+		}
+
+		status = sdhci_readb(host, PHY_DLL_STATUS_R);
+		if (status & DLL_ERROR_STS) {
+			pr_err("%s: DLL lock failed!err_status:0x%x\n",
+				mmc_hostname(host->mmc), status);
+		} else {
+			pr_debug("%s: DLL lock is success\n", mmc_hostname(host->mmc));
+		}
+	}
+}
+
+static const struct cqhci_host_ops eswin_sdhci_cqhci_ops = {
+	.enable = eswin_sdhci_cqe_enable,
+	.disable = sdhci_cqe_disable,
+	.dumpregs = eswin_sdhci_dumpregs,
+};
+
+static const struct sdhci_ops eswin_sdhci_cqe_ops = {
+	.set_clock = eswin_sdhci_set_clock,
+	.get_max_clock = sdhci_pltfm_clk_get_max_clock,
+	.get_timeout_clock = sdhci_pltfm_clk_get_max_clock,
+	.set_bus_width = sdhci_set_bus_width,
+	.reset = eswin_sdhci_reset,
+	.set_uhs_signaling = eswin_sdhci_set_uhs_signaling,
+	.set_power = sdhci_set_power_and_bus_voltage,
+	.irq = eswin_sdhci_cqhci_irq,
+	.platform_execute_tuning = eswin_sdhci_executing_tuning,
+};
+
+static const struct sdhci_pltfm_data eswin_sdhci_cqe_pdata = {
+	.ops = &eswin_sdhci_cqe_ops,
+	.quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
+	.quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
+#if defined(__DISABLE_HS200)
+		SDHCI_QUIRK2_BROKEN_HS200 |
+#endif
+		SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN,
+};
+
+#ifdef CONFIG_PM_SLEEP
+/**
+ * eswin_sdhci_suspend - Suspend method for the driver
+ * @dev:    Address of the device structure
+ *
+ * Put the device in a low power state.
+ *
+ * Return: 0 on success and error value on error
+ */
+static int eswin_sdhci_suspend(struct device *dev)
+{
+	struct sdhci_host *host = dev_get_drvdata(dev);
+	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
+	struct eswin_sdhci_data *eswin_sdhci = sdhci_pltfm_priv(pltfm_host);
+	int ret;
+
+	if (host->tuning_mode != SDHCI_TUNING_MODE_3)
+		mmc_retune_needed(host->mmc);
+
+	if (eswin_sdhci->has_cqe) {
+		ret = cqhci_suspend(host->mmc);
+		if (ret)
+			return ret;
+	}
+
+	ret = sdhci_suspend_host(host);
+	if (ret)
+		return ret;
+
+	clk_disable(pltfm_host->clk);
+	clk_disable(eswin_sdhci->clk_ahb);
+
+	return 0;
+}
+
+/**
+ * eswin_sdhci_resume - Resume method for the driver
+ * @dev:    Address of the device structure
+ *
+ * Resume operation after suspend
+ *
+ * Return: 0 on success and error value on error
+ */
+static int eswin_sdhci_resume(struct device *dev)
+{
+	struct sdhci_host *host = dev_get_drvdata(dev);
+	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
+	struct eswin_sdhci_data *eswin_sdhci = sdhci_pltfm_priv(pltfm_host);
+	int ret;
+
+	ret = clk_enable(eswin_sdhci->clk_ahb);
+	if (ret) {
+		dev_err(dev, "Cannot enable AHB clock.\n");
+		return ret;
+	}
+
+	ret = clk_enable(pltfm_host->clk);
+	if (ret) {
+		dev_err(dev, "Cannot enable SD clock.\n");
+		return ret;
+	}
+
+	ret = sdhci_resume_host(host);
+	if (ret) {
+		dev_err(dev, "Cannot resume host.\n");
+		return ret;
+	}
+
+	if (eswin_sdhci->has_cqe)
+		return cqhci_resume(host->mmc);
+
+	return 0;
+}
+#endif /* ! CONFIG_PM_SLEEP */
+
+static SIMPLE_DEV_PM_OPS(eswin_sdhci_dev_pm_ops, eswin_sdhci_suspend,
+			 eswin_sdhci_resume);
+
+/**
+ * eswin_sdhci_sdcardclk_recalc_rate - Return the card clock rate
+ *
+ * @hw:         Pointer to the hardware clock structure.
+ * @parent_rate:        The parent rate (should be rate of clk_xin).
+ *
+ * Return the current actual rate of the SD card clock.  This can be used
+ * to communicate with out PHY.
+ *
+ * Return: The card clock rate.
+ */
+static unsigned long
+eswin_sdhci_sdcardclk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
+{
+	struct eswin_sdhci_clk_data *clk_data =
+		container_of(hw, struct eswin_sdhci_clk_data, sdcardclk_hw);
+	struct eswin_sdhci_data *eswin_sdhci =
+		container_of(clk_data, struct eswin_sdhci_data, clk_data);
+	struct sdhci_host *host = eswin_sdhci->host;
+
+	return host->mmc->actual_clock;
+}
+
+static const struct clk_ops eswin_sdcardclk_ops = {
+	.recalc_rate = eswin_sdhci_sdcardclk_recalc_rate,
+};
+
+/**
+ * eswin_sdhci_sampleclk_recalc_rate - Return the sampling clock rate
+ *
+ * @hw:         Pointer to the hardware clock structure.
+ * @parent_rate:        The parent rate (should be rate of clk_xin).
+ *
+ * Return the current actual rate of the sampling clock.  This can be used
+ * to communicate with out PHY.
+ *
+ * Return: The sample clock rate.
+ */
+static unsigned long
+eswin_sdhci_sampleclk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
+{
+	struct eswin_sdhci_clk_data *clk_data =
+		container_of(hw, struct eswin_sdhci_clk_data, sampleclk_hw);
+	struct eswin_sdhci_data *eswin_sdhci =
+		container_of(clk_data, struct eswin_sdhci_data, clk_data);
+	struct sdhci_host *host = eswin_sdhci->host;
+
+	return host->mmc->actual_clock;
+}
+
+static const struct clk_ops eswin_sampleclk_ops = {
+	.recalc_rate = eswin_sdhci_sampleclk_recalc_rate,
+};
+
+static const struct eswin_sdhci_clk_ops eswin_clk_ops = {
+	.sdcardclk_ops = &eswin_sdcardclk_ops,
+	.sampleclk_ops = &eswin_sampleclk_ops,
+};
+
+static struct eswin_sdhci_of_data eswin_sdhci_fu800_data = {
+	.pdata = &eswin_sdhci_cqe_pdata,
+	.clk_ops = &eswin_clk_ops,
+};
+
+static const struct of_device_id eswin_sdhci_of_match[] = {
+	{
+		.compatible = "eswin,emmc-sdhci-5.1",
+		.data = &eswin_sdhci_fu800_data,
+	},
+	{ /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, eswin_sdhci_of_match);
+
+/**
+ * eswin_sdhci_register_sdcardclk - Register the sdcardclk for a PHY to use
+ *
+ * @eswin_sdhci:    Our private data structure.
+ * @clk_xin:        Pointer to the functional clock
+ * @dev:        Pointer to our struct device.
+ *
+ * Some PHY devices need to know what the actual card clock is.  In order for
+ * them to find out, we'll provide a clock through the common clock framework
+ * for them to query.
+ *
+ * Return: 0 on success and error value on error
+ */
+static int eswin_sdhci_register_sdcardclk(struct eswin_sdhci_data *eswin_sdhci,
+									struct clk *clk_xin, struct device *dev)
+{
+	struct eswin_sdhci_clk_data *clk_data = &eswin_sdhci->clk_data;
+	struct device_node *np = dev->of_node;
+	struct clk_init_data sdcardclk_init;
+	const char *parent_clk_name;
+	int ret;
+
+	ret = of_property_read_string_index(np, "clock-output-names", 0,
+						&sdcardclk_init.name);
+	if (ret) {
+		dev_err(dev, "DT has #clock-cells but no clock-output-names\n");
+		return ret;
+	}
+
+	parent_clk_name = __clk_get_name(clk_xin);
+	sdcardclk_init.parent_names = &parent_clk_name;
+	sdcardclk_init.num_parents = 1;
+	sdcardclk_init.flags = CLK_GET_RATE_NOCACHE;
+	sdcardclk_init.ops = eswin_sdhci->clk_ops->sdcardclk_ops;
+
+	clk_data->sdcardclk_hw.init = &sdcardclk_init;
+	clk_data->sdcardclk = devm_clk_register(dev, &clk_data->sdcardclk_hw);
+	if (IS_ERR(clk_data->sdcardclk))
+		return PTR_ERR(clk_data->sdcardclk);
+	clk_data->sdcardclk_hw.init = NULL;
+
+	ret = of_clk_add_provider(np, of_clk_src_simple_get,
+							clk_data->sdcardclk);
+	if (ret)
+		dev_err(dev, "Failed to add sdcard clock provider\n");
+
+	return ret;
+}
+
+/**
+ * eswin_sdhci_register_sampleclk - Register the sampleclk for a PHY to use
+ *
+ * @eswin_sdhci:    Our private data structure.
+ * @clk_xin:        Pointer to the functional clock
+ * @dev:        Pointer to our struct device.
+ *
+ * Some PHY devices need to know what the actual card clock is.  In order for
+ * them to find out, we'll provide a clock through the common clock framework
+ * for them to query.
+ *
+ * Return: 0 on success and error value on error
+ */
+static int eswin_sdhci_register_sampleclk(struct eswin_sdhci_data *eswin_sdhci,
+						struct clk *clk_xin, struct device *dev)
+{
+	struct eswin_sdhci_clk_data *clk_data = &eswin_sdhci->clk_data;
+	struct device_node *np = dev->of_node;
+	struct clk_init_data sampleclk_init;
+	const char *parent_clk_name;
+	int ret;
+
+	ret = of_property_read_string_index(np, "clock-output-names", 1,
+						&sampleclk_init.name);
+	if (ret) {
+		dev_err(dev, "DT has #clock-cells but no clock-output-names\n");
+		return ret;
+	}
+
+	parent_clk_name = __clk_get_name(clk_xin);
+	sampleclk_init.parent_names = &parent_clk_name;
+	sampleclk_init.num_parents = 1;
+	sampleclk_init.flags = CLK_GET_RATE_NOCACHE;
+	sampleclk_init.ops = eswin_sdhci->clk_ops->sampleclk_ops;
+
+	clk_data->sampleclk_hw.init = &sampleclk_init;
+	clk_data->sampleclk = devm_clk_register(dev, &clk_data->sampleclk_hw);
+	if (IS_ERR(clk_data->sampleclk))
+		return PTR_ERR(clk_data->sampleclk);
+	clk_data->sampleclk_hw.init = NULL;
+
+	ret = of_clk_add_provider(np, of_clk_src_simple_get,
+				  clk_data->sampleclk);
+	if (ret)
+		dev_err(dev, "Failed to add sample clock provider\n");
+
+	return ret;
+}
+
+/**
+ * eswin_sdhci_unregister_sdclk - Undoes eswin_sdhci_register_sdclk()
+ *
+ * @dev:        Pointer to our struct device.
+ *
+ * Should be called any time we're exiting and eswin_sdhci_register_sdclk()
+ * returned success.
+ */
+static void eswin_sdhci_unregister_sdclk(struct device *dev)
+{
+	struct device_node *np = dev->of_node;
+
+	if (!of_find_property(np, "#clock-cells", NULL))
+		return;
+
+	of_clk_del_provider(dev->of_node);
+}
+
+/**
+ * eswin_sdhci_register_sdclk - Register the sdcardclk for a PHY to use
+ *
+ * @eswin_sdhci:    Our private data structure.
+ * @clk_xin:        Pointer to the functional clock
+ * @dev:        Pointer to our struct device.
+ *
+ * Some PHY devices need to know what the actual card clock is.  In order for
+ * them to find out, we'll provide a clock through the common clock framework
+ * for them to query.
+ *
+ * Note: without seriously re-architecting SDHCI's clock code and testing on
+ * all platforms, there's no way to create a totally beautiful clock here
+ * with all clock ops implemented.  Instead, we'll just create a clock that can
+ * be queried and set the CLK_GET_RATE_NOCACHE attribute to tell common clock
+ * framework that we're doing things behind its back.  This should be sufficient
+ * to create nice clean device tree bindings and later (if needed) we can try
+ * re-architecting SDHCI if we see some benefit to it.
+ *
+ * Return: 0 on success and error value on error
+ */
+static int eswin_sdhci_register_sdclk(struct eswin_sdhci_data *eswin_sdhci,
+				      struct clk *clk_xin, struct device *dev)
+{
+	struct device_node *np = dev->of_node;
+	u32 num_clks = 0;
+	int ret;
+
+	/* Providing a clock to the PHY is optional; no error if missing */
+	if (of_property_read_u32(np, "#clock-cells", &num_clks) < 0)
+		return 0;
+
+	ret = eswin_sdhci_register_sdcardclk(eswin_sdhci, clk_xin, dev);
+	if (ret)
+		return ret;
+
+	if (num_clks) {
+		ret = eswin_sdhci_register_sampleclk(eswin_sdhci, clk_xin, dev);
+		if (ret) {
+			eswin_sdhci_unregister_sdclk(dev);
+			return ret;
+		}
+	}
+
+	return 0;
+}
+
+static int eswin_sdhci_add_host(struct eswin_sdhci_data *eswin_sdhci)
+{
+	struct sdhci_host *host = eswin_sdhci->host;
+	struct cqhci_host *cq_host;
+	bool dma64;
+	int ret;
+
+	if (!eswin_sdhci->has_cqe)
+		return sdhci_add_host(host);
+
+	ret = sdhci_setup_host(host);
+	if (ret)
+		return ret;
+
+	cq_host = devm_kzalloc(host->mmc->parent, sizeof(*cq_host), GFP_KERNEL);
+	if (!cq_host) {
+		ret = -ENOMEM;
+		goto cleanup;
+	}
+
+	cq_host->mmio = host->ioaddr + eswin_sdhci_CQE_BASE_ADDR;
+	cq_host->ops = &eswin_sdhci_cqhci_ops;
+
+	dma64 = host->flags & SDHCI_USE_64_BIT_DMA;
+	if (dma64)
+		cq_host->caps |= CQHCI_TASK_DESC_SZ_128;
+
+	ret = cqhci_init(cq_host, host->mmc, dma64);
+	if (ret)
+		goto cleanup;
+
+	ret = __sdhci_add_host(host);
+	if (ret)
+		goto cleanup;
+
+	return 0;
+
+cleanup:
+	sdhci_cleanup_host(host);
+	return ret;
+}
+
+static int eswin_sdhci_probe(struct platform_device *pdev)
+{
+	int ret;
+	struct clk *clk_xin;
+	struct sdhci_host *host;
+	struct sdhci_pltfm_host *pltfm_host;
+	struct device *dev = &pdev->dev;
+	struct eswin_sdhci_data *eswin_sdhci;
+	const struct eswin_sdhci_of_data *data;
+	struct regmap *regmap;
+	unsigned int val = 0;
+
+	data = of_device_get_match_data(dev);
+	host = sdhci_pltfm_init(pdev, data->pdata, sizeof(*eswin_sdhci));
+	if (IS_ERR(host))
+		return PTR_ERR(host);
+
+	pltfm_host = sdhci_priv(host);
+	eswin_sdhci = sdhci_pltfm_priv(pltfm_host);
+	eswin_sdhci->host = host;
+	eswin_sdhci->clk_ops = data->clk_ops;
+
+	eswin_sdhci->core_clk_reg = ioremap(ESWIN_EMMC_CORE_CLK_REG, 0x4);
+	if (!eswin_sdhci->core_clk_reg) {
+		dev_err(dev, "ioremap core clk reg failed.\n");
+		goto err_pltfm_free;
+	}
+
+	eswin_sdhci->clk_ahb = devm_clk_get(dev, "clk_ahb");
+	if (IS_ERR(eswin_sdhci->clk_ahb)) {
+		ret = dev_err_probe(dev, PTR_ERR(eswin_sdhci->clk_ahb),
+				    "clk_ahb clock not found.\n");
+		goto err_pltfm_free;
+	}
+
+	clk_xin = devm_clk_get(dev, "clk_xin");
+	if (IS_ERR(clk_xin)) {
+		ret = dev_err_probe(dev, PTR_ERR(clk_xin),
+				    "clk_xin clock not found.\n");
+		goto err_pltfm_free;
+	}
+
+	ret = clk_prepare_enable(eswin_sdhci->clk_ahb);
+	if (ret) {
+		dev_err(dev, "Unable to enable AHB clock.\n");
+		goto err_pltfm_free;
+	}
+
+	ret = clk_prepare_enable(clk_xin);
+	if (ret) {
+		dev_err(dev, "Unable to enable SD clock.\n");
+		goto clk_dis_ahb;
+	}
+
+	ret = eswin_sdhci_reset_init(dev, eswin_sdhci);
+	if (ret < 0) {
+		dev_err(dev, "failed to reset\n");
+		goto clk_disable_all;
+	}
+
+	regmap = syscon_regmap_lookup_by_phandle(dev->of_node,
+						 "eswin,hsp_sp_csr");
+	if (IS_ERR(regmap)) {
+		dev_dbg(dev, "No hsp_sp_csr phandle specified\n");
+		goto clk_disable_all;
+	}
+
+	regmap_write(regmap, SDHCI_EMMC0_INT_STATUS, MSHC_INT_CLK_STABLE);
+	regmap_write(regmap, SDHCI_EMMC0_PWR_CLEAR, MSHC_HOST_VAL_STABLE);
+
+	if (!of_property_read_u32(dev->of_node, "delay_code", &val)) {
+		eswin_sdhci->phy.delay_code = val;
+	}
+
+	if (!of_property_read_u32(dev->of_node, "drive-impedance-ohm", &val))
+		eswin_sdhci->phy.drive_impedance =
+			eswin_convert_drive_impedance_ohm(pdev, val);
+
+	if (of_property_read_bool(dev->of_node, "enable-cmd-pullup"))
+		eswin_sdhci->phy.enable_cmd_pullup = ENABLE;
+	else
+		eswin_sdhci->phy.enable_cmd_pullup = DISABLE;
+
+	if (of_property_read_bool(dev->of_node, "enable-data-pullup"))
+		eswin_sdhci->phy.enable_data_pullup = ENABLE;
+	else
+		eswin_sdhci->phy.enable_data_pullup = DISABLE;
+
+	if (of_property_read_bool(dev->of_node, "enable-strobe-pulldown"))
+		eswin_sdhci->phy.enable_strobe_pulldown = ENABLE;
+	else
+		eswin_sdhci->phy.enable_strobe_pulldown = DISABLE;
+
+	sdhci_get_of_property(pdev);
+
+	pltfm_host->clk = clk_xin;
+
+	ret = eswin_sdhci_register_sdclk(eswin_sdhci, clk_xin, dev);
+	if (ret)
+		goto clk_disable_all;
+
+	eswin_sdhci_dt_parse_clk_phases(dev, &eswin_sdhci->clk_data);
+
+	ret = mmc_of_parse(host->mmc);
+	if (ret) {
+		ret = dev_err_probe(dev, ret, "parsing dt failed.\n");
+		goto unreg_clk;
+	}
+
+	if (of_device_is_compatible(dev->of_node, "eswin,sdhci-5.1")) {
+		host->mmc_host_ops.hs400_enhanced_strobe =
+			eswin_sdhci_hs400_enhanced_strobe;
+		eswin_sdhci->has_cqe = true;
+		host->mmc->caps2 |= MMC_CAP2_CQE;
+
+		if (!of_property_read_bool(dev->of_node, "disable-cqe-dcmd"))
+			host->mmc->caps2 |= MMC_CAP2_CQE_DCMD;
+	}
+
+	sdhci_enable_v4_mode(eswin_sdhci->host);
+
+	ret = eswin_sdhci_add_host(eswin_sdhci);
+	if (ret)
+		goto unreg_clk;
+
+	return 0;
+
+unreg_clk:
+	eswin_sdhci_unregister_sdclk(dev);
+clk_disable_all:
+	clk_disable_unprepare(clk_xin);
+clk_dis_ahb:
+	clk_disable_unprepare(eswin_sdhci->clk_ahb);
+err_pltfm_free:
+	if (eswin_sdhci->core_clk_reg)
+		iounmap(eswin_sdhci->core_clk_reg);
+	sdhci_pltfm_free(pdev);
+	return ret;
+}
+
+static void eswin_sdhci_remove(struct platform_device *pdev)
+{
+	int ret;
+	struct sdhci_host *host = platform_get_drvdata(pdev);
+	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
+	struct eswin_sdhci_data *eswin_sdhci = sdhci_pltfm_priv(pltfm_host);
+	struct clk *clk_ahb = eswin_sdhci->clk_ahb;
+	void __iomem *core_clk_reg = eswin_sdhci->core_clk_reg;
+
+	sdhci_pltfm_remove(pdev);
+
+	if (eswin_sdhci->txrx_rst) {
+		ret = reset_control_assert(eswin_sdhci->txrx_rst);
+		WARN_ON(0 != ret);
+	}
+
+	if (eswin_sdhci->phy_rst) {
+		ret = reset_control_assert(eswin_sdhci->phy_rst);
+		WARN_ON(0 != ret);
+	}
+
+	if (eswin_sdhci->prstn) {
+		ret = reset_control_assert(eswin_sdhci->prstn);
+		WARN_ON(0 != ret);
+	}
+
+	if (eswin_sdhci->arstn) {
+		ret = reset_control_assert(eswin_sdhci->arstn);
+		WARN_ON(0 != ret);
+	}
+	eswin_sdhci_unregister_sdclk(&pdev->dev);
+	clk_disable_unprepare(clk_ahb);
+	iounmap(core_clk_reg);
+}
+
+static void emmc_hard_reset(struct sdhci_host *host)
+{
+	unsigned int val;
+
+	val = sdhci_readw(host, VENDOR_EMMC_CTRL_R);
+	val |= EMMC_RST_N_OE;
+	sdhci_writew(host, val, VENDOR_EMMC_CTRL_R);
+	val &= ~EMMC_RST_N;
+	sdhci_writew(host, val, VENDOR_EMMC_CTRL_R);
+	mdelay(20);
+	val |= EMMC_RST_N;
+	sdhci_writew(host, val, VENDOR_EMMC_CTRL_R);
+}
+
+static void eswin_sdhci_shutdown(struct platform_device *pdev)
+{
+	struct sdhci_host *host = platform_get_drvdata(pdev);
+
+	if (!host)
+		return;
+
+	emmc_hard_reset(host);
+	host->ops->reset(host, SDHCI_RESET_ALL);
+	platform_set_drvdata(pdev, NULL);
+}
+
+static struct platform_driver eswin_sdhci_driver =
+{
+	.driver = {
+		.name = "sdhci-eswin",
+		.probe_type = PROBE_PREFER_ASYNCHRONOUS,
+		.of_match_table = eswin_sdhci_of_match,
+		.pm = &eswin_sdhci_dev_pm_ops,
+	},
+	.probe = eswin_sdhci_probe,
+	.remove = eswin_sdhci_remove,
+	.shutdown = eswin_sdhci_shutdown,
+};
+
+module_platform_driver(eswin_sdhci_driver);
+
+MODULE_DESCRIPTION("Driver for the ESWIN SDHCI Controller");
+MODULE_AUTHOR("Shuang Liang <liangshuang@eswincomputing.com>");
+MODULE_LICENSE("GPL v2");
diff --git a/drivers/net/ethernet/stmicro/stmmac/Kconfig b/drivers/net/ethernet/stmicro/stmmac/Kconfig
index 67fa879b1e52..4bd9ad7969e2 100644
--- a/drivers/net/ethernet/stmicro/stmmac/Kconfig
+++ b/drivers/net/ethernet/stmicro/stmmac/Kconfig
@@ -67,6 +67,14 @@ config DWMAC_ANARION
 
 	  This selects the Anarion SoC glue layer support for the stmmac driver.
 
+config DWMAC_EIC7700
+	tristate "Support for Eswin EIC77xx ethernet driver"
+	select CRC32
+	select MII
+	depends on OF && HAS_DMA
+	help
+	  Support for Eswin EIC7700 ethernet driver.
+
 config DWMAC_INGENIC
 	tristate "Ingenic MAC support"
 	default MACH_INGENIC
diff --git a/drivers/net/ethernet/stmicro/stmmac/Makefile b/drivers/net/ethernet/stmicro/stmmac/Makefile
index b591d93f8503..b15688248152 100644
--- a/drivers/net/ethernet/stmicro/stmmac/Makefile
+++ b/drivers/net/ethernet/stmicro/stmmac/Makefile
@@ -14,6 +14,7 @@ stmmac-$(CONFIG_STMMAC_SELFTESTS) += stmmac_selftests.o
 # Ordering matters. Generic driver must be last.
 obj-$(CONFIG_STMMAC_PLATFORM)	+= stmmac-platform.o
 obj-$(CONFIG_DWMAC_ANARION)	+= dwmac-anarion.o
+obj-$(CONFIG_DWMAC_EIC7700) += dwmac-eic7700.o
 obj-$(CONFIG_DWMAC_INGENIC)	+= dwmac-ingenic.o
 obj-$(CONFIG_DWMAC_IPQ806X)	+= dwmac-ipq806x.o
 obj-$(CONFIG_DWMAC_LPC18XX)	+= dwmac-lpc18xx.o
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-eic7700.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-eic7700.c
new file mode 100644
index 000000000000..62a95c28e7fa
--- /dev/null
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-eic7700.c
@@ -0,0 +1,498 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Eswin DWC Ethernet linux driver
+ */
+
+#include <linux/clk.h>
+#include <linux/clk-provider.h>
+#include <linux/device.h>
+#include <linux/gpio/consumer.h>
+#include <linux/ethtool.h>
+#include <linux/io.h>
+#include <linux/iopoll.h>
+#include <linux/ioport.h>
+#include <linux/module.h>
+#include <linux/of_device.h>
+#include <linux/of_net.h>
+#include <linux/mfd/syscon.h>
+#include <linux/platform_device.h>
+#include <linux/reset.h>
+#include <linux/stmmac.h>
+#include "stmmac_platform.h"
+#include "dwmac4.h"
+#include <linux/mfd/syscon.h>
+#include <linux/bitfield.h>
+#include <linux/regmap.h>
+#include <linux/gpio/consumer.h>
+
+/* eth_phy_ctrl_offset eth0:0x100; eth1:0x200 */
+#define ETH_TX_CLK_SEL          BIT(16)
+#define ETH_PHY_INTF_SELI       BIT(0)
+
+/* eth_axi_lp_ctrl_offset eth0:0x108; eth1:0x208 */
+#define ETH_CSYSREQ_VAL         BIT(0)
+
+/* hsp_aclk_ctrl_offset (0x148) */
+#define HSP_ACLK_CLKEN           BIT(31)
+#define HSP_ACLK_DIVSOR          (0x2 << 4)
+
+/* hsp_cfg_ctrl_offset (0x14c) */
+#define HSP_CFG_CLKEN            BIT(31)
+#define SCU_HSP_PCLK_EN          BIT(30)
+#define HSP_CFG_CTRL_REGSET      (HSP_CFG_CLKEN | SCU_HSP_PCLK_EN)
+
+/* RTL8211F PHY Configurations for LEDs */
+#define PHY_ADDR                 0
+#define PHY_PAGE_SWITCH_REG      31
+#define PHY_LED_CFG_REG          16
+#define PHY_LED_PAGE_CFG         0xd04
+
+struct dwc_qos_priv {
+	struct device *dev;
+	int dev_id;
+	struct regmap *crg_regmap;
+	struct regmap *hsp_regmap;
+	struct reset_control *rst;
+	struct clk *clk_app;
+	struct clk *clk_tx;
+	struct regmap *rgmii_sel;
+	struct gpio_desc *phy_reset;
+	struct stmmac_priv *stmpriv;
+	int phyled_cfgs[3];
+};
+
+static int dwc_eth_dwmac_config_dt(struct platform_device *pdev,
+				   struct plat_stmmacenet_data *plat_dat)
+{
+	struct device *dev = &pdev->dev;
+	u32 burst_map = 0;
+	u32 bit_index = 0;
+	u32 a_index = 0;
+
+	if (!plat_dat->axi) {
+		plat_dat->axi = kzalloc(sizeof(struct stmmac_axi), GFP_KERNEL);
+
+		if (!plat_dat->axi)
+			return -ENOMEM;
+	}
+
+	plat_dat->axi->axi_lpi_en = device_property_read_bool(dev,
+							      "snps,en-lpi");
+	if (device_property_read_u32(dev, "snps,write-requests",
+				     &plat_dat->axi->axi_wr_osr_lmt)) {
+		/**
+		 * Since the register has a reset value of 1, if property
+		 * is missing, default to 1.
+		 */
+		plat_dat->axi->axi_wr_osr_lmt = 1;
+	} else {
+		/**
+		 * If property exists, to keep the behavior from dwc_eth_qos,
+		 * subtract one after parsing.
+		 */
+		plat_dat->axi->axi_wr_osr_lmt--;
+	}
+
+	if (device_property_read_u32(dev, "snps,read-requests",
+				     &plat_dat->axi->axi_rd_osr_lmt)) {
+		/**
+		 * Since the register has a reset value of 1, if property
+		 * is missing, default to 1.
+		 */
+		plat_dat->axi->axi_rd_osr_lmt = 1;
+	} else {
+		/**
+		 * If property exists, to keep the behavior from dwc_eth_qos,
+		 * subtract one after parsing.
+		 */
+		plat_dat->axi->axi_rd_osr_lmt--;
+	}
+	device_property_read_u32(dev, "snps,burst-map", &burst_map);
+
+	/* converts burst-map bitmask to burst array */
+	for (bit_index = 0; bit_index < 7; bit_index++) {
+		if (burst_map & (1 << bit_index)) {
+			switch (bit_index) {
+			case 0:
+			plat_dat->axi->axi_blen[a_index] = 4; break;
+			case 1:
+			plat_dat->axi->axi_blen[a_index] = 8; break;
+			case 2:
+			plat_dat->axi->axi_blen[a_index] = 16; break;
+			case 3:
+			plat_dat->axi->axi_blen[a_index] = 32; break;
+			case 4:
+			plat_dat->axi->axi_blen[a_index] = 64; break;
+			case 5:
+			plat_dat->axi->axi_blen[a_index] = 128; break;
+			case 6:
+			plat_dat->axi->axi_blen[a_index] = 256; break;
+			default:
+			break;
+			}
+			a_index++;
+		}
+	}
+
+	/* dwc-qos needs GMAC4, AAL, TSO and PMT */
+	plat_dat->has_gmac4 = 1;
+	plat_dat->dma_cfg->aal = 1;
+	plat_dat->flags |= STMMAC_FLAG_TSO_EN;
+	plat_dat->pmt = 1;
+
+	return 0;
+}
+
+static void dwc_qos_fix_speed(void *priv, int speed, unsigned int mode)
+{
+	unsigned long rate = 125000000;
+	int err, data = 0;
+	struct dwc_qos_priv *dwc_priv = (struct dwc_qos_priv *)priv;
+
+	switch (speed) {
+	case SPEED_1000:
+		rate = 125000000;
+
+		if (dwc_priv->dev_id == 0) {
+			regmap_write(dwc_priv->hsp_regmap, 0x118, 0x800c8023);
+			regmap_write(dwc_priv->hsp_regmap, 0x11c, 0x0c0c0c0c);
+			regmap_write(dwc_priv->hsp_regmap, 0x114, 0x23232323);
+		} else {
+			regmap_write(dwc_priv->hsp_regmap, 0x218, 0x80268025);
+			regmap_write(dwc_priv->hsp_regmap, 0x21c, 0x26262626);
+			regmap_write(dwc_priv->hsp_regmap, 0x214, 0x25252525);
+		}
+
+		if (dwc_priv->stmpriv) {
+			data = mdiobus_read(dwc_priv->stmpriv->mii, PHY_ADDR, PHY_PAGE_SWITCH_REG);
+			mdiobus_write(dwc_priv->stmpriv->mii, PHY_ADDR, PHY_PAGE_SWITCH_REG, PHY_LED_PAGE_CFG);
+			mdiobus_write(dwc_priv->stmpriv->mii, PHY_ADDR, PHY_LED_CFG_REG, dwc_priv->phyled_cfgs[0]);
+			mdiobus_write(dwc_priv->stmpriv->mii, PHY_ADDR, PHY_PAGE_SWITCH_REG, data);
+		}
+
+		break;
+	case SPEED_100:
+		rate = 25000000;
+
+		if (dwc_priv->dev_id == 0) {
+			regmap_write(dwc_priv->hsp_regmap, 0x118, 0x803f8050);
+			regmap_write(dwc_priv->hsp_regmap, 0x11c, 0x3f3f3f3f);
+			regmap_write(dwc_priv->hsp_regmap, 0x114, 0x50505050);
+		} else {
+			regmap_write(dwc_priv->hsp_regmap, 0x218, 0x80588048);
+			regmap_write(dwc_priv->hsp_regmap, 0x21c, 0x58585858);
+			regmap_write(dwc_priv->hsp_regmap, 0x214, 0x48484848);
+		}
+
+		if (dwc_priv->stmpriv) {
+			data = mdiobus_read(dwc_priv->stmpriv->mii, PHY_ADDR, PHY_PAGE_SWITCH_REG);
+			mdiobus_write(dwc_priv->stmpriv->mii, PHY_ADDR, PHY_PAGE_SWITCH_REG, PHY_LED_PAGE_CFG);
+			mdiobus_write(dwc_priv->stmpriv->mii, PHY_ADDR, PHY_LED_CFG_REG, dwc_priv->phyled_cfgs[1]);
+			mdiobus_write(dwc_priv->stmpriv->mii, PHY_ADDR, PHY_PAGE_SWITCH_REG, data);
+		}
+
+		break;
+	case SPEED_10:
+		rate = 2500000;
+
+		if (dwc_priv->dev_id == 0) {
+			regmap_write(dwc_priv->hsp_regmap, 0x118, 0x0);
+			regmap_write(dwc_priv->hsp_regmap, 0x11c, 0x0);
+			regmap_write(dwc_priv->hsp_regmap, 0x114, 0x0);
+		} else {
+			regmap_write(dwc_priv->hsp_regmap, 0x218, 0x0);
+			regmap_write(dwc_priv->hsp_regmap, 0x21c, 0x0);
+			regmap_write(dwc_priv->hsp_regmap, 0x214, 0x0);
+		}
+
+		if (dwc_priv->stmpriv) {
+			data = mdiobus_read(dwc_priv->stmpriv->mii, PHY_ADDR, PHY_PAGE_SWITCH_REG);
+			mdiobus_write(dwc_priv->stmpriv->mii, PHY_ADDR, PHY_PAGE_SWITCH_REG, PHY_LED_PAGE_CFG);
+			mdiobus_write(dwc_priv->stmpriv->mii, PHY_ADDR, PHY_LED_CFG_REG, dwc_priv->phyled_cfgs[2]);
+			mdiobus_write(dwc_priv->stmpriv->mii, PHY_ADDR, PHY_PAGE_SWITCH_REG, data);
+		}
+
+		break;
+	default:
+		dev_err(dwc_priv->dev, "invalid speed %d\n", speed);
+		break;
+	}
+
+	err = clk_set_rate(dwc_priv->clk_tx, rate);
+	if (err < 0)
+	{
+		dev_err(dwc_priv->dev, "failed to set TX rate: %d\n", err);
+	}
+}
+
+static int dwc_qos_probe(struct platform_device *pdev,
+			 struct plat_stmmacenet_data *plat_dat,
+			 struct stmmac_resources *stmmac_res)
+{
+	struct dwc_qos_priv *dwc_priv;
+	int ret;
+	int err;
+	u32 hsp_aclk_ctrl_offset;
+	u32 hsp_aclk_ctrl_regset;
+	u32 hsp_cfg_ctrl_offset;
+	u32 eth_axi_lp_ctrl_offset;
+	u32 eth_phy_ctrl_offset;
+	u32 eth_phy_ctrl_regset;
+	u32 rgmiisel_offset;
+	u32 rgmiisel_regset;
+
+	dwc_priv = devm_kzalloc(&pdev->dev, sizeof(*dwc_priv), GFP_KERNEL);
+	if (!dwc_priv)
+		return -ENOMEM;
+
+	if (device_property_read_u32(&pdev->dev, "id", &dwc_priv->dev_id)) {
+		dev_err(&pdev->dev, "Can not read device id!\n");
+		return -EINVAL;
+	}
+
+	dwc_priv->dev = &pdev->dev;
+	dwc_priv->phy_reset = devm_gpiod_get(&pdev->dev, "rst", GPIOD_OUT_LOW);
+	if (IS_ERR(dwc_priv->phy_reset)) {
+		dev_err(&pdev->dev, "Reset gpio not specified\n");
+		return -EINVAL;
+	}
+
+	gpiod_set_value(dwc_priv->phy_reset, 0);
+
+	dwc_priv->rgmii_sel = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, "eswin,rgmiisel");
+	if (IS_ERR(dwc_priv->rgmii_sel)){
+		dev_dbg(&pdev->dev, "rgmiisel not specified\n");
+		return -EINVAL;
+	}
+
+	ret = of_property_read_u32_index(pdev->dev.of_node, "eswin,led-cfgs", 0, &dwc_priv->phyled_cfgs[0]);
+	if (ret) {
+		dev_warn(&pdev->dev, "can't get led cfgs for 1Gbps mode (%d)\n", ret);
+	}
+
+	ret = of_property_read_u32_index(pdev->dev.of_node, "eswin,led-cfgs", 1, &dwc_priv->phyled_cfgs[1]);
+	if (ret) {
+		dev_warn(&pdev->dev, "can't get led cfgs for 100Mbps mode (%d)\n", ret);
+	}
+
+	ret = of_property_read_u32_index(pdev->dev.of_node, "eswin,led-cfgs", 2, &dwc_priv->phyled_cfgs[2]);
+	if (ret) {
+		dev_warn(&pdev->dev, "can't get led cfgs for 10Mbps mode (%d)\n", ret);
+	}
+
+	ret = of_property_read_u32_index(pdev->dev.of_node, "eswin,rgmiisel", 1, &rgmiisel_offset);
+	if (ret) {
+		dev_err(&pdev->dev, "can't get rgmiisel_offset (%d)\n", ret);
+		return ret;
+	}
+
+	ret = of_property_read_u32_index(pdev->dev.of_node, "eswin,rgmiisel", 2, &rgmiisel_regset);
+	if (ret) {
+		dev_err(&pdev->dev, "can't get rgmiisel_regset (%d)\n", ret);
+		return ret;
+	}
+
+	regmap_write(dwc_priv->rgmii_sel, rgmiisel_offset, rgmiisel_regset);
+
+	dwc_priv->crg_regmap = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, "eswin,syscrg_csr");
+	if (IS_ERR(dwc_priv->crg_regmap)){
+		dev_dbg(&pdev->dev, "No syscrg_csr phandle specified\n");
+		return 0;
+	}
+
+	ret = of_property_read_u32_index(pdev->dev.of_node, "eswin,syscrg_csr", 1,
+                                    &hsp_aclk_ctrl_offset);
+	if (ret) {
+		dev_err(&pdev->dev, "can't get hsp_aclk_ctrl_offset (%d)\n", ret);
+		return ret;
+	}
+	regmap_read(dwc_priv->crg_regmap, hsp_aclk_ctrl_offset, &hsp_aclk_ctrl_regset);
+	hsp_aclk_ctrl_regset |= (HSP_ACLK_CLKEN | HSP_ACLK_DIVSOR);
+	regmap_write(dwc_priv->crg_regmap, hsp_aclk_ctrl_offset, hsp_aclk_ctrl_regset);
+
+	ret = of_property_read_u32_index(pdev->dev.of_node, "eswin,syscrg_csr", 2,
+                                    &hsp_cfg_ctrl_offset);
+	if (ret) {
+		dev_err(&pdev->dev, "can't get hsp_cfg_ctrl_offset (%d)\n", ret);
+		return ret;
+	}
+	regmap_write(dwc_priv->crg_regmap, hsp_cfg_ctrl_offset, HSP_CFG_CTRL_REGSET);
+
+	dwc_priv->hsp_regmap = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, "eswin,hsp_sp_csr");
+	if (IS_ERR(dwc_priv->hsp_regmap)){
+		dev_dbg(&pdev->dev, "No hsp_sp_csr phandle specified\n");
+		return 0;
+	}
+
+	ret = of_property_read_u32_index(pdev->dev.of_node, "eswin,hsp_sp_csr", 2,
+                                    &eth_phy_ctrl_offset);
+	if (ret) {
+		dev_err(&pdev->dev, "can't get eth_phy_ctrl_offset (%d)\n", ret);
+		return ret;
+	}
+	regmap_read(dwc_priv->hsp_regmap, eth_phy_ctrl_offset, &eth_phy_ctrl_regset);
+	eth_phy_ctrl_regset |= (ETH_TX_CLK_SEL | ETH_PHY_INTF_SELI);
+	regmap_write(dwc_priv->hsp_regmap, eth_phy_ctrl_offset, eth_phy_ctrl_regset);
+
+	ret = of_property_read_u32_index(pdev->dev.of_node, "eswin,hsp_sp_csr", 3,
+                                    &eth_axi_lp_ctrl_offset);
+	if (ret) {
+		dev_err(&pdev->dev, "can't get eth_axi_lp_ctrl_offset (%d)\n", ret);
+		return ret;
+	}
+	regmap_write(dwc_priv->hsp_regmap, eth_axi_lp_ctrl_offset, ETH_CSYSREQ_VAL);
+
+	dwc_priv->clk_app = devm_clk_get(&pdev->dev, "app");
+	if (IS_ERR(dwc_priv->clk_app)) {
+		dev_err(&pdev->dev, "app clock not found.\n");
+		return PTR_ERR(dwc_priv->clk_app);
+	}
+
+	err = clk_prepare_enable(dwc_priv->clk_app);
+	if (err < 0) {
+		dev_err(&pdev->dev, "failed to enable app clock: %d\n",
+			err);
+		return err;
+	}
+
+	dwc_priv->clk_tx = devm_clk_get(&pdev->dev, "tx");
+	if (IS_ERR(plat_dat->pclk)) {
+		dev_err(&pdev->dev, "tx clock not found.\n");
+		return PTR_ERR(dwc_priv->clk_tx);
+	}
+
+	err = clk_prepare_enable(dwc_priv->clk_tx);
+	if (err < 0) {
+		dev_err(&pdev->dev, "failed to enable tx clock: %d\n",
+            err);
+		return err;
+	}
+	dwc_priv->rst = devm_reset_control_get_optional_exclusive(&pdev->dev, "ethrst");
+	if (IS_ERR(dwc_priv->rst)) {
+		return PTR_ERR(dwc_priv->rst);
+	}
+
+	ret = reset_control_assert(dwc_priv->rst);
+	WARN_ON(0 != ret);
+	ret = reset_control_deassert(dwc_priv->rst);
+	WARN_ON(0 != ret);
+
+	plat_dat->fix_mac_speed = dwc_qos_fix_speed;
+	plat_dat->bsp_priv = dwc_priv;
+	plat_dat->phy_addr = PHY_ADDR;
+
+	return 0;
+}
+
+static void dwc_qos_remove(struct platform_device *pdev)
+{
+	struct dwc_qos_priv *dwc_priv = get_stmmac_bsp_priv(&pdev->dev);
+
+	reset_control_assert(dwc_priv->rst);
+	clk_disable_unprepare(dwc_priv->clk_tx);
+	clk_disable_unprepare(dwc_priv->clk_app);
+
+	devm_gpiod_put(&pdev->dev, dwc_priv->phy_reset);
+}
+
+struct dwc_eth_dwmac_data {
+	int (*probe)(struct platform_device *pdev,
+		     struct plat_stmmacenet_data *data,
+		     struct stmmac_resources *res);
+	void (*remove)(struct platform_device *pdev);
+};
+
+static const struct dwc_eth_dwmac_data dwc_qos_data = {
+	.probe = dwc_qos_probe,
+	.remove = dwc_qos_remove,
+};
+
+static int dwc_eth_dwmac_probe(struct platform_device *pdev)
+{
+	const struct dwc_eth_dwmac_data *data;
+	struct plat_stmmacenet_data *plat_dat;
+	struct stmmac_resources stmmac_res;
+	struct net_device *ndev = NULL;
+	struct stmmac_priv *stmpriv = NULL;
+	struct dwc_qos_priv *dwc_priv = NULL;
+	int ret;
+
+	data = device_get_match_data(&pdev->dev);
+
+	memset(&stmmac_res, 0, sizeof(struct stmmac_resources));
+
+	/**
+	 * Since stmmac_platform supports name IRQ only, basic platform
+	 * resource initialization is done in the glue logic.
+	 */
+	stmmac_res.irq = platform_get_irq(pdev, 0);
+	if (stmmac_res.irq < 0)
+		return stmmac_res.irq;
+	stmmac_res.wol_irq = stmmac_res.irq;
+	stmmac_res.addr = devm_platform_ioremap_resource(pdev, 0);
+	if (IS_ERR(stmmac_res.addr))
+		return PTR_ERR(stmmac_res.addr);
+
+	plat_dat = devm_stmmac_probe_config_dt(pdev, stmmac_res.mac);
+	if (IS_ERR(plat_dat))
+		return PTR_ERR(plat_dat);
+
+	ret = data->probe(pdev, plat_dat, &stmmac_res);
+	if (ret < 0) {
+		if (ret != -EPROBE_DEFER)
+			dev_err(&pdev->dev, "failed to probe subdriver: %d\n",
+				ret);
+		return ret;
+	}
+
+	ret = dwc_eth_dwmac_config_dt(pdev, plat_dat);
+	if (ret)
+		goto remove;
+
+	ret = stmmac_dvr_probe(&pdev->dev, plat_dat, &stmmac_res);
+	if (ret)
+		goto remove;
+
+	ndev = dev_get_drvdata(&pdev->dev);
+	stmpriv = netdev_priv(ndev);
+	dwc_priv = (struct dwc_qos_priv *)plat_dat->bsp_priv;
+	dwc_priv->stmpriv = stmpriv;
+
+	return ret;
+
+remove:
+	data->remove(pdev);
+	return ret;
+}
+
+static void dwc_eth_dwmac_remove(struct platform_device *pdev)
+{
+	const struct dwc_eth_dwmac_data *data;
+
+	data = device_get_match_data(&pdev->dev);
+
+	stmmac_dvr_remove(&pdev->dev);
+
+	data->remove(pdev);
+}
+
+static const struct of_device_id dwc_eth_dwmac_match[] = {
+	{ .compatible = "eswin,eic7700-qos-eth", .data = &dwc_qos_data },
+	{ }
+};
+MODULE_DEVICE_TABLE(of, dwc_eth_dwmac_match);
+
+static struct platform_driver eic7700_eth_dwmac_driver = {
+	.probe  = dwc_eth_dwmac_probe,
+	.remove = dwc_eth_dwmac_remove,
+	.driver = {
+		.name           = "eic7700-eth-dwmac",
+		.pm             = &stmmac_pltfr_pm_ops,
+		.of_match_table = dwc_eth_dwmac_match,
+	},
+};
+module_platform_driver(eic7700_eth_dwmac_driver);
+
+MODULE_AUTHOR("Eswin");
+MODULE_DESCRIPTION("Eswin eic7700 qos ethernet driver");
+MODULE_LICENSE("GPL v2");
diff --git a/drivers/pci/controller/dwc/Kconfig b/drivers/pci/controller/dwc/Kconfig
index d9f0386396ed..edc934122f5a 100644
--- a/drivers/pci/controller/dwc/Kconfig
+++ b/drivers/pci/controller/dwc/Kconfig
@@ -480,4 +480,12 @@ config PCIE_VISCONTI_HOST
 	  Say Y here if you want PCIe controller support on Toshiba Visconti SoC.
 	  This driver supports TMPV7708 SoC.
 
+config PCIE_ESWIN
+	tristate "ESWIN PCIe host controller"
+	depends on PCI_MSI
+	depends on ARCH_SIFIVE || COMPILE_TEST
+	select PCIE_DW_HOST
+	help
+	  Say Y here if you want PCIe controller support for the ESWIN.
+
 endmenu
diff --git a/drivers/pci/controller/dwc/Makefile b/drivers/pci/controller/dwc/Makefile
index 908cb7f345db..eba027346411 100644
--- a/drivers/pci/controller/dwc/Makefile
+++ b/drivers/pci/controller/dwc/Makefile
@@ -30,6 +30,7 @@ obj-$(CONFIG_PCIE_UNIPHIER) += pcie-uniphier.o
 obj-$(CONFIG_PCIE_UNIPHIER_EP) += pcie-uniphier-ep.o
 obj-$(CONFIG_PCIE_VISCONTI_HOST) += pcie-visconti.o
 obj-$(CONFIG_PCIE_RCAR_GEN4) += pcie-rcar-gen4.o
+obj-$(CONFIG_PCIE_ESWIN) += pcie-eswin.o
 
 # The following drivers are for devices that use the generic ACPI
 # pci_root.c driver but don't support standard ECAM config access.
diff --git a/drivers/pci/controller/dwc/pcie-eswin.c b/drivers/pci/controller/dwc/pcie-eswin.c
new file mode 100644
index 000000000000..853763ae9223
--- /dev/null
+++ b/drivers/pci/controller/dwc/pcie-eswin.c
@@ -0,0 +1,369 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * ESWIN PCIe root complex driver
+ *
+ * Copyright 2024, Beijing ESWIN Computing Technology Co., Ltd.. All rights reserved.
+ * SPDX-License-Identifier: GPL-2.0
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, version 2.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <https://www.gnu.org/licenses/>.
+ *
+ * Authors: Yu Ning <ningyu@eswincomputing.com>
+ */
+
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/gpio.h>
+#include <linux/gpio/consumer.h>
+#include <linux/kernel.h>
+#include <linux/mfd/syscon.h>
+#include <linux/module.h>
+#include <linux/pci.h>
+#include <linux/platform_device.h>
+#include <linux/regulator/consumer.h>
+#include <linux/resource.h>
+#include <linux/types.h>
+#include <linux/interrupt.h>
+#include <linux/iopoll.h>
+#include <linux/reset.h>
+#include <linux/gpio/consumer.h>
+#include <linux/property.h>
+#include "pcie-designware.h"
+
+struct eswin_pcie {
+	struct dw_pcie pci;
+	void __iomem *mgmt_base;
+	struct gpio_desc *reset;
+	struct clk *pcie_aux;
+	struct clk *pcie_cfg;
+	struct clk *pcie_cr;
+	struct clk *pcie_aclk;
+	struct reset_control *powerup_rst;
+	struct reset_control *cfg_rst;
+	struct reset_control *perst;
+};
+
+#define PCIE_PM_SEL_AUX_CLK		BIT(16)
+#define PCIEMGMT_APP_HOLD_PHY_RST	BIT(6)
+#define PCIEMGMT_APP_LTSSM_ENABLE	BIT(5)
+#define PCIEMGMT_DEVICE_TYPE_MASK	0xf
+
+#define PCIEMGMT_CTRL0_OFFSET	0x0
+#define PCIEMGMT_STATUS0_OFFSET	0x100
+
+#define PCIE_TYPE_DEV_VEND_ID	0x0
+#define PCIE_DSP_PF0_MSI_CAP	0x50
+#define PCIE_NEXT_CAP_PTR		0x70
+#define DEVICE_CONTROL_DEVICE_STATUS	0x78
+
+#define PCIE_MSI_MULTIPLE_MSG_32	(0x5<<17)
+#define PCIE_MSI_MULTIPLE_MSG_MASK	(0x7<<17)
+
+#define PCIEMGMT_LINKUP_STATE_VALIDATE  ((0x11<<2)|0x3)
+#define PCIEMGMT_LINKUP_STATE_MASK      0xff
+
+static void eswin_pcie_shutdown(struct platform_device *pdev)
+{
+	struct eswin_pcie *pcie = platform_get_drvdata(pdev);
+
+	/* Bring down link, so bootloader gets clean state in case of reboot */
+	reset_control_assert(pcie->perst);
+}
+
+static int eswin_pcie_start_link(struct dw_pcie *pci)
+{
+	struct device *dev = pci->dev;
+	struct eswin_pcie *pcie = dev_get_drvdata(dev);
+	u32 val;
+
+	/* Enable LTSSM */
+	val = readl_relaxed(pcie->mgmt_base + PCIEMGMT_CTRL0_OFFSET);
+	val |= PCIEMGMT_APP_LTSSM_ENABLE;
+	writel_relaxed(val, pcie->mgmt_base + PCIEMGMT_CTRL0_OFFSET);
+	return 0;
+}
+
+static bool eswin_pcie_link_up(struct dw_pcie *pci)
+{
+	struct device *dev = pci->dev;
+	struct eswin_pcie *pcie = dev_get_drvdata(dev);
+	u32 val;
+
+	val = readl_relaxed(pcie->mgmt_base + PCIEMGMT_STATUS0_OFFSET);
+	if ((val & PCIEMGMT_LINKUP_STATE_MASK) == PCIEMGMT_LINKUP_STATE_VALIDATE)
+		return true;
+	else
+		return false;
+}
+
+static int eswin_pcie_clk_enable(struct eswin_pcie *pcie)
+{
+	int ret;
+
+	ret = clk_prepare_enable(pcie->pcie_cr);
+	if (ret) {
+		pr_err("PCIe: failed to enable cr clk: %d\n", ret);
+		return ret;
+	}
+
+	ret = clk_prepare_enable(pcie->pcie_aclk);
+	if (ret) {
+		pr_err("PCIe: failed to enable aclk: %d\n", ret);
+		return ret;
+	}
+
+	ret = clk_prepare_enable(pcie->pcie_cfg);
+	if (ret) {
+		pr_err("PCIe: failed to enable cfg_clk: %d\n", ret);
+		return ret;
+	}
+
+	ret = clk_prepare_enable(pcie->pcie_aux);
+	if (ret) {
+		pr_err("PCIe: failed to enable aux_clk: %d\n", ret);
+		return ret;
+	}
+
+	return 0;
+}
+
+static int eswin_pcie_clk_disable(struct eswin_pcie *eswin_pcie)
+{
+	clk_disable_unprepare(eswin_pcie->pcie_aux);
+	clk_disable_unprepare(eswin_pcie->pcie_cfg);
+	clk_disable_unprepare(eswin_pcie->pcie_cr);
+	clk_disable_unprepare(eswin_pcie->pcie_aclk);
+
+	return 0;
+}
+
+static int eswin_pcie_power_on(struct eswin_pcie *pcie)
+{
+	int ret = 0;
+
+	/* pciet_cfg_rstn */
+	ret = reset_control_reset(pcie->cfg_rst);
+	WARN_ON(0 != ret);
+
+	/* pciet_powerup_rstn */
+	ret = reset_control_reset(pcie->powerup_rst);
+	WARN_ON(0 != ret);
+
+	return ret;
+}
+
+static int eswin_pcie_power_off(struct eswin_pcie *eswin_pcie)
+{
+	reset_control_assert(eswin_pcie->perst);
+
+	reset_control_assert(eswin_pcie->powerup_rst);
+
+	reset_control_assert(eswin_pcie->cfg_rst);
+
+	return 0;
+}
+
+static int eswin_evb_socket_power_on(struct device *dev)
+{
+	int err_desc=0;
+	struct gpio_desc *gpio;
+	gpio = devm_gpiod_get(dev, "pci-socket", GPIOD_OUT_LOW);
+	err_desc = IS_ERR(gpio);
+
+	if (err_desc) {
+		pr_debug("No power control gpio found, maybe not needed\n");
+		return 0;
+	}
+
+	gpiod_set_value(gpio,1);
+
+	return err_desc;
+}
+
+static int eswin_pcie_host_init(struct dw_pcie_rp *pp)
+{
+	struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
+	struct eswin_pcie *pcie = dev_get_drvdata(pci->dev);
+	int ret;
+	u32 val;
+
+	/* pciet_aux_clken, pcie_cfg_clken */
+	ret = eswin_pcie_clk_enable(pcie);
+	if (ret)
+		return ret;
+
+	ret = eswin_pcie_power_on(pcie);
+	if (ret)
+		return ret;
+
+	/* set device type : rc */
+	val = readl_relaxed(pcie->mgmt_base + PCIEMGMT_CTRL0_OFFSET);
+	val &= 0xfffffff0;
+	writel_relaxed(val|0x4, pcie->mgmt_base + PCIEMGMT_CTRL0_OFFSET);
+
+	ret = reset_control_assert(pcie->perst);
+	WARN_ON(0 != ret);
+
+	eswin_evb_socket_power_on(pcie->pci.dev);
+	msleep(100);
+	ret = reset_control_deassert(pcie->perst);
+	WARN_ON(0 != ret);
+
+	/* app_hold_phy_rst */
+	val = readl_relaxed(pcie->mgmt_base + PCIEMGMT_CTRL0_OFFSET);
+	val &= ~(0x40);
+	writel_relaxed(val, pcie->mgmt_base + PCIEMGMT_CTRL0_OFFSET);
+
+	/* wait pm_sel_aux_clk to 0 */
+	while (1) {
+		val = readl_relaxed(pcie->mgmt_base + PCIEMGMT_STATUS0_OFFSET);
+		if (!(val & PCIE_PM_SEL_AUX_CLK)) {
+			break;
+		}
+		msleep(1);
+	}
+
+	/* config eswin vendor id and eic7700 device id */
+	dw_pcie_writel_dbi(pci, PCIE_TYPE_DEV_VEND_ID, 0x20301fe1);
+
+	/* lane fix config, real driver NOT need, default x4 */
+	val = dw_pcie_readl_dbi(pci, PCIE_PORT_MULTI_LANE_CTRL);
+	val &= 0xffffff80;
+	val |= 0x44;
+	dw_pcie_writel_dbi(pci, PCIE_PORT_MULTI_LANE_CTRL, val);
+
+	val = dw_pcie_readl_dbi(pci, DEVICE_CONTROL_DEVICE_STATUS);
+	val &= ~(0x7<<5);
+	val |= (0x2<<5);
+	dw_pcie_writel_dbi(pci, DEVICE_CONTROL_DEVICE_STATUS, val);
+
+	/*  config support 32 msi vectors */
+	val = dw_pcie_readl_dbi(pci, PCIE_DSP_PF0_MSI_CAP);
+	val &= ~PCIE_MSI_MULTIPLE_MSG_MASK;
+	val |= PCIE_MSI_MULTIPLE_MSG_32;
+	dw_pcie_writel_dbi(pci, PCIE_DSP_PF0_MSI_CAP, val);
+
+	/* disable msix cap */
+	val = dw_pcie_readl_dbi(pci, PCIE_NEXT_CAP_PTR);
+	val &= 0xffff00ff;
+	dw_pcie_writel_dbi(pci, PCIE_NEXT_CAP_PTR, val);
+
+	return 0;
+}
+
+static const struct dw_pcie_host_ops eswin_pcie_host_ops = {
+	.init = eswin_pcie_host_init,
+};
+
+static const struct dw_pcie_ops dw_pcie_ops = {
+	.start_link = eswin_pcie_start_link,
+	.link_up = eswin_pcie_link_up,
+};
+
+static void __exit eswin_pcie_remove(struct platform_device *pdev)
+{
+	struct eswin_pcie *pcie = platform_get_drvdata(pdev);
+
+	dw_pcie_host_deinit(&pcie->pci.pp);
+
+	eswin_pcie_power_off(pcie);
+	eswin_pcie_clk_disable(pcie);
+}
+
+static int eswin_pcie_probe(struct platform_device *pdev)
+{
+	struct device *dev = &pdev->dev;
+	struct dw_pcie *pci;
+	struct eswin_pcie *pcie;
+
+	pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL);
+	if (!pcie)
+		return -ENOMEM;
+	pci = &pcie->pci;
+	pci->dev = dev;
+	pci->ops = &dw_pcie_ops;
+	pci->pp.ops = &eswin_pcie_host_ops;
+
+	/* SiFive specific region: mgmt */
+	pcie->mgmt_base = devm_platform_ioremap_resource_byname(pdev, "mgmt");
+	if (IS_ERR(pcie->mgmt_base))
+		return PTR_ERR(pcie->mgmt_base);
+
+	/* Fetch clocks */
+	pcie->pcie_aux = devm_clk_get(dev, "pcie_aux_clk");
+	if (IS_ERR(pcie->pcie_aux)) {
+		dev_err(dev, "pcie_aux clock source missing or invalid\n");
+		return PTR_ERR(pcie->pcie_aux);
+	}
+
+	pcie->pcie_cfg = devm_clk_get(dev, "pcie_cfg_clk");
+	if (IS_ERR(pcie->pcie_cfg)) {
+		dev_err(dev, "pcie_cfg_clk clock source missing or invalid\n");
+		return PTR_ERR(pcie->pcie_cfg);
+	}
+
+	pcie->pcie_cr = devm_clk_get(dev, "pcie_cr_clk");
+	if (IS_ERR(pcie->pcie_cr)) {
+		dev_err(dev, "pcie_cr_clk clock source missing or invalid\n");
+		return PTR_ERR(pcie->pcie_cr);
+	}
+
+	pcie->pcie_aclk = devm_clk_get(dev, "pcie_aclk");
+
+	if (IS_ERR(pcie->pcie_aclk)) {
+		dev_err(dev, "pcie_aclk clock source missing or invalid\n");
+		return PTR_ERR(pcie->pcie_aclk);
+	}
+
+	/* Fetch reset */
+	pcie->powerup_rst = devm_reset_control_get_optional(&pdev->dev, "pcie_powerup");
+	if (IS_ERR_OR_NULL(pcie->powerup_rst)) {
+		dev_err_probe(dev, PTR_ERR(pcie->powerup_rst), "unable to get powerup reset\n");
+	}
+
+	pcie->cfg_rst = devm_reset_control_get_optional(&pdev->dev, "pcie_cfg");
+	if (IS_ERR_OR_NULL(pcie->cfg_rst)) {
+		dev_err_probe(dev, PTR_ERR(pcie->cfg_rst), "unable to get cfg reset\n");
+	}
+
+	pcie->perst = devm_reset_control_get_optional(&pdev->dev, "pcie_pwren");
+	if (IS_ERR_OR_NULL(pcie->perst)) {
+		dev_err_probe(dev, PTR_ERR(pcie->perst), "unable to get perst\n");
+	}
+
+	platform_set_drvdata(pdev, pcie);
+
+	return dw_pcie_host_init(&pci->pp);
+}
+
+static const struct of_device_id eswin_pcie_of_match[] = {
+	{ .compatible = "eswin,eic7700-pcie", },
+	{},
+};
+
+static struct platform_driver eswin_pcie_driver = {
+	.driver = {
+		   .name = "eswin-pcie",
+		   .of_match_table = eswin_pcie_of_match,
+		   .suppress_bind_attrs = true,
+	},
+	.probe = eswin_pcie_probe,
+	.remove = __exit_p(eswin_pcie_remove),
+	.shutdown = eswin_pcie_shutdown,
+};
+
+module_platform_driver(eswin_pcie_driver);
+
+MODULE_DEVICE_TABLE(of, eswin_pcie_of_match);
+MODULE_DESCRIPTION("PCIe host controller driver for ESWIN EIC7700 SoCs");
+MODULE_AUTHOR("Ning Yu <ningyu@eswincomputing.com>");
+MODULE_LICENSE("GPL v2");
diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
index 33db9104df17..ce49f69dcd93 100644
--- a/drivers/pinctrl/Kconfig
+++ b/drivers/pinctrl/Kconfig
@@ -232,6 +232,16 @@ config PINCTRL_EQUILIBRIUM
 	  desired pin functions, configure GPIO attributes for LGM SoC pins.
 	  Pin muxing and pin config settings are retrieved from device tree.
 
+config PINCTRL_EIC7700
+	tristate "EIC7700 PINCTRL driver"
+	select GENERIC_PINCONF
+	select PINMUX
+	select PINCONF
+	select GENERIC_PINCTRL_GROUPS
+	select GENERIC_PINMUX_FUNCTIONS
+	help
+	  say Y here to add pinctrl eic7700 driver
+
 config PINCTRL_EYEQ5
 	bool "Mobileye EyeQ5 pinctrl driver"
 	depends on OF
diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile
index ac27e88677d1..a74c74e95464 100644
--- a/drivers/pinctrl/Makefile
+++ b/drivers/pinctrl/Makefile
@@ -25,6 +25,7 @@ obj-$(CONFIG_PINCTRL_DA9062)	+= pinctrl-da9062.o
 obj-$(CONFIG_PINCTRL_DIGICOLOR)	+= pinctrl-digicolor.o
 obj-$(CONFIG_PINCTRL_EQUILIBRIUM)   += pinctrl-equilibrium.o
 obj-$(CONFIG_PINCTRL_EP93XX)	+= pinctrl-ep93xx.o
+obj-$(CONFIG_PINCTRL_EIC7700)	+= pinctrl-eic7700.o
 obj-$(CONFIG_PINCTRL_EYEQ5)	+= pinctrl-eyeq5.o
 obj-$(CONFIG_PINCTRL_GEMINI)	+= pinctrl-gemini.o
 obj-$(CONFIG_PINCTRL_INGENIC)	+= pinctrl-ingenic.o
diff --git a/drivers/pinctrl/pinctrl-eic7700.c b/drivers/pinctrl/pinctrl-eic7700.c
new file mode 100644
index 000000000000..21a31d5cb7fa
--- /dev/null
+++ b/drivers/pinctrl/pinctrl-eic7700.c
@@ -0,0 +1,1359 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * ESWIN Pinctrl Controller Platform Device Driver
+ *
+ * Copyright 2024, Beijing ESWIN Computing Technology Co., Ltd.. All rights reserved.
+ * SPDX-License-Identifier: GPL-2.0
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, version 2.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <https://www.gnu.org/licenses/>.
+ *
+ * Authors: Yulin Lu <luyulin@eswincomputing.com>
+ */
+#include <linux/io.h>
+#include <linux/mfd/syscon.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+#include <linux/pinctrl/pinctrl.h>
+#include <linux/pinctrl/pinmux.h>
+#include <linux/pinctrl/pinconf.h>
+#include <linux/pinctrl/pinconf-generic.h>
+#include <linux/regmap.h>
+#include "pinctrl-utils.h"
+#include "core.h"
+
+#define ESWIN_MIO_NUM 164
+
+#define ESWIN_PINCONF_IE	   BIT(0)
+#define ESWIN_PINCONF_PULLUP   BIT(1)
+#define ESWIN_PINCONF_PULLDOWN BIT(2)
+#define ESWIN_PINCONF_DRIVER_STRENGTH_MASK  0xf  // 0111 1000
+#define ESWIN_PINCONF_DRIVER_SHIFT 3
+#define ESWIN_PINCONF_SMT BIT(7)
+
+struct eswin_function_desc {
+	const char *name;
+	const char * const *groups;
+	int ngroups;
+	u32 mux_val;
+	u32 mux_mask;
+};
+
+struct eswin_group_desc{
+	const char *name;
+	const unsigned int *pins;
+	const unsigned int npins;
+
+};
+
+struct eswin_pinctrl {
+	struct pinctrl_dev *pctrl;
+	void __iomem		*base;
+	const struct eswin_group_desc *groups;
+	unsigned int ngroups;
+	const struct eswin_function_desc *funcs;
+	unsigned int nfuncs;
+};
+
+static const struct pinctrl_pin_desc eswin_pins[] = {
+
+	PINCTRL_PIN(0, "CHIP_MODE"),
+	PINCTRL_PIN(1, "MODE_SET0"),
+	PINCTRL_PIN(2, "MODE_SET1"),
+	PINCTRL_PIN(3, "MODE_SET2"),
+	PINCTRL_PIN(4, "MODE_SET3"),
+	PINCTRL_PIN(5, "XIN"),
+	PINCTRL_PIN(6, "RTC_XIN"),
+	PINCTRL_PIN(7, "RST_OUT_N"),
+	PINCTRL_PIN(8,"KEY_RESET_N"),
+	PINCTRL_PIN(9,"RST_IN_N"),
+	PINCTRL_PIN(10,"POR_IN_N"),
+	PINCTRL_PIN(11,"POR_OUT_N"),
+	PINCTRL_PIN(12,"GPIO0"),
+	PINCTRL_PIN(13,"POR_SEL"),
+	PINCTRL_PIN(14,"JTAG0_TCK"),
+	PINCTRL_PIN(15,"JTAG0_TMS"),
+	PINCTRL_PIN(16,"JTAG0_TDI"),
+	PINCTRL_PIN(17,"JTAG0_TDO"),
+	PINCTRL_PIN(18,"JTAG0_TRST"),
+	PINCTRL_PIN(19,"SPI2_CS0_N"),
+	PINCTRL_PIN(20,"JTAG1_TCK"),
+	PINCTRL_PIN(21,"JTAG1_TMS"),
+	PINCTRL_PIN(22,"JTAG1_TDI"),
+	PINCTRL_PIN(23,"JTAG1_TDO"),
+	PINCTRL_PIN(24,"JTAG1_TRST"),
+	PINCTRL_PIN(25,"SPI2_CS1_N"),
+	PINCTRL_PIN(26,"PCIE_CLKREQ_N"),
+	PINCTRL_PIN(27,"PCIE_WAKE_N"),
+	PINCTRL_PIN(28,"PCIE_PERST_N"),
+	PINCTRL_PIN(29,"HDMI_SCL"),
+	PINCTRL_PIN(30,"HDMI_SDA"),
+	PINCTRL_PIN(31,"HDMI_CEC"),
+	PINCTRL_PIN(32,"JTAG2_TRST"),
+	PINCTRL_PIN(33,"RGMII0_CLK_125"),
+	PINCTRL_PIN(34,"RGMII0_TXEN"),
+	PINCTRL_PIN(35,"RGMII0_TXCLK"),
+	PINCTRL_PIN(36,"RGMII0_TXD0"),
+	PINCTRL_PIN(37,"RGMII0_TXD1"),
+	PINCTRL_PIN(38,"RGMII0_TXD2"),
+	PINCTRL_PIN(39,"RGMII0_TXD3"),
+	PINCTRL_PIN(40,"I2S0_BCLK"),
+	PINCTRL_PIN(41,"I2S0_WCLK"),
+	PINCTRL_PIN(42,"I2S0_SDI"),
+	PINCTRL_PIN(43,"I2S0_SDO"),
+	PINCTRL_PIN(44,"I2S_MCLK"),
+	PINCTRL_PIN(45,"RGMII0_RXCLK"),
+	PINCTRL_PIN(46,"RGMII0_RXDV"),
+	PINCTRL_PIN(47,"RGMII0_RXD0"),
+	PINCTRL_PIN(48,"RGMII0_RXD1"),
+	PINCTRL_PIN(49,"RGMII0_RXD2"),
+	PINCTRL_PIN(50,"RGMII0_RXD3"),
+	PINCTRL_PIN(51,"I2S2_BCLK"),
+	PINCTRL_PIN(52,"I2S2_WCLK"),
+	PINCTRL_PIN(53,"I2S2_SDI"),
+	PINCTRL_PIN(54,"I2S2_SDO"),
+	PINCTRL_PIN(55,"GPIO27"),
+	PINCTRL_PIN(56,"GPIO28"),
+	PINCTRL_PIN(57,"GPIO29"),
+	PINCTRL_PIN(58,"RGMII0_MDC"),
+	PINCTRL_PIN(59,"RGMII0_MDIO"),
+	PINCTRL_PIN(60,"RGMII0_INTB"),
+	PINCTRL_PIN(61,"RGMII1_CLK_125"),
+	PINCTRL_PIN(62,"RGMII1_TXEN"),
+	PINCTRL_PIN(63,"RGMII1_TXCLK"),
+	PINCTRL_PIN(64,"RGMII1_TXD0"),
+	PINCTRL_PIN(65,"RGMII1_TXD1"),
+	PINCTRL_PIN(66,"RGMII1_TXD2"),
+	PINCTRL_PIN(67,"RGMII1_TXD3"),
+	PINCTRL_PIN(68,"I2S1_BCLK"),
+	PINCTRL_PIN(69,"I2S1_WCLK"),
+	PINCTRL_PIN(70,"I2S1_SDI"),
+	PINCTRL_PIN(71,"I2S1_SDO"),
+	PINCTRL_PIN(72,"GPIO34"),
+	PINCTRL_PIN(73,"RGMII1_RXCLK"),
+	PINCTRL_PIN(74,"RGMII1_RXDV"),
+	PINCTRL_PIN(75,"RGMII1_RXD0"),
+	PINCTRL_PIN(76,"RGMII1_RXD1"),
+	PINCTRL_PIN(77,"RGMII1_RXD2"),
+	PINCTRL_PIN(78,"RGMII1_RXD3"),
+	PINCTRL_PIN(79,"SPI1_CS0_N"),
+	PINCTRL_PIN(80,"SPI1_CLK"),
+	PINCTRL_PIN(81,"SPI1_D0"),
+	PINCTRL_PIN(82,"SPI1_D1"),
+	PINCTRL_PIN(83,"SPI1_D2"),
+	PINCTRL_PIN(84,"SPI1_D3"),
+	PINCTRL_PIN(85,"SPI1_CS1_N"),
+	PINCTRL_PIN(86,"RGMII1_MDC"),
+	PINCTRL_PIN(87,"RGMII1_MDIO"),
+	PINCTRL_PIN(88,"RGMII1_INTB"),
+	PINCTRL_PIN(89,"USB0_PWREN"),
+	PINCTRL_PIN(90,"USB1_PWREN"),
+	PINCTRL_PIN(91,"I2C0_SCL"),
+	PINCTRL_PIN(92,"I2C0_SDA"),
+	PINCTRL_PIN(93,"I2C1_SCL"),
+	PINCTRL_PIN(94,"I2C1_SDA"),
+	PINCTRL_PIN(95,"I2C2_SCL"),
+	PINCTRL_PIN(96,"I2C2_SDA"),
+	PINCTRL_PIN(97,"I2C3_SCL"),
+	PINCTRL_PIN(98,"I2C3_SDA"),
+	PINCTRL_PIN(99,"I2C4_SCL"),
+	PINCTRL_PIN(100,"I2C4_SDA"),
+	PINCTRL_PIN(101,"I2C5_SCL"),
+	PINCTRL_PIN(102,"I2C5_SDA"),
+	PINCTRL_PIN(103,"UART0_TX"),
+	PINCTRL_PIN(104,"UART0_RX"),
+	PINCTRL_PIN(105,"UART1_TX"),
+	PINCTRL_PIN(106,"UART1_RX"),
+	PINCTRL_PIN(107,"UART1_CTS"),
+	PINCTRL_PIN(108,"UART1_RTS"),
+	PINCTRL_PIN(109,"UART2_TX"),
+	PINCTRL_PIN(110,"UART2_RX"),
+	PINCTRL_PIN(111,"JTAG2_TCK"),
+	PINCTRL_PIN(112,"JTAG2_TMS"),
+	PINCTRL_PIN(113,"JTAG2_TDI"),
+	PINCTRL_PIN(114,"JTAG2_TDO"),
+	PINCTRL_PIN(115,"FAN_PWM"),
+	PINCTRL_PIN(116,"FAN_TACH"),
+	PINCTRL_PIN(117,"MIPI_CSI0_XVS"),
+	PINCTRL_PIN(118,"MIPI_CSI0_XHS"),
+	PINCTRL_PIN(119,"MIPI_CSI0_MCLK"),
+	PINCTRL_PIN(120,"MIPI_CSI1_XVS"),
+	PINCTRL_PIN(121,"MIPI_CSI1_XHS"),
+	PINCTRL_PIN(122,"MIPI_CSI1_MCLK"),
+	PINCTRL_PIN(123,"MIPI_CSI2_XVS"),
+	PINCTRL_PIN(124,"MIPI_CSI2_XHS"),
+	PINCTRL_PIN(125,"MIPI_CSI2_MCLK"),
+	PINCTRL_PIN(126,"MIPI_CSI3_XVS"),
+	PINCTRL_PIN(127,"MIPI_CSI3_XHS"),
+	PINCTRL_PIN(128,"MIPI_CSI3_MCLK"),
+	PINCTRL_PIN(129,"MIPI_CSI4_XVS"),
+	PINCTRL_PIN(130,"MIPI_CSI4_XHS"),
+	PINCTRL_PIN(131,"MIPI_CSI4_MCLK"),
+	PINCTRL_PIN(132,"MIPI_CSI5_XVS"),
+	PINCTRL_PIN(133,"MIPI_CSI5_XHS"),
+	PINCTRL_PIN(134,"MIPI_CSI5_MCLK"),
+	PINCTRL_PIN(135,"SPI3_CS_N"),
+	PINCTRL_PIN(136,"SPI3_CLK"),
+	PINCTRL_PIN(137,"SPI3_DI"),
+	PINCTRL_PIN(138,"SPI3_DO"),
+	PINCTRL_PIN(139,"GPIO92"),
+	PINCTRL_PIN(140,"GPIO93"),
+	PINCTRL_PIN(141,"S_MODE"),
+	PINCTRL_PIN(142,"GPIO95"),
+	PINCTRL_PIN(143,"SPI0_CS_N"),
+	PINCTRL_PIN(144,"SPI0_CLK"),
+	PINCTRL_PIN(145,"SPI0_D0"),
+	PINCTRL_PIN(146,"SPI0_D1"),
+	PINCTRL_PIN(147,"SPI0_D2"),
+	PINCTRL_PIN(148,"SPI0_D3"),
+	PINCTRL_PIN(149,"I2C10_SCL"),
+	PINCTRL_PIN(150,"I2C10_SDA"),
+	PINCTRL_PIN(151,"I2C11_SCL"),
+	PINCTRL_PIN(152,"I2C11_SDA"),
+	PINCTRL_PIN(153,"GPIO106"),
+	PINCTRL_PIN(154,"BOOT_SEL0"),
+	PINCTRL_PIN(155,"BOOT_SEL1"),
+	PINCTRL_PIN(156,"BOOT_SEL2"),
+	PINCTRL_PIN(157,"BOOT_SEL3"),
+	PINCTRL_PIN(158,"GPIO111"),
+	PINCTRL_PIN(159,"D2D_SERDES_STATUS_IN"),
+	PINCTRL_PIN(160,"D2D_SERDES_STATUS_OUT"),
+	PINCTRL_PIN(161,"LPDDR_REF_CLK"),
+
+};
+
+#define ESWIN_PINCTRL_GRP(_name) \
+	{ \
+		.name = #_name "_group", \
+		.pins = _name ## _pins, \
+		.npins = ARRAY_SIZE(_name ## _pins), \
+	}
+
+//func0
+static const char * const sdio0_group[] = {"sdio0_group"};
+static const char * const sdio1_group[] = {"sdio1_group"};
+static const char * const por_sel_group[] = {"por_sel_group"};
+static const char * const jtag0_group[] = {"jtag0_group"};
+static const char * const jtag1_group[] = {"jtag1_group"};
+static const char * const spi2_cs_group[] = {"spi2_cs_group"};
+static const char * const pcie_group[] = {"pcie_group"};
+static const char * const hdmi_group[] = {"hdmi_group"};
+static const char * const jtag2_group[] = {"jtag2_group"};
+static const char * const rgmii0_group[] = {"rgmii0_group"};
+static const char * const i2s0_group[] = {"i2s0_group"};
+static const char * const i2s1_group[] = {"i2s1_group"};
+static const char * const i2s2_group[] = {"i2s2_group"};
+static const char * const por_time_sel0_group[] = {"por_time_sel0_group"};
+static const char * const por_time_sel1_group[] = {"por_time_sel1_group"};
+static const char * const rgmii1_group[] = {"rgmii1_group"};
+static const char * const spi1_group[] = {"spi1_group"};
+static const char * const usb0_pwren_group[] = {"usb0_pwren_group"};
+static const char * const usb1_pwren_group[] = {"usb1_pwren_group"};
+static const char * const i2c0_group[] = {"i2c0_group"};
+static const char * const i2c1_group[] = {"i2c1_group"};
+static const char * const i2c2_group[] = {"i2c2_group"};
+static const char * const i2c3_group[] = {"i2c3_group"};
+static const char * const i2c4_group[] = {"i2c4_group"};
+static const char * const i2c5_group[] = {"i2c5_group"};
+static const char * const uart0_group[] = {"uart0_group"};
+static const char * const uart1_group[] = {"uart1_group"};
+static const char * const uart2_group[] = {"uart2_group"};
+
+static const char * const pwm0_group[] = {"pwm0_group"};
+static const char * const fan_tach_group[] = {"fan_tach_group"};
+static const char * const mipi_csi0_group[] = {"mipi_csi0_group"};
+static const char * const mipi_csi1_group[] = {"mipi_csi1_group"};
+static const char * const mipi_csi2_group[] = {"mipi_csi2_group"};
+static const char * const mipi_csi3_group[] = {"mipi_csi3_group"};
+static const char * const mipi_csi4_group[] = {"mipi_csi4_group"};
+static const char * const mipi_csi5_group[] = {"mipi_csi5_group"};
+static const char * const spi3_group[] = {"spi3_group"};
+static const char * const i2c8_group[] = {"i2c8_group"};
+static const char * const s_mode_group[] = {"s_mode_group"};
+static const char * const pinmux_ddr_refclk_sel_group[] = {"pinmux_ddr_refclk_sel_group"};
+static const char * const spi0_group[] = {"spi0_group"};
+static const char * const i2c10_group[] = {"i2c10_group"};
+static const char * const i2c11_group[] = {"i2c11_group"};
+static const char * const boot_sel_group[] = {"boot_sel_group"};
+static const char * const lpddr_ref_clk_group[] = {"lpddr_ref_clk_group"};
+
+//func1
+static const char * const spi2_clk_group[] = {"spi2_clk_group"};
+static const char * const spi2_d0_group[] = {"spi2_d0_group"};
+static const char * const spi2_d1_d2_d3_group[] = {"spi2_d1_d2_d3_group"};
+
+static const char * const sata_act_led_group[] = {"sata_act_led_group"};
+static const char * const emmc_led_control_group[] = {"emmc_led_control_group"};
+static const char * const sd0_led_control_group[] = {"sd0_led_control_group"};
+static const char * const i2c9_group[] = {"i2c9_group"};
+static const char * const sd1_led_control_group[] = {"sd1_led_control_group"};
+static const char * const pwm1_group[] = {"pwm1_group"};
+static const char * const pwm2_group[] = {"pwm2_group"};
+static const char * const i2c6_group[] = {"i2c6_group"};
+static const char * const i2c7_group[] = {"i2c7_group"};
+static const char * const mipi_csi_xtrig_group[] = {"mipi_csi_xtrig_group"};
+
+//gpio
+static const char * const gpio0_group[] = {"gpio0_group"};
+static const char * const gpio1_group[] = {"gpio1_group"};
+static const char * const gpio2_group[] = {"gpio2_group"};
+static const char * const gpio3_group[] = {"gpio3_group"};
+static const char * const gpio4_group[] = {"gpio4_group"};
+static const char * const gpio5_group[] = {"gpio5_group"};
+static const char * const gpio6_group[] = {"gpio6_group"};
+static const char * const gpio7_group[] = {"gpio7_group"};
+static const char * const gpio8_group[] = {"gpio8_group"};
+static const char * const gpio9_group[] = {"gpio9_group"};
+static const char * const gpio10_group[] = {"gpio10_group"};
+static const char * const gpio11_group[] = {"gpio11_group"};
+static const char * const gpio12_group[] = {"gpio12_group"};
+static const char * const gpio13_group[] = {"gpio13_group"};
+static const char * const gpio14_group[] = {"gpio14_group"};
+static const char * const gpio15_group[] = {"gpio15_group"};
+static const char * const gpio16_group[] = {"gpio16_group"};
+static const char * const gpio17_group[] = {"gpio17_group"};
+static const char * const gpio18_group[] = {"gpio18_group"};
+static const char * const gpio19_group[] = {"gpio19_group"};
+static const char * const gpio20_group[] = {"gpio20_group"};
+static const char * const gpio21_group[] = {"gpio21_group"};
+static const char * const gpio22_group[] = {"gpio22_group"};
+static const char * const gpio23_group[] = {"gpio23_group"};
+static const char * const gpio24_group[] = {"gpio24_group"};
+static const char * const gpio25_group[] = {"gpio25_group"};
+static const char * const gpio26_group[] = {"gpio26_group"};
+static const char * const gpio27_group[] = {"gpio27_group"};
+static const char * const gpio28_group[] = {"gpio28_group"};
+static const char * const gpio29_group[] = {"gpio29_group"};
+static const char * const gpio30_group[] = {"gpio30_group"};
+static const char * const gpio31_group[] = {"gpio31_group"};
+static const char * const gpio32_group[] = {"gpio32_group"};
+static const char * const gpio33_group[] = {"gpio33_group"};
+static const char * const gpio34_group[] = {"gpio34_group"};
+static const char * const gpio35_group[] = {"gpio35_group"};
+static const char * const gpio36_group[] = {"gpio36_group"};
+static const char * const gpio37_group[] = {"gpio37_group"};
+static const char * const gpio38_group[] = {"gpio38_group"};
+static const char * const gpio39_group[] = {"gpio39_group"};
+static const char * const gpio40_group[] = {"gpio40_group"};
+static const char * const gpio41_group[] = {"gpio41_group"};
+static const char * const gpio42_group[] = {"gpio42_group"};
+static const char * const gpio43_group[] = {"gpio43_group"};
+static const char * const gpio44_group[] = {"gpio44_group"};
+static const char * const gpio45_group[] = {"gpio45_group"};
+static const char * const gpio46_group[] = {"gpio46_group"};
+static const char * const gpio47_group[] = {"gpio47_group"};
+static const char * const gpio48_group[] = {"gpio48_group"};
+static const char * const gpio49_group[] = {"gpio49_group"};
+
+static const char * const gpio50_group[] = {"gpio50_group"};
+static const char * const gpio51_group[] = {"gpio51_group"};
+static const char * const gpio52_group[] = {"gpio52_group"};
+static const char * const gpio53_group[] = {"gpio53_group"};
+static const char * const gpio54_group[] = {"gpio54_group"};
+static const char * const gpio55_group[] = {"gpio55_group"};
+static const char * const gpio56_group[] = {"gpio56_group"};
+static const char * const gpio57_group[] = {"gpio57_group"};
+static const char * const gpio58_group[] = {"gpio58_group"};
+static const char * const gpio59_group[] = {"gpio59_group"};
+
+static const char * const gpio60_group[] = {"gpio60_group"};
+static const char * const gpio61_group[] = {"gpio61_group"};
+static const char * const gpio62_group[] = {"gpio62_group"};
+static const char * const gpio63_group[] = {"gpio63_group"};
+static const char * const gpio64_group[] = {"gpio64_group"};
+static const char * const gpio65_group[] = {"gpio65_group"};
+static const char * const gpio66_group[] = {"gpio66_group"};
+static const char * const gpio67_group[] = {"gpio67_group"};
+static const char * const gpio68_group[] = {"gpio68_group"};
+static const char * const gpio69_group[] = {"gpio69_group"};
+
+static const char * const gpio70_group[] = {"gpio70_group"};
+static const char * const gpio71_group[] = {"gpio71_group"};
+static const char * const gpio72_group[] = {"gpio72_group"};
+static const char * const gpio73_group[] = {"gpio73_group"};
+static const char * const gpio74_group[] = {"gpio74_group"};
+static const char * const gpio75_group[] = {"gpio75_group"};
+static const char * const gpio76_group[] = {"gpio76_group"};
+static const char * const gpio77_group[] = {"gpio77_group"};
+static const char * const gpio78_group[] = {"gpio78_group"};
+static const char * const gpio79_group[] = {"gpio79_group"};
+
+static const char * const gpio80_group[] = {"gpio80_group"};
+static const char * const gpio81_group[] = {"gpio81_group"};
+static const char * const gpio82_group[] = {"gpio82_group"};
+static const char * const gpio83_group[] = {"gpio83_group"};
+static const char * const gpio84_group[] = {"gpio84_group"};
+static const char * const gpio85_group[] = {"gpio85_group"};
+static const char * const gpio86_group[] = {"gpio86_group"};
+static const char * const gpio87_group[] = {"gpio87_group"};
+static const char * const gpio88_group[] = {"gpio88_group"};
+static const char * const gpio89_group[] = {"gpio89_group"};
+
+static const char * const gpio90_group[] = {"gpio90_group"};
+static const char * const gpio91_group[] = {"gpio91_group"};
+static const char * const gpio92_group[] = {"gpio92_group"};
+static const char * const gpio93_group[] = {"gpio93_group"};
+static const char * const gpio94_group[] = {"gpio94_group"};
+static const char * const gpio95_group[] = {"gpio95_group"};
+static const char * const gpio96_group[] = {"gpio96_group"};
+static const char * const gpio97_group[] = {"gpio97_group"};
+static const char * const gpio98_group[] = {"gpio98_group"};
+static const char * const gpio99_group[] = {"gpio99_group"};
+
+static const char * const gpio100_group[] = {"gpio100_group"};
+static const char * const gpio101_group[] = {"gpio101_group"};
+static const char * const gpio102_group[] = {"gpio102_group"};
+static const char * const gpio103_group[] = {"gpio103_group"};
+static const char * const gpio104_group[] = {"gpio104_group"};
+static const char * const gpio105_group[] = {"gpio105_group"};
+static const char * const gpio106_group[] = {"gpio106_group"};
+static const char * const gpio107_group[] = {"gpio107_group"};
+static const char * const gpio108_group[] = {"gpio108_group"};
+static const char * const gpio109_group[] = {"gpio109_group"};
+static const char * const gpio110_group[] = {"gpio110_group"};
+static const char * const gpio111_group[] = {"gpio111_group"};
+
+//func3
+static const char * const uart4_group[] = {"uart4_group"};
+static const char * const uart3_group[] = {"uart3_group"};
+
+//func6
+static const char * const csi_mon_out_group[] = {"csi_mon_out_group"};
+static const char * const csi_ocla_clk_group[] = {"csi_ocla_clk_group"};
+static const char * const csi_mon_out_valid_group[] = {"csi_mon_out_valid_group"};
+static const char * const csi_parity_error_group[] = {"csi_parity_error_group"};
+static const char * const csi_dtb_out_group[] = {"csi_dtb_out_group"};
+static const char * const csi_phy_sel_group[] = {"csi_phy_sel_group"};
+static const char * const vc_g2d0_debug_out_group[] = {"vc_g2d0_debug_out_group"};
+static const char * const vc_g2d1_debug_out_group[] = {"vc_g2d1_debug_out_group"};
+static const char * const sata_mpll_clk_group[] = {"sata_mpll_clk_group"};
+static const char * const sata_ref_repeat_clk_m_group[] = {"sata_ref_repeat_clk_m_group"};
+static const char * const sata_ref_repeat_clk_p_group[] = {"sata_ref_repeat_clk_p_group"};
+
+//func0
+static const unsigned int sdio0_pins[] = {1,2};
+static const unsigned int sdio1_pins[] = {3,4};
+static const unsigned int por_sel_pins[] = {13};
+static const unsigned int jtag0_pins[] = {14,15,16,17};
+static const unsigned int jtag1_pins[] = {20,21,22,23};
+static const unsigned int spi2_cs_pins[] = {19,25};
+static const unsigned int pcie_pins[] = {26,27,28};
+static const unsigned int hdmi_pins[] = {29,30,31};
+static const unsigned int jtag2_pins[] = {32,111,112,113,114};
+static const unsigned int rgmii0_pins[] = {33,34,35,36,37,38,39,45,46,47,48,49,50,58,59,60};
+static const unsigned int i2s0_pins[] = {40,41,42,43,44};
+static const unsigned int i2s1_pins[] = {68,69,70,71,44};
+static const unsigned int i2s2_pins[] = {51,52,53,54,44};
+static const unsigned int por_time_sel0_pins[] = {57};
+static const unsigned int por_time_sel1_pins[] = {72};
+static const unsigned int rgmii1_pins[] = {61,62,63,64,65,66,67,73,74,75,76,77,78,86,87,88};
+static const unsigned int spi1_pins[] = {79,80,81,82,83,84,85};
+static const unsigned int usb0_pwren_pins[] = {89};
+static const unsigned int usb1_pwren_pins[] = {90};
+static const unsigned int i2c0_pins[] = {91,92};
+static const unsigned int i2c1_pins[] = {93,94};
+static const unsigned int i2c2_pins[] = {95,96};
+static const unsigned int i2c3_pins[] = {97,98};
+static const unsigned int i2c4_pins[] = {99,100};
+static const unsigned int i2c5_pins[] = {101,102};
+static const unsigned int uart0_pins[] = {103,104};
+static const unsigned int uart1_pins[] = {105,106,107,108};
+static const unsigned int uart2_pins[] = {109,110};
+static const unsigned int pwm0_pins[] = {115};
+static const unsigned int fan_tach_pins[] = {116};
+static const unsigned int mipi_csi0_pins[] = {117,118,119};
+static const unsigned int mipi_csi1_pins[] = {120,121,122};
+static const unsigned int mipi_csi2_pins[] = {123,124,125};
+static const unsigned int mipi_csi3_pins[] = {126,127,128};
+static const unsigned int mipi_csi4_pins[] = {129,130,131};
+static const unsigned int mipi_csi5_pins[] = {132,133,134};
+static const unsigned int spi3_pins[] = {135,136,137,138};
+static const unsigned int i2c8_pins[] = {139,140};
+static const unsigned int s_mode_pins[] = {141};
+static const unsigned int pinmux_ddr_refclk_sel_pins[] = {142};
+static const unsigned int spi0_pins[] = {143,144,145,146,147,148};
+static const unsigned int i2c10_pins[] = {149,150};
+static const unsigned int i2c11_pins[] = {151,152};
+static const unsigned int boot_sel_pins[] = {154,155,156,157};
+static const unsigned int lpddr_ref_clk_pins[] = {158};
+
+//func1
+static const unsigned int spi2_clk_pins[] = {14};
+static const unsigned int spi2_d0_pins[] = {15};
+static const unsigned int spi2_d1_d2_d3_pins[] = {16,17,18};
+
+static const unsigned int sata_act_led_pins[] = {55};
+static const unsigned int emmc_led_control_pins[] = {57};
+static const unsigned int sd0_led_control_pins[] = {72};
+static const unsigned int i2c9_pins[] = {81,82};
+static const unsigned int sd1_led_control_pins[] = {83};
+static const unsigned int pwm1_pins[] = {84};
+static const unsigned int pwm2_pins[] = {85};
+static const unsigned int i2c6_pins[] = {107,108};
+static const unsigned int i2c7_pins[] = {109,110};
+static const unsigned int mipi_csi_xtrig_pins[] = {139,140};
+
+//gpio
+static const unsigned int gpio0_pins[] = {12};
+static const unsigned int gpio1_pins[] = {14};
+static const unsigned int gpio2_pins[] = {15};
+static const unsigned int gpio3_pins[] = {16};
+static const unsigned int gpio4_pins[] = {17};
+static const unsigned int gpio5_pins[] = {18};
+static const unsigned int gpio6_pins[] = {19};
+static const unsigned int gpio7_pins[] = {20};
+static const unsigned int gpio8_pins[] = {21};
+static const unsigned int gpio9_pins[] = {22};
+
+static const unsigned int gpio10_pins[] = {23};
+static const unsigned int gpio11_pins[] = {24};
+static const unsigned int gpio12_pins[] = {25};
+static const unsigned int gpio13_pins[] = {1};
+static const unsigned int gpio14_pins[] = {2};
+static const unsigned int gpio15_pins[] = {3};
+static const unsigned int gpio16_pins[] = {4};
+static const unsigned int gpio17_pins[] = {32};
+static const unsigned int gpio18_pins[] = {40};
+static const unsigned int gpio19_pins[] = {41};
+
+static const unsigned int gpio20_pins[] = {42};
+static const unsigned int gpio21_pins[] = {43};
+static const unsigned int gpio22_pins[] = {44};
+static const unsigned int gpio23_pins[] = {51};
+static const unsigned int gpio24_pins[] = {52};
+static const unsigned int gpio25_pins[] = {53};
+static const unsigned int gpio26_pins[] = {54};
+static const unsigned int gpio27_pins[] = {55};
+static const unsigned int gpio28_pins[] = {56};
+static const unsigned int gpio29_pins[] = {57};
+
+static const unsigned int gpio30_pins[] = {68};
+static const unsigned int gpio31_pins[] = {69};
+static const unsigned int gpio32_pins[] = {70};
+static const unsigned int gpio33_pins[] = {71};
+static const unsigned int gpio34_pins[] = {72};
+static const unsigned int gpio35_pins[] = {79};
+static const unsigned int gpio36_pins[] = {80};
+static const unsigned int gpio37_pins[] = {81};
+static const unsigned int gpio38_pins[] = {82};
+static const unsigned int gpio39_pins[] = {83};
+
+static const unsigned int gpio40_pins[] = {84};
+static const unsigned int gpio41_pins[] = {85};
+static const unsigned int gpio42_pins[] = {89};
+static const unsigned int gpio43_pins[] = {90};
+static const unsigned int gpio44_pins[] = {91};
+static const unsigned int gpio45_pins[] = {92};
+static const unsigned int gpio46_pins[] = {93};
+static const unsigned int gpio47_pins[] = {94};
+static const unsigned int gpio48_pins[] = {95};
+static const unsigned int gpio49_pins[] = {96};
+
+static const unsigned int gpio50_pins[] = {97};
+static const unsigned int gpio51_pins[] = {98};
+static const unsigned int gpio52_pins[] = {99};
+static const unsigned int gpio53_pins[] = {100};
+static const unsigned int gpio54_pins[] = {101};
+static const unsigned int gpio55_pins[] = {102};
+static const unsigned int gpio56_pins[] = {103};
+static const unsigned int gpio57_pins[] = {104};
+static const unsigned int gpio58_pins[] = {105};
+static const unsigned int gpio59_pins[] = {106};
+
+static const unsigned int gpio60_pins[] = {107};
+static const unsigned int gpio61_pins[] = {108};
+static const unsigned int gpio62_pins[] = {109};
+static const unsigned int gpio63_pins[] = {110};
+static const unsigned int gpio64_pins[] = {111};
+static const unsigned int gpio65_pins[] = {112};
+static const unsigned int gpio66_pins[] = {113};
+static const unsigned int gpio67_pins[] = {114};
+static const unsigned int gpio68_pins[] = {115};
+static const unsigned int gpio69_pins[] = {116};
+
+static const unsigned int gpio70_pins[] = {117};
+static const unsigned int gpio71_pins[] = {118};
+static const unsigned int gpio72_pins[] = {119};
+static const unsigned int gpio73_pins[] = {120};
+static const unsigned int gpio74_pins[] = {121};
+static const unsigned int gpio75_pins[] = {122};
+static const unsigned int gpio76_pins[] = {123};
+static const unsigned int gpio77_pins[] = {124};
+static const unsigned int gpio78_pins[] = {125};
+static const unsigned int gpio79_pins[] = {126};
+
+static const unsigned int gpio80_pins[] = {127};
+static const unsigned int gpio81_pins[] = {128};
+static const unsigned int gpio82_pins[] = {129};
+static const unsigned int gpio83_pins[] = {130};
+static const unsigned int gpio84_pins[] = {131};
+static const unsigned int gpio85_pins[] = {132};
+static const unsigned int gpio86_pins[] = {133};
+static const unsigned int gpio87_pins[] = {134};
+static const unsigned int gpio88_pins[] = {135};
+static const unsigned int gpio89_pins[] = {136};
+
+static const unsigned int gpio90_pins[] = {137};
+static const unsigned int gpio91_pins[] = {138};
+static const unsigned int gpio92_pins[] = {139};
+static const unsigned int gpio93_pins[] = {140};
+static const unsigned int gpio94_pins[] = {141};
+static const unsigned int gpio95_pins[] = {142};
+static const unsigned int gpio96_pins[] = {143};
+static const unsigned int gpio97_pins[] = {144};
+static const unsigned int gpio98_pins[] = {145};
+static const unsigned int gpio99_pins[] = {146};
+
+static const unsigned int gpio100_pins[] = {147};
+static const unsigned int gpio101_pins[] = {148};
+static const unsigned int gpio102_pins[] = {149};
+static const unsigned int gpio103_pins[] = {150};
+static const unsigned int gpio104_pins[] = {151};
+static const unsigned int gpio105_pins[] = {152};
+static const unsigned int gpio106_pins[] = {153};
+static const unsigned int gpio107_pins[] = {154};
+static const unsigned int gpio108_pins[] = {155};
+static const unsigned int gpio109_pins[] = {156};
+static const unsigned int gpio110_pins[] = {157};
+static const unsigned int gpio111_pins[] = {158};
+
+//func3
+static const unsigned int uart4_pins[] = {81,82};
+static const unsigned int uart3_pins[] = {139,140};
+
+//func6
+static const unsigned int csi_mon_out_pins[] = {32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55};
+static const unsigned int csi_ocla_clk_pins[] = {96};
+static const unsigned int csi_mon_out_valid_pins[] = {97};
+static const unsigned int csi_parity_error_pins[] = {98};
+static const unsigned int csi_dtb_out_pins[] = {99,100,101,102,129,130,131,132};
+static const unsigned int csi_phy_sel_pins[] = {133,134,109};
+static const unsigned int vc_g2d0_debug_out_pins[] = {110,111,112,113,114,115,116,117};
+static const unsigned int vc_g2d1_debug_out_pins[] = {118,119,120,121,122,123,124,125};
+static const unsigned int sata_mpll_clk_pins[] = {126};
+static const unsigned int sata_ref_repeat_clk_m_pins[] = {127};
+static const unsigned int sata_ref_repeat_clk_p_pins[] = {128};
+
+static const struct eswin_group_desc eswin_pinctrl_groups[] =
+{
+	//func0
+	ESWIN_PINCTRL_GRP(sdio0),
+	ESWIN_PINCTRL_GRP(sdio1),
+	ESWIN_PINCTRL_GRP(por_sel),
+	ESWIN_PINCTRL_GRP(jtag0),
+	ESWIN_PINCTRL_GRP(jtag1),
+	ESWIN_PINCTRL_GRP(spi2_cs),
+	ESWIN_PINCTRL_GRP(pcie),
+	ESWIN_PINCTRL_GRP(hdmi),
+	ESWIN_PINCTRL_GRP(jtag2),
+	ESWIN_PINCTRL_GRP(rgmii0),
+	ESWIN_PINCTRL_GRP(i2s0),
+	ESWIN_PINCTRL_GRP(i2s1),
+	ESWIN_PINCTRL_GRP(i2s2),
+	ESWIN_PINCTRL_GRP(por_time_sel0),
+	ESWIN_PINCTRL_GRP(por_time_sel1),
+	ESWIN_PINCTRL_GRP(rgmii1),
+	ESWIN_PINCTRL_GRP(spi1),
+	ESWIN_PINCTRL_GRP(usb0_pwren),
+	ESWIN_PINCTRL_GRP(usb1_pwren),
+	ESWIN_PINCTRL_GRP(i2c0),
+	ESWIN_PINCTRL_GRP(i2c1),
+	ESWIN_PINCTRL_GRP(i2c2),
+	ESWIN_PINCTRL_GRP(i2c3),
+	ESWIN_PINCTRL_GRP(i2c4),
+	ESWIN_PINCTRL_GRP(i2c5),
+	ESWIN_PINCTRL_GRP(uart0),
+	ESWIN_PINCTRL_GRP(uart1),
+	ESWIN_PINCTRL_GRP(uart2),
+	ESWIN_PINCTRL_GRP(pwm0),
+	ESWIN_PINCTRL_GRP(fan_tach),
+	ESWIN_PINCTRL_GRP(mipi_csi0),
+	ESWIN_PINCTRL_GRP(mipi_csi1),
+	ESWIN_PINCTRL_GRP(mipi_csi2),
+	ESWIN_PINCTRL_GRP(mipi_csi3),
+	ESWIN_PINCTRL_GRP(mipi_csi4),
+	ESWIN_PINCTRL_GRP(mipi_csi5),
+	ESWIN_PINCTRL_GRP(spi3),
+	ESWIN_PINCTRL_GRP(i2c8),
+	ESWIN_PINCTRL_GRP(s_mode),
+	ESWIN_PINCTRL_GRP(pinmux_ddr_refclk_sel),
+	ESWIN_PINCTRL_GRP(spi0),
+	ESWIN_PINCTRL_GRP(i2c10),
+	ESWIN_PINCTRL_GRP(i2c11),
+	ESWIN_PINCTRL_GRP(boot_sel),
+	ESWIN_PINCTRL_GRP(lpddr_ref_clk),
+
+	//func1
+	ESWIN_PINCTRL_GRP(spi2_clk),
+	ESWIN_PINCTRL_GRP(spi2_d0),
+	ESWIN_PINCTRL_GRP(spi2_d1_d2_d3),
+
+	ESWIN_PINCTRL_GRP(sata_act_led),
+	ESWIN_PINCTRL_GRP(emmc_led_control),
+	ESWIN_PINCTRL_GRP(sd0_led_control),
+	ESWIN_PINCTRL_GRP(i2c9),
+	ESWIN_PINCTRL_GRP(sd1_led_control),
+	ESWIN_PINCTRL_GRP(pwm1),
+	ESWIN_PINCTRL_GRP(pwm2),
+	ESWIN_PINCTRL_GRP(i2c6),
+	ESWIN_PINCTRL_GRP(i2c7),
+	ESWIN_PINCTRL_GRP(mipi_csi_xtrig),
+
+	//gpio
+	ESWIN_PINCTRL_GRP(gpio0),
+	ESWIN_PINCTRL_GRP(gpio1),
+	ESWIN_PINCTRL_GRP(gpio2),
+	ESWIN_PINCTRL_GRP(gpio3),
+	ESWIN_PINCTRL_GRP(gpio4),
+	ESWIN_PINCTRL_GRP(gpio5),
+	ESWIN_PINCTRL_GRP(gpio6),
+	ESWIN_PINCTRL_GRP(gpio7),
+	ESWIN_PINCTRL_GRP(gpio8),
+	ESWIN_PINCTRL_GRP(gpio9),
+	ESWIN_PINCTRL_GRP(gpio10),
+	ESWIN_PINCTRL_GRP(gpio11),
+	ESWIN_PINCTRL_GRP(gpio12),
+	ESWIN_PINCTRL_GRP(gpio13),
+	ESWIN_PINCTRL_GRP(gpio14),
+	ESWIN_PINCTRL_GRP(gpio15),
+	ESWIN_PINCTRL_GRP(gpio16),
+	ESWIN_PINCTRL_GRP(gpio17),
+	ESWIN_PINCTRL_GRP(gpio18),
+	ESWIN_PINCTRL_GRP(gpio19),
+	ESWIN_PINCTRL_GRP(gpio20),
+	ESWIN_PINCTRL_GRP(gpio21),
+	ESWIN_PINCTRL_GRP(gpio22),
+	ESWIN_PINCTRL_GRP(gpio23),
+	ESWIN_PINCTRL_GRP(gpio24),
+	ESWIN_PINCTRL_GRP(gpio25),
+	ESWIN_PINCTRL_GRP(gpio26),
+	ESWIN_PINCTRL_GRP(gpio27),
+	ESWIN_PINCTRL_GRP(gpio28),
+	ESWIN_PINCTRL_GRP(gpio29),
+	ESWIN_PINCTRL_GRP(gpio30),
+	ESWIN_PINCTRL_GRP(gpio31),
+	ESWIN_PINCTRL_GRP(gpio32),
+	ESWIN_PINCTRL_GRP(gpio33),
+	ESWIN_PINCTRL_GRP(gpio34),
+	ESWIN_PINCTRL_GRP(gpio35),
+	ESWIN_PINCTRL_GRP(gpio36),
+	ESWIN_PINCTRL_GRP(gpio37),
+	ESWIN_PINCTRL_GRP(gpio38),
+	ESWIN_PINCTRL_GRP(gpio39),
+	ESWIN_PINCTRL_GRP(gpio40),
+	ESWIN_PINCTRL_GRP(gpio41),
+	ESWIN_PINCTRL_GRP(gpio42),
+	ESWIN_PINCTRL_GRP(gpio43),
+	ESWIN_PINCTRL_GRP(gpio44),
+	ESWIN_PINCTRL_GRP(gpio45),
+	ESWIN_PINCTRL_GRP(gpio46),
+	ESWIN_PINCTRL_GRP(gpio47),
+	ESWIN_PINCTRL_GRP(gpio48),
+	ESWIN_PINCTRL_GRP(gpio49),
+
+	ESWIN_PINCTRL_GRP(gpio50),
+	ESWIN_PINCTRL_GRP(gpio51),
+	ESWIN_PINCTRL_GRP(gpio52),
+	ESWIN_PINCTRL_GRP(gpio53),
+	ESWIN_PINCTRL_GRP(gpio54),
+	ESWIN_PINCTRL_GRP(gpio55),
+	ESWIN_PINCTRL_GRP(gpio56),
+	ESWIN_PINCTRL_GRP(gpio57),
+	ESWIN_PINCTRL_GRP(gpio58),
+	ESWIN_PINCTRL_GRP(gpio59),
+
+	ESWIN_PINCTRL_GRP(gpio60),
+	ESWIN_PINCTRL_GRP(gpio61),
+	ESWIN_PINCTRL_GRP(gpio62),
+	ESWIN_PINCTRL_GRP(gpio63),
+	ESWIN_PINCTRL_GRP(gpio64),
+	ESWIN_PINCTRL_GRP(gpio65),
+	ESWIN_PINCTRL_GRP(gpio66),
+	ESWIN_PINCTRL_GRP(gpio67),
+	ESWIN_PINCTRL_GRP(gpio68),
+	ESWIN_PINCTRL_GRP(gpio69),
+
+	ESWIN_PINCTRL_GRP(gpio70),
+	ESWIN_PINCTRL_GRP(gpio71),
+	ESWIN_PINCTRL_GRP(gpio72),
+	ESWIN_PINCTRL_GRP(gpio73),
+	ESWIN_PINCTRL_GRP(gpio74),
+	ESWIN_PINCTRL_GRP(gpio75),
+	ESWIN_PINCTRL_GRP(gpio76),
+	ESWIN_PINCTRL_GRP(gpio77),
+	ESWIN_PINCTRL_GRP(gpio78),
+	ESWIN_PINCTRL_GRP(gpio79),
+
+	ESWIN_PINCTRL_GRP(gpio80),
+	ESWIN_PINCTRL_GRP(gpio81),
+	ESWIN_PINCTRL_GRP(gpio82),
+	ESWIN_PINCTRL_GRP(gpio83),
+	ESWIN_PINCTRL_GRP(gpio84),
+	ESWIN_PINCTRL_GRP(gpio85),
+	ESWIN_PINCTRL_GRP(gpio86),
+	ESWIN_PINCTRL_GRP(gpio87),
+	ESWIN_PINCTRL_GRP(gpio88),
+	ESWIN_PINCTRL_GRP(gpio89),
+
+	ESWIN_PINCTRL_GRP(gpio90),
+	ESWIN_PINCTRL_GRP(gpio91),
+	ESWIN_PINCTRL_GRP(gpio92),
+	ESWIN_PINCTRL_GRP(gpio93),
+	ESWIN_PINCTRL_GRP(gpio94),
+	ESWIN_PINCTRL_GRP(gpio95),
+	ESWIN_PINCTRL_GRP(gpio96),
+	ESWIN_PINCTRL_GRP(gpio97),
+	ESWIN_PINCTRL_GRP(gpio98),
+	ESWIN_PINCTRL_GRP(gpio99),
+
+	ESWIN_PINCTRL_GRP(gpio100),
+	ESWIN_PINCTRL_GRP(gpio101),
+	ESWIN_PINCTRL_GRP(gpio102),
+	ESWIN_PINCTRL_GRP(gpio103),
+	ESWIN_PINCTRL_GRP(gpio104),
+	ESWIN_PINCTRL_GRP(gpio105),
+	ESWIN_PINCTRL_GRP(gpio106),
+	ESWIN_PINCTRL_GRP(gpio107),
+	ESWIN_PINCTRL_GRP(gpio108),
+	ESWIN_PINCTRL_GRP(gpio109),
+	ESWIN_PINCTRL_GRP(gpio110),
+	ESWIN_PINCTRL_GRP(gpio111),
+
+	//func3
+	ESWIN_PINCTRL_GRP(uart4),
+	ESWIN_PINCTRL_GRP(uart3),
+
+	//func6
+	ESWIN_PINCTRL_GRP(csi_mon_out),
+	ESWIN_PINCTRL_GRP(csi_ocla_clk),
+	ESWIN_PINCTRL_GRP(csi_mon_out_valid),
+	ESWIN_PINCTRL_GRP(csi_parity_error),
+	ESWIN_PINCTRL_GRP(csi_dtb_out),
+	ESWIN_PINCTRL_GRP(csi_phy_sel),
+	ESWIN_PINCTRL_GRP(vc_g2d0_debug_out),
+	ESWIN_PINCTRL_GRP(vc_g2d1_debug_out),
+	ESWIN_PINCTRL_GRP(sata_mpll_clk),
+	ESWIN_PINCTRL_GRP(sata_ref_repeat_clk_m),
+	ESWIN_PINCTRL_GRP(sata_ref_repeat_clk_p),
+};
+
+#define ESWIN_PINMUX_FUNCTION(_func_name, _mux_val, _mask)\
+	{				   \
+		.name = #_func_name"_func",			 \
+		.groups = _func_name##_group,	  \
+		.ngroups = ARRAY_SIZE(_func_name##_group),  \
+		.mux_val = _mux_val,			\
+		.mux_mask = _mask,		  \
+	}
+
+#define ESWIN_PINMUX_SHIFT  16
+#define ESWIN_PINMUX_MASK   (0x07 << ESWIN_PINMUX_SHIFT)
+
+static const struct eswin_function_desc eswin_pinmux_functions[] = {
+
+	//func0
+	ESWIN_PINMUX_FUNCTION(sdio0, 0, ESWIN_PINMUX_MASK),
+	ESWIN_PINMUX_FUNCTION(sdio1, 0, ESWIN_PINMUX_MASK),
+	ESWIN_PINMUX_FUNCTION(por_sel, 0, ESWIN_PINMUX_MASK),
+	ESWIN_PINMUX_FUNCTION(jtag0, 0, ESWIN_PINMUX_MASK),
+	ESWIN_PINMUX_FUNCTION(jtag1, 0, ESWIN_PINMUX_MASK),
+	ESWIN_PINMUX_FUNCTION(spi2_cs, 0, ESWIN_PINMUX_MASK),
+	ESWIN_PINMUX_FUNCTION(pcie, 0, ESWIN_PINMUX_MASK),
+	ESWIN_PINMUX_FUNCTION(hdmi, 0, ESWIN_PINMUX_MASK),
+	ESWIN_PINMUX_FUNCTION(jtag2, 0, ESWIN_PINMUX_MASK),
+	ESWIN_PINMUX_FUNCTION(rgmii0, 0, ESWIN_PINMUX_MASK),
+	ESWIN_PINMUX_FUNCTION(i2s0, 0, ESWIN_PINMUX_MASK),
+	ESWIN_PINMUX_FUNCTION(i2s1, 0, ESWIN_PINMUX_MASK),
+	ESWIN_PINMUX_FUNCTION(i2s2, 0, ESWIN_PINMUX_MASK),
+	ESWIN_PINMUX_FUNCTION(por_time_sel0, 0, ESWIN_PINMUX_MASK),
+	ESWIN_PINMUX_FUNCTION(por_time_sel1, 0, ESWIN_PINMUX_MASK),
+	ESWIN_PINMUX_FUNCTION(rgmii1, 0, ESWIN_PINMUX_MASK),
+	ESWIN_PINMUX_FUNCTION(spi1, 0, ESWIN_PINMUX_MASK),
+	ESWIN_PINMUX_FUNCTION(usb0_pwren, 0, ESWIN_PINMUX_MASK),
+	ESWIN_PINMUX_FUNCTION(usb1_pwren, 0, ESWIN_PINMUX_MASK),
+	ESWIN_PINMUX_FUNCTION(i2c0, 0, ESWIN_PINMUX_MASK),
+	ESWIN_PINMUX_FUNCTION(i2c1, 0, ESWIN_PINMUX_MASK),
+	ESWIN_PINMUX_FUNCTION(i2c2, 0, ESWIN_PINMUX_MASK),
+	ESWIN_PINMUX_FUNCTION(i2c3, 0, ESWIN_PINMUX_MASK),
+	ESWIN_PINMUX_FUNCTION(i2c4, 0, ESWIN_PINMUX_MASK),
+	ESWIN_PINMUX_FUNCTION(i2c5, 0, ESWIN_PINMUX_MASK),
+	ESWIN_PINMUX_FUNCTION(uart0, 0, ESWIN_PINMUX_MASK),
+	ESWIN_PINMUX_FUNCTION(uart1, 0, ESWIN_PINMUX_MASK),
+	ESWIN_PINMUX_FUNCTION(uart2, 0, ESWIN_PINMUX_MASK),
+	ESWIN_PINMUX_FUNCTION(pwm0, 0, ESWIN_PINMUX_MASK),
+	ESWIN_PINMUX_FUNCTION(fan_tach, 0, ESWIN_PINMUX_MASK),
+	ESWIN_PINMUX_FUNCTION(mipi_csi0, 0, ESWIN_PINMUX_MASK),
+	ESWIN_PINMUX_FUNCTION(mipi_csi1, 0, ESWIN_PINMUX_MASK),
+	ESWIN_PINMUX_FUNCTION(mipi_csi2, 0, ESWIN_PINMUX_MASK),
+	ESWIN_PINMUX_FUNCTION(mipi_csi3, 0, ESWIN_PINMUX_MASK),
+	ESWIN_PINMUX_FUNCTION(mipi_csi4, 0, ESWIN_PINMUX_MASK),
+	ESWIN_PINMUX_FUNCTION(mipi_csi5, 0, ESWIN_PINMUX_MASK),
+	ESWIN_PINMUX_FUNCTION(spi3, 0, ESWIN_PINMUX_MASK),
+	ESWIN_PINMUX_FUNCTION(i2c8, 0, ESWIN_PINMUX_MASK),
+	ESWIN_PINMUX_FUNCTION(s_mode, 0, ESWIN_PINMUX_MASK),
+	ESWIN_PINMUX_FUNCTION(pinmux_ddr_refclk_sel, 0, ESWIN_PINMUX_MASK),
+	ESWIN_PINMUX_FUNCTION(spi0, 0, ESWIN_PINMUX_MASK),
+	ESWIN_PINMUX_FUNCTION(i2c10, 0, ESWIN_PINMUX_MASK),
+	ESWIN_PINMUX_FUNCTION(i2c11, 0, ESWIN_PINMUX_MASK),
+	ESWIN_PINMUX_FUNCTION(boot_sel, 0, ESWIN_PINMUX_MASK),
+	ESWIN_PINMUX_FUNCTION(lpddr_ref_clk, 0, ESWIN_PINMUX_MASK),
+
+	//func1
+	ESWIN_PINMUX_FUNCTION(spi2_clk, 1, ESWIN_PINMUX_MASK),
+	ESWIN_PINMUX_FUNCTION(spi2_d0, 1, ESWIN_PINMUX_MASK),
+	ESWIN_PINMUX_FUNCTION(spi2_d1_d2_d3, 1, ESWIN_PINMUX_MASK),
+	ESWIN_PINMUX_FUNCTION(sata_act_led, 1, ESWIN_PINMUX_MASK),
+	ESWIN_PINMUX_FUNCTION(emmc_led_control, 1, ESWIN_PINMUX_MASK),
+	ESWIN_PINMUX_FUNCTION(sd0_led_control, 1, ESWIN_PINMUX_MASK),
+	ESWIN_PINMUX_FUNCTION(i2c9, 1, ESWIN_PINMUX_MASK),
+	ESWIN_PINMUX_FUNCTION(sd1_led_control, 1, ESWIN_PINMUX_MASK),
+	ESWIN_PINMUX_FUNCTION(pwm1, 1, ESWIN_PINMUX_MASK),
+	ESWIN_PINMUX_FUNCTION(pwm2, 1, ESWIN_PINMUX_MASK),
+	ESWIN_PINMUX_FUNCTION(i2c6, 1, ESWIN_PINMUX_MASK),
+	ESWIN_PINMUX_FUNCTION(i2c7, 1, ESWIN_PINMUX_MASK),
+	ESWIN_PINMUX_FUNCTION(mipi_csi_xtrig, 1, ESWIN_PINMUX_MASK),
+
+	//gpio
+	ESWIN_PINMUX_FUNCTION(gpio0, 0, ESWIN_PINMUX_MASK),
+	ESWIN_PINMUX_FUNCTION(gpio1, 2, ESWIN_PINMUX_MASK),
+	ESWIN_PINMUX_FUNCTION(gpio2, 2, ESWIN_PINMUX_MASK),
+	ESWIN_PINMUX_FUNCTION(gpio3, 2, ESWIN_PINMUX_MASK),
+	ESWIN_PINMUX_FUNCTION(gpio4, 2, ESWIN_PINMUX_MASK),
+	ESWIN_PINMUX_FUNCTION(gpio5, 0, ESWIN_PINMUX_MASK),
+	ESWIN_PINMUX_FUNCTION(gpio6, 2, ESWIN_PINMUX_MASK),
+	ESWIN_PINMUX_FUNCTION(gpio7, 2, ESWIN_PINMUX_MASK),
+	ESWIN_PINMUX_FUNCTION(gpio8, 2, ESWIN_PINMUX_MASK),
+	ESWIN_PINMUX_FUNCTION(gpio9, 2, ESWIN_PINMUX_MASK),
+
+	ESWIN_PINMUX_FUNCTION(gpio10, 2, ESWIN_PINMUX_MASK),
+	ESWIN_PINMUX_FUNCTION(gpio11, 0, ESWIN_PINMUX_MASK),
+	ESWIN_PINMUX_FUNCTION(gpio12, 2, ESWIN_PINMUX_MASK),
+	ESWIN_PINMUX_FUNCTION(gpio13, 2, ESWIN_PINMUX_MASK),
+	ESWIN_PINMUX_FUNCTION(gpio14, 2, ESWIN_PINMUX_MASK),
+	ESWIN_PINMUX_FUNCTION(gpio15, 2, ESWIN_PINMUX_MASK),
+	ESWIN_PINMUX_FUNCTION(gpio16, 2, ESWIN_PINMUX_MASK),
+	ESWIN_PINMUX_FUNCTION(gpio17, 2, ESWIN_PINMUX_MASK),
+	ESWIN_PINMUX_FUNCTION(gpio18, 2, ESWIN_PINMUX_MASK),
+	ESWIN_PINMUX_FUNCTION(gpio19, 2, ESWIN_PINMUX_MASK),
+
+	ESWIN_PINMUX_FUNCTION(gpio20, 2, ESWIN_PINMUX_MASK),
+	ESWIN_PINMUX_FUNCTION(gpio21, 2, ESWIN_PINMUX_MASK),
+	ESWIN_PINMUX_FUNCTION(gpio22, 2, ESWIN_PINMUX_MASK),
+	ESWIN_PINMUX_FUNCTION(gpio23, 2, ESWIN_PINMUX_MASK),
+	ESWIN_PINMUX_FUNCTION(gpio24, 2, ESWIN_PINMUX_MASK),
+	ESWIN_PINMUX_FUNCTION(gpio25, 2, ESWIN_PINMUX_MASK),
+	ESWIN_PINMUX_FUNCTION(gpio26, 2, ESWIN_PINMUX_MASK),
+	ESWIN_PINMUX_FUNCTION(gpio27, 0, ESWIN_PINMUX_MASK),
+	ESWIN_PINMUX_FUNCTION(gpio28, 0, ESWIN_PINMUX_MASK),
+	ESWIN_PINMUX_FUNCTION(gpio29, 2, ESWIN_PINMUX_MASK),
+
+	ESWIN_PINMUX_FUNCTION(gpio30, 2, ESWIN_PINMUX_MASK),
+	ESWIN_PINMUX_FUNCTION(gpio31, 2, ESWIN_PINMUX_MASK),
+	ESWIN_PINMUX_FUNCTION(gpio32, 2, ESWIN_PINMUX_MASK),
+	ESWIN_PINMUX_FUNCTION(gpio33, 2, ESWIN_PINMUX_MASK),
+	ESWIN_PINMUX_FUNCTION(gpio34, 2, ESWIN_PINMUX_MASK),
+	ESWIN_PINMUX_FUNCTION(gpio35, 2, ESWIN_PINMUX_MASK),
+	ESWIN_PINMUX_FUNCTION(gpio36, 2, ESWIN_PINMUX_MASK),
+	ESWIN_PINMUX_FUNCTION(gpio37, 2, ESWIN_PINMUX_MASK),
+	ESWIN_PINMUX_FUNCTION(gpio38, 2, ESWIN_PINMUX_MASK),
+	ESWIN_PINMUX_FUNCTION(gpio39, 2, ESWIN_PINMUX_MASK),
+
+	ESWIN_PINMUX_FUNCTION(gpio40, 2, ESWIN_PINMUX_MASK),
+	ESWIN_PINMUX_FUNCTION(gpio41, 2, ESWIN_PINMUX_MASK),
+	ESWIN_PINMUX_FUNCTION(gpio42, 2, ESWIN_PINMUX_MASK),
+	ESWIN_PINMUX_FUNCTION(gpio43, 2, ESWIN_PINMUX_MASK),
+	ESWIN_PINMUX_FUNCTION(gpio44, 2, ESWIN_PINMUX_MASK),
+	ESWIN_PINMUX_FUNCTION(gpio45, 2, ESWIN_PINMUX_MASK),
+	ESWIN_PINMUX_FUNCTION(gpio46, 2, ESWIN_PINMUX_MASK),
+	ESWIN_PINMUX_FUNCTION(gpio47, 2, ESWIN_PINMUX_MASK),
+	ESWIN_PINMUX_FUNCTION(gpio48, 2, ESWIN_PINMUX_MASK),
+	ESWIN_PINMUX_FUNCTION(gpio49, 2, ESWIN_PINMUX_MASK),
+
+	ESWIN_PINMUX_FUNCTION(gpio50, 2, ESWIN_PINMUX_MASK),
+	ESWIN_PINMUX_FUNCTION(gpio51, 2, ESWIN_PINMUX_MASK),
+	ESWIN_PINMUX_FUNCTION(gpio52, 2, ESWIN_PINMUX_MASK),
+	ESWIN_PINMUX_FUNCTION(gpio53, 2, ESWIN_PINMUX_MASK),
+	ESWIN_PINMUX_FUNCTION(gpio54, 2, ESWIN_PINMUX_MASK),
+	ESWIN_PINMUX_FUNCTION(gpio55, 2, ESWIN_PINMUX_MASK),
+	ESWIN_PINMUX_FUNCTION(gpio56, 2, ESWIN_PINMUX_MASK),
+	ESWIN_PINMUX_FUNCTION(gpio57, 2, ESWIN_PINMUX_MASK),
+	ESWIN_PINMUX_FUNCTION(gpio58, 2, ESWIN_PINMUX_MASK),
+	ESWIN_PINMUX_FUNCTION(gpio59, 2, ESWIN_PINMUX_MASK),
+
+	ESWIN_PINMUX_FUNCTION(gpio60, 2, ESWIN_PINMUX_MASK),
+	ESWIN_PINMUX_FUNCTION(gpio61, 2, ESWIN_PINMUX_MASK),
+	ESWIN_PINMUX_FUNCTION(gpio62, 2, ESWIN_PINMUX_MASK),
+	ESWIN_PINMUX_FUNCTION(gpio63, 2, ESWIN_PINMUX_MASK),
+	ESWIN_PINMUX_FUNCTION(gpio64, 2, ESWIN_PINMUX_MASK),
+	ESWIN_PINMUX_FUNCTION(gpio65, 2, ESWIN_PINMUX_MASK),
+	ESWIN_PINMUX_FUNCTION(gpio66, 2, ESWIN_PINMUX_MASK),
+	ESWIN_PINMUX_FUNCTION(gpio67, 2, ESWIN_PINMUX_MASK),
+	ESWIN_PINMUX_FUNCTION(gpio68, 2, ESWIN_PINMUX_MASK),
+	ESWIN_PINMUX_FUNCTION(gpio69, 2, ESWIN_PINMUX_MASK),
+
+	ESWIN_PINMUX_FUNCTION(gpio70, 2, ESWIN_PINMUX_MASK),
+	ESWIN_PINMUX_FUNCTION(gpio71, 2, ESWIN_PINMUX_MASK),
+	ESWIN_PINMUX_FUNCTION(gpio72, 2, ESWIN_PINMUX_MASK),
+	ESWIN_PINMUX_FUNCTION(gpio73, 2, ESWIN_PINMUX_MASK),
+	ESWIN_PINMUX_FUNCTION(gpio74, 2, ESWIN_PINMUX_MASK),
+	ESWIN_PINMUX_FUNCTION(gpio75, 2, ESWIN_PINMUX_MASK),
+	ESWIN_PINMUX_FUNCTION(gpio76, 2, ESWIN_PINMUX_MASK),
+	ESWIN_PINMUX_FUNCTION(gpio77, 2, ESWIN_PINMUX_MASK),
+	ESWIN_PINMUX_FUNCTION(gpio78, 2, ESWIN_PINMUX_MASK),
+	ESWIN_PINMUX_FUNCTION(gpio79, 2, ESWIN_PINMUX_MASK),
+
+	ESWIN_PINMUX_FUNCTION(gpio80, 2, ESWIN_PINMUX_MASK),
+	ESWIN_PINMUX_FUNCTION(gpio81, 2, ESWIN_PINMUX_MASK),
+	ESWIN_PINMUX_FUNCTION(gpio82, 2, ESWIN_PINMUX_MASK),
+	ESWIN_PINMUX_FUNCTION(gpio83, 2, ESWIN_PINMUX_MASK),
+	ESWIN_PINMUX_FUNCTION(gpio84, 2, ESWIN_PINMUX_MASK),
+	ESWIN_PINMUX_FUNCTION(gpio85, 2, ESWIN_PINMUX_MASK),
+	ESWIN_PINMUX_FUNCTION(gpio86, 2, ESWIN_PINMUX_MASK),
+	ESWIN_PINMUX_FUNCTION(gpio87, 2, ESWIN_PINMUX_MASK),
+	ESWIN_PINMUX_FUNCTION(gpio88, 2, ESWIN_PINMUX_MASK),
+	ESWIN_PINMUX_FUNCTION(gpio89, 2, ESWIN_PINMUX_MASK),
+
+	ESWIN_PINMUX_FUNCTION(gpio90, 2, ESWIN_PINMUX_MASK),
+	ESWIN_PINMUX_FUNCTION(gpio91, 2, ESWIN_PINMUX_MASK),
+	ESWIN_PINMUX_FUNCTION(gpio92, 2, ESWIN_PINMUX_MASK),
+	ESWIN_PINMUX_FUNCTION(gpio93, 2, ESWIN_PINMUX_MASK),
+	ESWIN_PINMUX_FUNCTION(gpio94, 2, ESWIN_PINMUX_MASK),
+	ESWIN_PINMUX_FUNCTION(gpio95, 2, ESWIN_PINMUX_MASK),
+	ESWIN_PINMUX_FUNCTION(gpio96, 2, ESWIN_PINMUX_MASK),
+	ESWIN_PINMUX_FUNCTION(gpio97, 2, ESWIN_PINMUX_MASK),
+	ESWIN_PINMUX_FUNCTION(gpio98, 2, ESWIN_PINMUX_MASK),
+	ESWIN_PINMUX_FUNCTION(gpio99, 2, ESWIN_PINMUX_MASK),
+
+	ESWIN_PINMUX_FUNCTION(gpio100, 2, ESWIN_PINMUX_MASK),
+	ESWIN_PINMUX_FUNCTION(gpio101, 2, ESWIN_PINMUX_MASK),
+	ESWIN_PINMUX_FUNCTION(gpio102, 2, ESWIN_PINMUX_MASK),
+	ESWIN_PINMUX_FUNCTION(gpio103, 2, ESWIN_PINMUX_MASK),
+	ESWIN_PINMUX_FUNCTION(gpio104, 2, ESWIN_PINMUX_MASK),
+	ESWIN_PINMUX_FUNCTION(gpio105, 2, ESWIN_PINMUX_MASK),
+	ESWIN_PINMUX_FUNCTION(gpio106, 0, ESWIN_PINMUX_MASK),
+	ESWIN_PINMUX_FUNCTION(gpio107, 2, ESWIN_PINMUX_MASK),
+	ESWIN_PINMUX_FUNCTION(gpio108, 2, ESWIN_PINMUX_MASK),
+	ESWIN_PINMUX_FUNCTION(gpio109, 2, ESWIN_PINMUX_MASK),
+	ESWIN_PINMUX_FUNCTION(gpio110, 2, ESWIN_PINMUX_MASK),
+	ESWIN_PINMUX_FUNCTION(gpio111, 0, ESWIN_PINMUX_MASK),
+
+	//func3
+	ESWIN_PINMUX_FUNCTION(uart4, 3, ESWIN_PINMUX_MASK),
+	ESWIN_PINMUX_FUNCTION(uart3, 3, ESWIN_PINMUX_MASK),
+
+	//func6
+	ESWIN_PINMUX_FUNCTION(csi_mon_out, 6, ESWIN_PINMUX_MASK),
+	ESWIN_PINMUX_FUNCTION(csi_ocla_clk, 6, ESWIN_PINMUX_MASK),
+	ESWIN_PINMUX_FUNCTION(csi_mon_out_valid, 6, ESWIN_PINMUX_MASK),
+	ESWIN_PINMUX_FUNCTION(csi_parity_error, 6, ESWIN_PINMUX_MASK),
+	ESWIN_PINMUX_FUNCTION(csi_dtb_out, 6, ESWIN_PINMUX_MASK),
+	ESWIN_PINMUX_FUNCTION(csi_phy_sel, 6, ESWIN_PINMUX_MASK),
+	ESWIN_PINMUX_FUNCTION(vc_g2d0_debug_out, 6, ESWIN_PINMUX_MASK),
+	ESWIN_PINMUX_FUNCTION(vc_g2d1_debug_out, 6, ESWIN_PINMUX_MASK),
+	ESWIN_PINMUX_FUNCTION(sata_mpll_clk, 6, ESWIN_PINMUX_MASK),
+	ESWIN_PINMUX_FUNCTION(sata_ref_repeat_clk_m, 6, ESWIN_PINMUX_MASK),
+	ESWIN_PINMUX_FUNCTION(sata_ref_repeat_clk_p, 6, ESWIN_PINMUX_MASK),
+};
+
+/* pinctrl */
+static int eswin_pctrl_get_groups_count(struct pinctrl_dev *pctldev)
+{
+	struct eswin_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
+	return pctrl->ngroups;
+}
+
+static const char *eswin_pctrl_get_group_name(struct pinctrl_dev *pctldev,
+						 unsigned int selector)
+{
+	struct eswin_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
+	return pctrl->groups[selector].name;
+}
+
+static int eswin_pctrl_get_group_pins(struct pinctrl_dev *pctldev,
+					 unsigned int selector,
+					 const unsigned int **pins,
+					 unsigned int *num_pins)
+{
+	struct eswin_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
+	*pins = pctrl->groups[selector].pins;
+	*num_pins = pctrl->groups[selector].npins;
+	return 0;
+}
+
+static const struct pinctrl_ops eswin_pinctrl_ops = {
+	.get_groups_count = eswin_pctrl_get_groups_count,
+	.get_group_name = eswin_pctrl_get_group_name,
+	.get_group_pins = eswin_pctrl_get_group_pins,
+	.dt_node_to_map = pinconf_generic_dt_node_to_map_all,
+	.dt_free_map = pinctrl_utils_free_map,
+};
+
+/* pinmux */
+static int eswin_pmux_get_functions_count(struct pinctrl_dev *pctldev)
+{
+	struct eswin_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
+
+	return pctrl->nfuncs;
+}
+
+static const char *eswin_pmux_get_function_name(struct pinctrl_dev *pctldev,
+						   unsigned int selector)
+{
+	struct eswin_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
+
+	return pctrl->funcs[selector].name;
+}
+
+static int eswin_pmux_get_function_groups(struct pinctrl_dev *pctldev,
+					 unsigned int selector,
+					 const char * const **groups,
+					 unsigned * const num_groups)
+{
+	struct eswin_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
+	*groups = pctrl->funcs[selector].groups;
+	*num_groups = pctrl->funcs[selector].ngroups;
+	return 0;
+}
+
+static int eswin_pinmux_set_mux(struct pinctrl_dev *pctldev,
+				   unsigned int function,
+				   unsigned int  group)
+{
+	int i ;
+	struct eswin_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
+	const struct eswin_group_desc *pgrp = &pctrl->groups[group];
+	const struct eswin_function_desc *func = &pctrl->funcs[function];
+
+	for(i = 0 ;i< pgrp->npins;i++){
+		u32 reg ;
+		unsigned int pin = pgrp->pins[i];
+		reg = readl(pctrl->base + 4*pin);
+		reg &= ~ESWIN_PINMUX_MASK;
+		reg |= (func->mux_val << ESWIN_PINMUX_SHIFT);
+		writel(reg,pctrl->base + 4*pin);
+	}
+	return 0;
+}
+
+static const struct pinmux_ops eswin_pinmux_ops = {
+	.get_functions_count = eswin_pmux_get_functions_count,
+	.get_function_name = eswin_pmux_get_function_name,
+	.get_function_groups = eswin_pmux_get_function_groups,
+	.set_mux = eswin_pinmux_set_mux,
+};
+
+/* pinconfig */
+static int eswin_pinconf_cfg_get(struct pinctrl_dev *pctldev,
+		   unsigned pin,
+			  unsigned long *config)
+{
+	u32 reg=0;
+	int ret=0;
+	unsigned int arg = 0;
+	unsigned int param = pinconf_to_config_param(*config);
+	struct eswin_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
+
+	if (pin >= ESWIN_MIO_NUM){
+		return -ENOTSUPP;
+	}
+	reg = readl(pctrl->base + 4*pin);
+	if (ret)
+		return -EIO;
+
+	switch (param) {
+	case PIN_CONFIG_BIAS_PULL_UP:
+	if (!(arg=(reg & ESWIN_PINCONF_PULLUP))){
+		return -EINVAL;}
+		break;
+	case PIN_CONFIG_BIAS_PULL_DOWN:
+	if (!(arg = (reg & ESWIN_PINCONF_PULLDOWN))){
+		return -EINVAL;}
+		break;
+	case PIN_CONFIG_DRIVE_STRENGTH:
+	arg = (reg & (ESWIN_PINCONF_DRIVER_STRENGTH_MASK
+						   <<ESWIN_PINCONF_DRIVER_SHIFT));
+		break;
+	case PIN_CONFIG_INPUT_ENABLE:
+	if (!(arg = (reg & ESWIN_PINCONF_IE))){
+		return -EINVAL;}
+	break;
+	case PIN_CONFIG_INPUT_SCHMITT:
+	if (!(arg = (reg & ESWIN_PINCONF_SMT))){
+		return -EINVAL;}
+	break;
+	default:
+	return -ENOTSUPP;
+	}
+	*config = pinconf_to_config_packed(param, arg);
+	return 0;
+}
+
+static int eswin_pinconf_cfg_set(struct pinctrl_dev *pctldev,
+			unsigned pin,
+			unsigned long *configs,
+			unsigned num_configs)
+{
+	int i=0, ret=0;
+	u32 reg = 0;
+	struct eswin_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
+
+	if (pin >= ESWIN_MIO_NUM)
+		return -ENOTSUPP;
+	reg = readl(pctrl->base + 4*pin);
+
+	if (ret)
+		return -EIO;
+
+	for (i = 0; i < num_configs; i++) {
+		unsigned int param = pinconf_to_config_param(configs[i]);
+		unsigned int arg = pinconf_to_config_argument(configs[i]);
+
+		switch (param) {
+			case PIN_CONFIG_INPUT_ENABLE:
+				reg &=~ESWIN_PINCONF_IE;
+				reg |= (arg<<0);
+				break;
+			case PIN_CONFIG_BIAS_PULL_UP:
+				reg &=~ESWIN_PINCONF_PULLUP;
+				reg |= (arg<<1);
+				break;
+			case PIN_CONFIG_BIAS_PULL_DOWN:
+				reg &=~ESWIN_PINCONF_PULLDOWN;
+				reg |= (arg<<2);
+				break;
+			case PIN_CONFIG_DRIVE_STRENGTH:
+				reg &= ~(ESWIN_PINCONF_DRIVER_STRENGTH_MASK<<3);
+				reg |= (arg<<3);
+				break;
+			case PIN_CONFIG_INPUT_SCHMITT:
+				reg &= ~ESWIN_PINCONF_SMT;
+				reg |= (arg<<7);
+				break;
+			default:
+				dev_warn(pctldev->dev,
+					"unsupported configuration parameter '%u'\n",
+					param);
+				continue;
+		}
+
+
+	}
+		writel(reg,pctrl->base + 4*pin);
+
+	if (ret)
+		return -EIO;
+	return 0;
+}
+
+static int eswin_pinconf_group_set(struct pinctrl_dev *pctldev,
+			unsigned selector,
+			unsigned long *configs,
+			unsigned num_configs)
+
+{
+	int i=0, ret=0;
+	struct eswin_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
+	const struct eswin_group_desc *pgrp = &pctrl->groups[selector];
+
+	for (i = 0; i < pgrp->npins; i++) {
+		ret = eswin_pinconf_cfg_set(pctldev, pgrp->pins[i], configs,
+					 num_configs);
+	if (ret)
+		  return ret;
+	}
+	return 0;
+}
+
+static const struct pinconf_ops eswin_pinconf_ops = {
+	.is_generic = true,
+	.pin_config_get = eswin_pinconf_cfg_get,
+	.pin_config_set = eswin_pinconf_cfg_set,
+	.pin_config_group_set = eswin_pinconf_group_set,
+};
+
+static struct pinctrl_desc eswin_desc = {
+	.name = "eswin_pinctrl",
+	.pins = eswin_pins,
+	.npins = ARRAY_SIZE(eswin_pins),
+	.pctlops = &eswin_pinctrl_ops,
+	.pmxops = &eswin_pinmux_ops,
+	.confops = &eswin_pinconf_ops,
+	.owner = THIS_MODULE,
+};
+
+static int eswin_pinctrl_probe(struct platform_device *pdev)
+{
+	struct resource *res;
+	struct eswin_pinctrl *pctrl;
+	pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL);
+	if (!pctrl)
+		return -ENOMEM;
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	if (!res)
+		return -ENODEV;
+	pctrl->base = devm_ioremap_resource(&pdev->dev, res);
+	if (IS_ERR(pctrl->base))
+		return PTR_ERR(pctrl->base);
+
+	pctrl->groups = eswin_pinctrl_groups;
+	pctrl->ngroups = ARRAY_SIZE(eswin_pinctrl_groups);
+	pctrl->funcs = eswin_pinmux_functions;
+	pctrl->nfuncs = ARRAY_SIZE(eswin_pinmux_functions);
+
+	pctrl->pctrl = devm_pinctrl_register(&pdev->dev, &eswin_desc, pctrl);
+	if (IS_ERR(pctrl->pctrl)){
+		return PTR_ERR(pctrl->pctrl);
+	}
+
+	platform_set_drvdata(pdev, pctrl);
+
+	dev_info(&pdev->dev, "eswin pinctrl initialized\n");
+
+	return 0;
+}
+
+static void eswin_pinctrl_remove(struct platform_device *platform_dev)
+{
+	struct eswin_pinctrl *eswin_pinctrl_ptr = platform_get_drvdata(platform_dev);
+	pinctrl_unregister(eswin_pinctrl_ptr->pctrl);
+}
+
+static const struct of_device_id eswin_pinctrl_of_match[] = {
+	{ .compatible = "eswin,eic7700-pinctrl" },
+	{ }
+};
+
+static struct platform_driver eswin_pinctrl_driver = {
+	.driver = {
+		.name = "eswin-pinctrl",
+		.of_match_table = eswin_pinctrl_of_match,
+	},
+	.probe = eswin_pinctrl_probe,
+	.remove = eswin_pinctrl_remove,
+};
+
+static int __init eswin_pinctrl_init(void)
+{
+	return platform_driver_register(&eswin_pinctrl_driver);
+}
+postcore_initcall(eswin_pinctrl_init);
+
+static void __exit eswin_pinctrl_exit(void)
+{
+	platform_driver_unregister(&eswin_pinctrl_driver);
+}
+module_exit(eswin_pinctrl_exit);
+
+MODULE_DESCRIPTION("ESWIN Pinctrl Controller Platform Device Drivers");
+MODULE_AUTHOR("luyulin@eswincomputing.com");
+MODULE_LICENSE("GPL");
diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig
index d9bcd1e8413e..b395b90ecc5e 100644
--- a/drivers/pwm/Kconfig
+++ b/drivers/pwm/Kconfig
@@ -231,6 +231,12 @@ config PWM_EP93XX
 	  To compile this driver as a module, choose M here: the module
 	  will be called pwm-ep93xx.
 
+config PWM_ESWIN
+	tristate "ESWIN PWM support"
+	help
+	  Generic PWM framework driver for the PWM controller found on
+	  ESWIN SoCs.
+
 config PWM_FSL_FTM
 	tristate "Freescale FlexTimer Module (FTM) PWM support"
 	depends on HAS_IOMEM
diff --git a/drivers/pwm/Makefile b/drivers/pwm/Makefile
index 96160f4257fc..0039372fa37d 100644
--- a/drivers/pwm/Makefile
+++ b/drivers/pwm/Makefile
@@ -19,6 +19,7 @@ obj-$(CONFIG_PWM_CROS_EC)	+= pwm-cros-ec.o
 obj-$(CONFIG_PWM_DWC_CORE)	+= pwm-dwc-core.o
 obj-$(CONFIG_PWM_DWC)		+= pwm-dwc.o
 obj-$(CONFIG_PWM_EP93XX)	+= pwm-ep93xx.o
+obj-$(CONFIG_PWM_ESWIN)	+= pwm-eswin.o
 obj-$(CONFIG_PWM_FSL_FTM)	+= pwm-fsl-ftm.o
 obj-$(CONFIG_PWM_GPIO)		+= pwm-gpio.o
 obj-$(CONFIG_PWM_HIBVT)		+= pwm-hibvt.o
diff --git a/drivers/pwm/pwm-eswin.c b/drivers/pwm/pwm-eswin.c
new file mode 100644
index 000000000000..ff949906939a
--- /dev/null
+++ b/drivers/pwm/pwm-eswin.c
@@ -0,0 +1,322 @@
+/*
+ * Copyright (c) 2022, ESWIN, Inc.
+ * Author: zhangchunyun@eswincomputing.com
+ */
+
+#include <linux/bitops.h>
+#include <linux/export.h>
+#include <linux/kernel.h>
+#include <linux/pm_runtime.h>
+#include <linux/clk.h>
+#include <linux/reset.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+#include <linux/pwm.h>
+#include <linux/time.h>
+#include <linux/pinctrl/pinctrl.h>
+#include <linux/pinctrl/pinmux.h>
+#include <linux/pinctrl/pinconf.h>
+#include <linux/pinctrl/pinconf-generic.h>
+
+#define	NUM_PWM_CHANNEL	3
+#define ESWIN_TIM_LD_CNT(n)   ((n) * 0x14)
+#define ESWIN_TIM_LD_CNT2(n)  (((n) * 4) + 0xb0)
+#define ESWIN_TIM_CUR_VAL(n)  (((n) * 0x14) + 0x04)
+#define ESWIN_TIM_CTRL(n)     (((n) * 0x14) + 0x08)
+#define ESWIN_TIM_EOI(n)      (((n) * 0x14) + 0x0c)
+#define ESWIN_TIM_INT_STS(n)  (((n) * 0x14) + 0x10)
+
+#define ESWIN_TIMERS_INT_STS  0xa0
+#define ESWIN_TIMERS_EOI      0xa4
+#define ESWIN_TIMERS_RAW_INT_STS  0xa8
+#define ESWIN_TIMERS_COMP_VERSION 0xac
+
+#define ESWIN_TIMERS_TOTAL    8
+#define NSEC_TO_SEC	1000000000
+
+/* Timer Control Register */
+#define ESWIN_TIM_CTRL_EN     BIT(0)
+#define ESWIN_TIM_CTRL_MODE   BIT(1)
+#define ESWIN_TIM_CTRL_MODE_FREE  (0 << 1)
+#define ESWIN_TIM_CTRL_MODE_USER  (1 << 1)
+#define ESWIN_TIM_CTRL_INT_MASK   BIT(2)
+#define ESWIN_TIM_CTRL_PWM    BIT(3)
+
+struct eswin_pwm_ctx {
+	u32 cnt;
+	u32 cnt2;
+	u32 ctrl;
+};
+
+struct eswin_pwm {
+	void __iomem *base;
+	struct clk *clk;
+	struct clk *pclk;
+	struct eswin_pwm_ctx ctx[ESWIN_TIMERS_TOTAL];
+	struct reset_control * pwm_rst;
+	u32 clk_period_ns;
+};
+
+#define to_eswin_pwm(p)   pwmchip_get_drvdata(p)
+
+static inline u32 eswin_pwm_readl(struct eswin_pwm *eswin, u32 offset)
+{
+	return readl(eswin->base + offset);
+}
+
+static inline void eswin_pwm_writel(struct eswin_pwm *eswin, u32 value, u32 offset)
+{
+	writel(value, eswin->base + offset);
+}
+
+static void __eswin_pwm_set_enable(struct eswin_pwm *eswin, int pwm, int enabled)
+{
+	u32 reg;
+
+	reg = eswin_pwm_readl(eswin, ESWIN_TIM_CTRL(pwm));
+
+	if (enabled)
+		reg |= ESWIN_TIM_CTRL_EN;
+	else
+		reg &= ~ESWIN_TIM_CTRL_EN;
+
+	eswin_pwm_writel(eswin, reg, ESWIN_TIM_CTRL(pwm));
+	reg = eswin_pwm_readl(eswin, ESWIN_TIM_CTRL(pwm));
+}
+
+static int __eswin_pwm_configure_timer(struct eswin_pwm *eswin,
+       struct pwm_device *pwm,
+       const struct pwm_state *state)
+{
+	u64 tmp;
+	u32 ctrl;
+	u32 high;
+	u32 low;
+
+	/*
+	¦* Calculate width of low and high period in terms of input clock
+	¦* periods and check are the result within HW limits between 1 and
+	¦* 2^32 periods.
+	¦*/
+
+	tmp = DIV_ROUND_CLOSEST_ULL(state->duty_cycle, eswin->clk_period_ns);
+	if (tmp < 1 || tmp > (1ULL << 32))
+              return -ERANGE;
+	high = tmp - 1;
+
+	tmp = DIV_ROUND_CLOSEST_ULL(state->period - state->duty_cycle,
+         eswin->clk_period_ns);
+	if (tmp < 1 || tmp > (1ULL << 32))
+        return -ERANGE;
+	low = tmp - 1;
+	/*
+	¦* Specification says timer usage flow is to disable timer, then
+	¦* program it followed by enable. It also says Load Count is loaded
+	¦* into timer after it is enabled - either after a disable or
+	¦* a reset. Based on measurements it happens also without disable
+	¦* whenever Load Count is updated. But follow the specification.
+	¦*/
+	__eswin_pwm_set_enable(eswin, pwm->hwpwm, false);
+
+	/*
+	¦* Write Load Count and Load Count 2 registers. Former defines the
+	¦* width of low period and latter the width of high period in terms
+	¦* multiple of input clock periods:
+	¦* Width = ((Count + 1) * input clock period).
+	¦*/
+	eswin_pwm_writel(eswin, low, ESWIN_TIM_LD_CNT(pwm->hwpwm));
+	eswin_pwm_writel(eswin, high, ESWIN_TIM_LD_CNT2(pwm->hwpwm));
+
+	/*
+	¦* Set user-defined mode, timer reloads from Load Count registers
+	¦* when it counts down to 0.
+	¦* Set PWM mode, it makes output to toggle and width of low and high
+	¦* periods are set by Load Count registers.
+	¦*/
+	ctrl = ESWIN_TIM_CTRL_MODE_USER | ESWIN_TIM_CTRL_PWM;
+	eswin_pwm_writel(eswin, ctrl, ESWIN_TIM_CTRL(pwm->hwpwm));
+
+	/*
+	¦* Enable timer. Output starts from low period.
+	¦*/
+	__eswin_pwm_set_enable(eswin, pwm->hwpwm, state->enabled);
+
+	return 0;
+}
+
+static int eswin_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
+	const struct pwm_state *state)
+{
+	struct eswin_pwm *eswin = to_eswin_pwm(chip);
+	struct pwm_state curstate;
+	int ret = 0;
+
+	ret = clk_enable(eswin->pclk);
+
+	ret = clk_enable(eswin->clk);
+
+	pwm_get_state(pwm, &curstate);
+
+	__eswin_pwm_configure_timer(eswin, pwm, state);
+
+	return 0;
+}
+
+static int eswin_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm,
+	struct pwm_state *state)
+{
+	struct eswin_pwm *eswin = to_eswin_pwm(chip);
+	u64 duty, period;
+
+	pm_runtime_get_sync(pwmchip_parent(chip));
+
+	state->enabled = !!(eswin_pwm_readl(eswin,
+		ESWIN_TIM_CTRL(pwm->hwpwm)) & ESWIN_TIM_CTRL_EN);
+
+	duty = eswin_pwm_readl(eswin, ESWIN_TIM_LD_CNT(pwm->hwpwm));
+	duty += 1;
+	duty *= eswin->clk_period_ns;
+	state->duty_cycle = duty;
+
+	period = eswin_pwm_readl(eswin, ESWIN_TIM_LD_CNT2(pwm->hwpwm));
+	period += 1;
+	period *= eswin->clk_period_ns;
+	period += duty;
+	state->period = period;
+
+	state->polarity = PWM_POLARITY_INVERSED;
+
+	pm_runtime_put_sync(pwmchip_parent(chip));
+
+	return 0;
+}
+
+
+static const struct pwm_ops eswin_pwm_ops = {
+	.get_state = eswin_pwm_get_state,
+	.apply = eswin_pwm_apply,
+};
+
+static const struct of_device_id eswin_pwm_dt_ids[] = {
+	{ .compatible = "eswin,pwm-eswin", },
+	{ /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, eswin_pwm_dt_ids);
+
+static int eswin_pwm_probe(struct platform_device *pdev)
+{
+	struct eswin_pwm *pc;
+	int ret, count;
+	struct resource *res;
+	int clk_rate;
+
+	struct pwm_chip *chip = devm_pwmchip_alloc(&pdev->dev, NUM_PWM_CHANNEL, sizeof(*pc));
+	if(IS_ERR(chip))
+		return PTR_ERR(chip);
+
+	pc = to_eswin_pwm(chip);
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	if (!res)
+		return -ENODEV;
+
+	pc->base = devm_ioremap_resource(&pdev->dev, res);
+	if (IS_ERR(pc->base))
+		return PTR_ERR(pc->base);
+
+	pc->clk = devm_clk_get(&pdev->dev, "pwm");
+	if (IS_ERR(pc->clk)) {
+		pc->clk = devm_clk_get(&pdev->dev, "pclk");
+        if (IS_ERR(pc->clk))
+			return dev_err_probe(&pdev->dev, PTR_ERR(pc->clk),
+                    "Can't get PWM clk\n");
+	}
+
+	count = of_count_phandle_with_args(pdev->dev.of_node,
+                      "clocks", "#clock-cells");
+	if (count == 2)
+		pc->pclk = devm_clk_get(&pdev->dev, "pclk");
+	else
+		pc->pclk = pc->clk;
+
+	if (IS_ERR(pc->pclk)) {
+		ret = PTR_ERR(pc->pclk);
+		if (ret != -EPROBE_DEFER)
+			dev_err(&pdev->dev, "Can't get APB clk: %d\n", ret);
+		return ret;
+	}
+
+	clk_rate = clk_get_rate(pc->pclk);
+	pc->clk_period_ns = DIV_ROUND_CLOSEST_ULL(NSEC_TO_SEC, clk_rate);
+
+	/* pwm reset init */
+	pc->pwm_rst = devm_reset_control_get_optional(&pdev->dev, "pwmrst");
+	if(IS_ERR_OR_NULL(pc->pwm_rst)) {
+		dev_err(&pdev->dev, "Failed to get pwmrst reset handle\n");
+		return -EFAULT;
+	}
+
+	ret = clk_prepare_enable(pc->clk);
+	if (ret) {
+		dev_err(&pdev->dev, "Can't prepare enable PWM clk: %d\n", ret);
+		return ret;
+	}
+
+	ret = clk_prepare_enable(pc->pclk);
+	if (ret) {
+		dev_err(&pdev->dev, "Can't prepare enable APB clk: %d\n", ret);
+		goto err_clk;
+	}
+
+	/* reset pwm */
+	ret = reset_control_assert(pc->pwm_rst);
+	WARN_ON(0 != ret);
+	ret = reset_control_deassert(pc->pwm_rst);
+	WARN_ON(0 != ret);
+
+	platform_set_drvdata(pdev, pc);
+
+	chip->ops = &eswin_pwm_ops;
+
+	ret = devm_pwmchip_add(&pdev->dev, chip);
+	if (ret < 0) {
+		dev_err(&pdev->dev, "pwmchip_add() failed: %d\n", ret);
+		goto err_pclk;
+	}
+
+	return 0;
+
+err_pclk:
+    clk_disable_unprepare(pc->pclk);
+err_clk:
+    clk_disable_unprepare(pc->clk);
+
+	return ret;
+}
+
+static void eswin_pwm_remove(struct platform_device *pdev)
+{
+	struct pwm_chip *chip = platform_get_drvdata(pdev);
+	struct eswin_pwm *pc = to_eswin_pwm(chip);
+
+	clk_disable_unprepare(pc->pclk);
+	clk_disable_unprepare(pc->clk);
+}
+
+static struct platform_driver eswin_pwm_driver = {
+	.driver = {
+		.name = "eswin-pwm",
+		.of_match_table = eswin_pwm_dt_ids,
+	},
+	.probe = eswin_pwm_probe,
+	.remove = eswin_pwm_remove,
+};
+module_platform_driver(eswin_pwm_driver);
+
+MODULE_DESCRIPTION("eswin SoC PWM driver");
+MODULE_AUTHOR("zhangchunyun@eswincomputing.com");
+MODULE_LICENSE("GPL");
+
diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig
index ec8c953cb73d..4289c87213b1 100644
--- a/drivers/reset/Kconfig
+++ b/drivers/reset/Kconfig
@@ -66,6 +66,12 @@ config RESET_BRCMSTB_RESCAL
 	  This enables the RESCAL reset controller for SATA, PCIe0, or PCIe1 on
 	  BCM7216 or the BCM2712.
 
+config RESET_ESWIN_EIC7700
+	tristate "Eswin EIC7700 Reset Driver"
+	default n
+	help
+	  This enables the reset controller driver for Eswin EIC7700 SoCs.
+
 config RESET_EYEQ
 	bool "Mobileye EyeQ reset controller"
 	depends on MACH_EYEQ5 || MACH_EYEQ6H || COMPILE_TEST
diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile
index 91e6348e3351..7de2778f1142 100644
--- a/drivers/reset/Makefile
+++ b/drivers/reset/Makefile
@@ -12,6 +12,7 @@ obj-$(CONFIG_RESET_BCM6345) += reset-bcm6345.o
 obj-$(CONFIG_RESET_BERLIN) += reset-berlin.o
 obj-$(CONFIG_RESET_BRCMSTB) += reset-brcmstb.o
 obj-$(CONFIG_RESET_BRCMSTB_RESCAL) += reset-brcmstb-rescal.o
+obj-$(CONFIG_RESET_ESWIN_EIC7700) += reset-eswin.o
 obj-$(CONFIG_RESET_EYEQ) += reset-eyeq.o
 obj-$(CONFIG_RESET_GPIO) += reset-gpio.o
 obj-$(CONFIG_RESET_HSDK) += reset-hsdk.o
diff --git a/drivers/reset/reset-eswin.c b/drivers/reset/reset-eswin.c
new file mode 100644
index 000000000000..3fda8842fc3b
--- /dev/null
+++ b/drivers/reset/reset-eswin.c
@@ -0,0 +1,259 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * ESWIN Reset Driver
+ *
+ * Copyright 2024, Beijing ESWIN Computing Technology Co., Ltd.. All rights reserved.
+ * SPDX-License-Identifier: GPL-2.0
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, version 2.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <https://www.gnu.org/licenses/>.
+ *
+ * Authors: HuangYiFeng<huangyifeng@eswincomputing.com>
+ */
+
+#include <linux/err.h>
+#include <linux/init.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+#include <linux/reset-controller.h>
+#include <linux/slab.h>
+#include <linux/types.h>
+#include <linux/regmap.h>
+#include <linux/mfd/syscon.h>
+
+#define SYSCRG_CLEAR_BOOT_INFO_OFFSET    (0x30C)
+#define CLEAR_BOOT_FLAG_BIT              BIT_ULL(0)
+#define SYSCRG_RESET_OFFSET              (0x400)
+
+/**
+ * struct eswin_reset_data - reset controller information structure
+ * @rcdev: reset controller entity
+ * @dev: reset controller device pointer
+ * @idr: idr structure for mapping ids to reset control structures
+ */
+struct eswin_reset_data {
+	struct reset_controller_dev rcdev;
+	struct device *dev;
+	struct idr idr;
+	struct regmap *regmap;
+};
+
+/**
+ * struct eswin_reset_control - reset control structure
+ * @dev_id: SoC-specific device identifier
+ * @reset_bit: reset mask to use for toggling reset
+ */
+struct eswin_reset_control {
+	u32 dev_id;
+	u32 reset_bit;
+};
+
+#define to_eswin_reset_data(p)	\
+	container_of((p), struct eswin_reset_data, rcdev)
+
+/**
+ * eswin_reset_set() - program a device's reset
+ * @rcdev: reset controller entity
+ * @id: ID of the reset to toggle
+ * @assert: boolean flag to indicate assert or deassert
+ *
+ * This is a common internal function used to assert or deassert a device's
+ * reset by clear and set the reset bit. The device's reset is asserted if the
+ * @assert argument is true, or deasserted if @assert argument is false.
+ *
+ * Return: 0 for successful request, else a corresponding error value
+ */
+static int eswin_reset_set(struct reset_controller_dev *rcdev,
+			    unsigned long id, bool assert)
+{
+	struct eswin_reset_data *data = to_eswin_reset_data(rcdev);
+	struct eswin_reset_control *control;
+	int ret;
+
+	control = idr_find(&data->idr, id);
+
+	dev_dbg(rcdev->dev, "dev_id 0x%x reset_bit 0x%x assert 0x%x\r\n",
+		control->dev_id, control->reset_bit, assert);
+
+	if (!control)
+		return -EINVAL;
+
+	if (assert) {
+		ret = regmap_clear_bits(data->regmap, SYSCRG_RESET_OFFSET + control->dev_id * sizeof(u32),
+			control->reset_bit);
+	} else {
+		ret = regmap_set_bits(data->regmap, SYSCRG_RESET_OFFSET + control->dev_id * sizeof(u32),
+			control->reset_bit);
+	}
+
+	return ret;
+}
+
+static int eswin_reset_reset(struct reset_controller_dev *rcdev,
+			      unsigned long id)
+{
+	int ret;
+
+	ret = eswin_reset_set(rcdev, id, true);
+	if (0 != ret) {
+		return ret;
+	}
+	usleep_range(10, 15);
+	ret = eswin_reset_set(rcdev, id, false);
+	if (0 != ret) {
+		return ret;
+	}
+
+	return 0;
+}
+
+static int eswin_reset_assert(struct reset_controller_dev *rcdev,
+			      unsigned long id)
+{
+	return eswin_reset_set(rcdev, id, true);
+}
+
+static int eswin_reset_deassert(struct reset_controller_dev *rcdev,
+				unsigned long id)
+{
+	return eswin_reset_set(rcdev, id, false);
+}
+
+static const struct reset_control_ops eswin_reset_ops = {
+	.reset		= eswin_reset_reset,
+	.assert		= eswin_reset_assert,
+	.deassert	= eswin_reset_deassert,
+};
+
+static int eswin_reset_of_xlate_lookup_id(int id, void *p, void *data)
+{
+	struct of_phandle_args *reset_spec = (struct of_phandle_args *)data;
+	struct eswin_reset_control *slot_control = (struct eswin_reset_control *)p;
+
+	if (reset_spec->args[0] == slot_control->dev_id
+		&& reset_spec->args[1] == slot_control->reset_bit) {
+			return id;
+	} else {
+		return 0;
+	}
+}
+
+/**
+ * eswin_reset_of_xlate() - translate a set of OF arguments to a reset ID
+ * @rcdev: reset controller entity
+ * @reset_spec: OF reset argument specifier
+ *
+ * This function performs the translation of the reset argument specifier
+ * values defined in a reset consumer device node. The function allocates a
+ * reset control structure for that device reset, and will be used by the
+ * driver for performing any reset functions on that reset. An idr structure
+ * is allocated and used to map to the reset control structure. This idr
+ * is used by the driver to do reset lookups.
+ *
+ * Return: 0 for successful request, else a corresponding error value
+ */
+static int eswin_reset_of_xlate(struct reset_controller_dev *rcdev,
+				 const struct of_phandle_args *reset_spec)
+{
+	struct eswin_reset_data *data = to_eswin_reset_data(rcdev);
+	struct eswin_reset_control *control;
+	int ret;
+
+	if (WARN_ON(reset_spec->args_count != rcdev->of_reset_n_cells))
+		return -EINVAL;
+
+	ret = idr_for_each(&data->idr, eswin_reset_of_xlate_lookup_id, (void *)reset_spec);
+	if (0 != ret) {
+		return ret;
+	}
+
+	control = devm_kzalloc(data->dev, sizeof(*control), GFP_KERNEL);
+	if (!control)
+		return -ENOMEM;
+
+	control->dev_id = reset_spec->args[0];
+	control->reset_bit = reset_spec->args[1];
+
+	return idr_alloc(&data->idr, control, 0, 0, GFP_KERNEL);
+}
+
+static const struct of_device_id eswin_reset_dt_ids[] = {
+	 { .compatible = "eswin,eic7700-reset", },
+	 { /* sentinel */ },
+};
+
+static int eswin_reset_probe(struct platform_device *pdev)
+{
+	struct eswin_reset_data *data;
+	struct device *parent;
+
+	parent = pdev->dev.parent;
+	if (!parent) {
+		dev_err(&pdev->dev, "no parent\n");
+		return -ENODEV;
+	}
+
+	data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
+	if (!data)
+		return -ENOMEM;
+
+	data->regmap = syscon_node_to_regmap(parent->of_node);
+	if (IS_ERR(data->regmap)) {
+		dev_err(&pdev->dev, "failed to get parent regmap\n");
+		return PTR_ERR(data->regmap);
+	}
+
+	platform_set_drvdata(pdev, data);
+
+	data->rcdev.owner = THIS_MODULE;
+	data->rcdev.ops = &eswin_reset_ops;
+	data->rcdev.of_node = pdev->dev.of_node;
+	data->rcdev.of_reset_n_cells = 2;
+	data->rcdev.of_xlate = eswin_reset_of_xlate;
+	data->rcdev.dev = &pdev->dev;
+	data->dev = &pdev->dev;
+	idr_init(&data->idr);
+
+	/*clear boot flag so u84 and scpu could be reseted by software*/
+	regmap_set_bits(data->regmap, SYSCRG_CLEAR_BOOT_INFO_OFFSET, CLEAR_BOOT_FLAG_BIT);
+	msleep(50);
+
+	platform_set_drvdata(pdev, data);
+
+	return devm_reset_controller_register(&pdev->dev, &data->rcdev);
+}
+
+static void eswin_reset_remove(struct platform_device *pdev)
+{
+	struct eswin_reset_data *data = platform_get_drvdata(pdev);
+
+	idr_destroy(&data->idr);
+}
+
+static struct platform_driver eswin_reset_driver = {
+	.probe	= eswin_reset_probe,
+	.remove = eswin_reset_remove,
+	.driver = {
+		.name		= "eswin-reset",
+		.of_match_table	= eswin_reset_dt_ids,
+	},
+};
+
+static int __init eic7700_reset_init(void)
+{
+	return platform_driver_register(&eswin_reset_driver);
+}
+arch_initcall(eic7700_reset_init);
+
+MODULE_AUTHOR("Huangyifeng <huangyifeng@eswincomputing.com>");
+MODULE_DESCRIPTION("Eswin Reset Controller Driver for EIC770X SoCs");
+MODULE_LICENSE("GPL v2");
diff --git a/drivers/rtc/Kconfig b/drivers/rtc/Kconfig
index 9aec922613ce..dcbc218c6f77 100644
--- a/drivers/rtc/Kconfig
+++ b/drivers/rtc/Kconfig
@@ -316,6 +316,15 @@ config RTC_DRV_DS1672
 	  This driver can also be built as a module. If so, the module
 	  will be called rtc-ds1672.
 
+config RTC_DRV_ESWIN
+	tristate "eswin EIC7700 RTC"
+	help
+	  If you say yes here you get support for the eswin EIC7700 real time
+	  clock.
+
+	  This driver can also be built as a module, if so, the module
+	  will be called "rtc-eswin".
+
 config RTC_DRV_HYM8563
 	tristate "Haoyu Microelectronics HYM8563"
 	depends on OF
diff --git a/drivers/rtc/Makefile b/drivers/rtc/Makefile
index 4619aa2ac469..695989276cd3 100644
--- a/drivers/rtc/Makefile
+++ b/drivers/rtc/Makefile
@@ -68,6 +68,7 @@ obj-$(CONFIG_RTC_DRV_DS3232)	+= rtc-ds3232.o
 obj-$(CONFIG_RTC_DRV_EFI)	+= rtc-efi.o
 obj-$(CONFIG_RTC_DRV_EM3027)	+= rtc-em3027.o
 obj-$(CONFIG_RTC_DRV_EP93XX)	+= rtc-ep93xx.o
+obj-$(CONFIG_RTC_DRV_ESWIN)	+= rtc-eswin.o
 obj-$(CONFIG_RTC_DRV_FM3130)	+= rtc-fm3130.o
 obj-$(CONFIG_RTC_DRV_FSL_FTM_ALARM)	+= rtc-fsl-ftm-alarm.o
 obj-$(CONFIG_RTC_DRV_FTRTC010)	+= rtc-ftrtc010.o
diff --git a/drivers/rtc/rtc-eswin.c b/drivers/rtc/rtc-eswin.c
new file mode 100644
index 000000000000..388a0968e53a
--- /dev/null
+++ b/drivers/rtc/rtc-eswin.c
@@ -0,0 +1,321 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * ESWIN rtc driver
+ *
+ * Copyright 2024, Beijing ESWIN Computing Technology Co., Ltd.. All rights reserved.
+ * SPDX-License-Identifier: GPL-2.0
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, version 2.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <https://www.gnu.org/licenses/>.
+ *
+ * Author: zhangpengcheng@eswincomputing.com
+ */
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+#include <linux/io.h>
+#include <linux/slab.h>
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/rtc.h>
+#include <linux/reset.h>
+#include <linux/regmap.h>
+#include <linux/mfd/syscon.h>
+
+#define RTC_INT_TO_U84  0xffff9fff
+/* RTC CSR Registers */
+#define RTC_CCVR        0x00
+#define RTC_CMR         0x04
+#define RTC_CLR         0x08
+#define RTC_CCR         0x0C
+#define RTC_CCR_IE      BIT(0)
+#define RTC_CCR_MASK    BIT(1)
+#define RTC_CCR_EN      BIT(2)
+#define RTC_CCR_WEN     BIT(3)
+#define RTC_CCR_PEN     BIT(4)
+#define RTC_STAT        0x10
+#define RTC_STAT_BIT    BIT(0)
+#define RTC_RSTAT       0x14
+#define RTC_EOI         0x18
+#define RTC_VER         0x1C
+#define RTC_CPSR        0x20
+#define RTC_CPCVR       0x24
+
+struct eswin_rtc_dev {
+	struct rtc_device *rtc;
+	struct device *dev;
+	unsigned long alarm_time;
+	void __iomem *csr_base;
+	struct clk *clk;
+	unsigned int irq_wake;
+	struct reset_control *rst_rtc;
+};
+
+static int eswin_rtc_read_time(struct device *dev, struct rtc_time *tm)
+{
+	struct eswin_rtc_dev *pdata = dev_get_drvdata(dev);
+	rtc_time64_to_tm(readl(pdata->csr_base + RTC_CCVR), tm);
+	return rtc_valid_tm(tm);
+}
+
+static int eswin_rtc_set_time(struct device *dev, struct rtc_time *tm)
+{
+	struct eswin_rtc_dev *pdata = dev_get_drvdata(dev);
+	unsigned long tr;
+
+	tr = rtc_tm_to_time64(tm);
+	writel(tr, pdata->csr_base + RTC_CLR);
+	readl(pdata->csr_base + RTC_CLR); /* Force a barrier */
+
+	return 0;
+}
+
+static int eswin_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
+{
+	struct eswin_rtc_dev *pdata = dev_get_drvdata(dev);
+	rtc_time64_to_tm(pdata->alarm_time, &alrm->time);
+	alrm->enabled = readl(pdata->csr_base + RTC_CCR) & RTC_CCR_IE;
+
+	return 0;
+}
+
+static int eswin_rtc_alarm_irq_enable(struct device *dev, u32 enabled)
+{
+	struct eswin_rtc_dev *pdata = dev_get_drvdata(dev);
+	u32 ccr;
+
+	ccr = readl(pdata->csr_base + RTC_CCR);
+	if (enabled) {
+		ccr &= ~RTC_CCR_MASK;
+		ccr |= RTC_CCR_IE;
+	} else {
+		ccr &= ~RTC_CCR_IE;
+		ccr |= RTC_CCR_MASK;
+	}
+	writel(ccr, pdata->csr_base + RTC_CCR);
+
+	return 0;
+}
+
+static int eswin_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
+{
+	struct eswin_rtc_dev *pdata = dev_get_drvdata(dev);
+	unsigned long rtc_time;
+	unsigned long alarm_time;
+	rtc_time = readl(pdata->csr_base + RTC_CCVR);
+	alarm_time = rtc_tm_to_time64(&alrm->time);
+
+	pdata->alarm_time = alarm_time;
+	writel((u32) pdata->alarm_time, pdata->csr_base + RTC_CMR);
+
+	eswin_rtc_alarm_irq_enable(dev, alrm->enabled);
+
+	return 0;
+}
+
+static const struct rtc_class_ops eswin_rtc_ops = {
+	.read_time  = eswin_rtc_read_time,
+	.set_time   = eswin_rtc_set_time,
+	.read_alarm = eswin_rtc_read_alarm,
+	.set_alarm  = eswin_rtc_set_alarm,
+	.alarm_irq_enable = eswin_rtc_alarm_irq_enable,
+};
+
+static irqreturn_t eswin_rtc_interrupt(int irq, void *id)
+{
+	struct eswin_rtc_dev *pdata = (struct eswin_rtc_dev *) id;
+	/* Check if interrupt asserted */
+	if (!(readl(pdata->csr_base + RTC_STAT) & RTC_STAT_BIT))
+		return IRQ_NONE;
+
+	/* Clear interrupt */
+	readl(pdata->csr_base + RTC_EOI);
+
+	rtc_update_irq(pdata->rtc, 1, RTC_IRQF | RTC_AF);
+
+	return IRQ_HANDLED;
+}
+
+static int eswin_rtc_probe(struct platform_device *pdev)
+{
+	struct eswin_rtc_dev *pdata;
+	struct resource *res;
+	int ret;
+	int irq;
+	unsigned int reg_val;
+	unsigned int int_off;
+	unsigned int clk_freq;
+	struct regmap *regmap;
+	pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
+	if (!pdata)
+		return -ENOMEM;
+	platform_set_drvdata(pdev, pdata);
+	pdata->dev = &pdev->dev;
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	pdata->csr_base = devm_ioremap_resource(&pdev->dev, res);
+	if (IS_ERR(pdata->csr_base))
+		return PTR_ERR(pdata->csr_base);
+
+	irq = platform_get_irq(pdev, 0);
+	if (irq < 0) {
+		dev_err(&pdev->dev, "No IRQ resource\n");
+		return irq;
+	}
+	ret = devm_request_irq(&pdev->dev, irq, eswin_rtc_interrupt, 0,
+                   dev_name(&pdev->dev), pdata);
+	if (ret) {
+		dev_err(&pdev->dev, "Could not request IRQ\n");
+		return ret;
+	}
+
+	/* update RTC interrupt to u84 */
+	regmap = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, "eswin,syscfg");
+	if (IS_ERR(regmap)) {
+		dev_err(&pdev->dev, "No syscfg phandle specified\n");
+		return PTR_ERR(regmap);
+	}
+
+	ret = of_property_read_u32_index(pdev->dev.of_node, "eswin,syscfg", 1, &int_off);
+	if (ret) {
+		dev_err(&pdev->dev, "No rtc interrupt offset found\n");
+		return -1;
+	}
+	regmap_read(regmap, int_off, &reg_val);
+	reg_val &= (RTC_INT_TO_U84);
+	regmap_write(regmap, int_off, reg_val);
+
+	ret = of_property_read_u32(pdev->dev.of_node, "clock-frequency", &clk_freq);
+	if (ret) {
+		dev_err(&pdev->dev, "No rtc clock-frequency found\n");
+	}
+	/* rtc reset init*/
+	pdata->rst_rtc = devm_reset_control_get_optional(&pdev->dev, "rtcrst");
+	if (IS_ERR_OR_NULL(pdata->rst_rtc)) {
+		dev_err(&pdev->dev, "Failed to get rtcrst reset handle\n");
+		return -EFAULT;
+	}
+
+	/* get RTC clock */
+	pdata->clk = devm_clk_get(&pdev->dev, "rtcclk");
+	if (IS_ERR(pdata->clk)) {
+		dev_err(&pdev->dev, "Couldn't get the clock for RTC\n");
+		return -ENODEV;
+	}
+	/* Enable the clock */
+	clk_prepare_enable(pdata->clk);
+	if (ret) {
+		dev_err(&pdev->dev, "failed to enable RTC clock: %d\n", ret);
+		return -ENODEV;
+	}
+	/* reset rtc */
+	ret = reset_control_assert(pdata->rst_rtc);
+	WARN_ON(0 != ret);
+	ret = reset_control_deassert(pdata->rst_rtc);
+	WARN_ON(0 != ret);
+
+	/* Turn on the clock and the crystal */
+	reg_val = readl(pdata->csr_base + RTC_CCR);
+	writel(RTC_CCR_EN | reg_val, pdata->csr_base + RTC_CCR);
+
+	/* Turn on the prescaler and set the value */
+	writel(clk_freq, pdata->csr_base + RTC_CPSR);
+	reg_val = readl(pdata->csr_base + RTC_CCR);
+	writel(RTC_CCR_PEN | reg_val, pdata->csr_base + RTC_CCR);
+
+	device_init_wakeup(&pdev->dev, 1);
+
+	pdata->rtc = devm_rtc_device_register(&pdev->dev, pdev->name,
+                     &eswin_rtc_ops, THIS_MODULE);
+	if (IS_ERR(pdata->rtc)) {
+		clk_disable_unprepare(pdata->clk);
+		return PTR_ERR(pdata->rtc);
+	}
+
+	return 0;
+}
+
+static void eswin_rtc_remove(struct platform_device *pdev)
+{
+	struct eswin_rtc_dev *pdata = platform_get_drvdata(pdev);
+
+	eswin_rtc_alarm_irq_enable(&pdev->dev, 0);
+	device_init_wakeup(&pdev->dev, 0);
+	clk_disable_unprepare(pdata->clk);
+}
+
+#ifdef CONFIG_PM_SLEEP
+static int eswin_rtc_suspend(struct device *dev)
+{
+	struct platform_device *pdev = to_platform_device(dev);
+	struct eswin_rtc_dev *pdata = platform_get_drvdata(pdev);
+	int irq;
+
+	irq = platform_get_irq(pdev, 0);
+	if (device_may_wakeup(&pdev->dev)) {
+		if (!enable_irq_wake(irq))
+			pdata->irq_wake = 1;
+	} else {
+		eswin_rtc_alarm_irq_enable(dev, 0);
+		clk_disable(pdata->clk);
+	}
+
+	return 0;
+}
+
+static int eswin_rtc_resume(struct device *dev)
+{
+	struct platform_device *pdev = to_platform_device(dev);
+	struct eswin_rtc_dev *pdata = platform_get_drvdata(pdev);
+	int irq;
+
+	irq = platform_get_irq(pdev, 0);
+	if (device_may_wakeup(&pdev->dev)) {
+		if (pdata->irq_wake) {
+			disable_irq_wake(irq);
+			pdata->irq_wake = 0;
+		}
+	} else {
+		clk_enable(pdata->clk);
+		eswin_rtc_alarm_irq_enable(dev, 1);
+	}
+
+	return 0;
+}
+#endif
+
+static SIMPLE_DEV_PM_OPS(eswin_rtc_pm_ops, eswin_rtc_suspend, eswin_rtc_resume);
+
+#ifdef CONFIG_OF
+static const struct of_device_id eswin_rtc_of_match[] = {
+	{.compatible = "eswin,eic7700-rtc" },
+	{ }
+};
+MODULE_DEVICE_TABLE(of, eswin_rtc_of_match);
+#endif
+
+static struct platform_driver eswin_rtc_driver = {
+	.probe      = eswin_rtc_probe,
+	.remove     = eswin_rtc_remove,
+	.driver     = {
+		.name   = "eswin-rtc",
+		.pm = &eswin_rtc_pm_ops,
+		.of_match_table = of_match_ptr(eswin_rtc_of_match),
+	},
+};
+
+module_platform_driver(eswin_rtc_driver);
+
+MODULE_DESCRIPTION("eswin eic7700 RTC driver");
+MODULE_AUTHOR("zhangpengcheng@eswin.com>");
+MODULE_LICENSE("GPL");
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index c51da3fc3604..c10c1cedfd68 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -392,6 +392,12 @@ config SPI_EP93XX
 	  This enables using the Cirrus EP93xx SPI controller in master
 	  mode.
 
+config SPI_ESWIN_BOOTSPI
+	tristate "Eswin Computing Boot SPI controller"
+	help
+	  This enables using the Eswin Computing Boot SPI controller in master
+	  mode.
+
 config SPI_FALCON
 	bool "Falcon SPI controller support"
 	depends on SOC_FALCON
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index 4ea89f6fc531..f01b4533ec2e 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -54,6 +54,7 @@ obj-$(CONFIG_SPI_DW_BT1)		+= spi-dw-bt1.o
 obj-$(CONFIG_SPI_DW_MMIO)		+= spi-dw-mmio.o
 obj-$(CONFIG_SPI_DW_PCI)		+= spi-dw-pci.o
 obj-$(CONFIG_SPI_EP93XX)		+= spi-ep93xx.o
+obj-$(CONFIG_SPI_ESWIN_BOOTSPI)	+= spi-eswin-bootspi.o
 obj-$(CONFIG_SPI_FALCON)		+= spi-falcon.o
 obj-$(CONFIG_SPI_FSI)			+= spi-fsi.o
 obj-$(CONFIG_SPI_FSL_CPM)		+= spi-fsl-cpm.o
diff --git a/drivers/spi/spi-eswin-bootspi.c b/drivers/spi/spi-eswin-bootspi.c
new file mode 100644
index 000000000000..b8f858939011
--- /dev/null
+++ b/drivers/spi/spi-eswin-bootspi.c
@@ -0,0 +1,646 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * ESWIN BootSpi Driver
+ *
+ * Copyright 2024, Beijing ESWIN Computing Technology Co., Ltd.. All rights reserved.
+ * SPDX-License-Identifier: GPL-2.0
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, version 2.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <https://www.gnu.org/licenses/>.
+ *
+ * Authors: HuangYiFeng<huangyifeng@eswincomputing.com>
+ */
+
+#include <linux/clk.h>
+#include <linux/reset.h>
+#include <linux/bitfield.h>
+#include <linux/interrupt.h>
+#include <linux/iopoll.h>
+#include <linux/module.h>
+#include <linux/mod_devicetable.h>
+#include <linux/platform_device.h>
+#include <linux/slab.h>
+#include <linux/spi/spi.h>
+#include <linux/spi/spi-mem.h>
+#include <linux/mtd/spi-nor.h>
+
+/* Register offsets */
+#define ES_SPI_CSR_00			0x00	/*WRITE_STATUS_REG_TIME*/
+#define ES_SPI_CSR_01			0x04	/*SPI_BUS_MODE*/
+#define ES_SPI_CSR_02			0x08	/*ERASE_COUNTER_TAP*/
+#define ES_SPI_CSR_03			0x0c	/*DMA_EN_HCLK_STATUS*/
+#define ES_SPI_CSR_04			0x10	/*FAST_READ_CONTROL*/
+#define ES_SPI_CSR_05			0x14	/*SPI_FLASH_WR_NUM*/
+#define ES_SPI_CSR_06			0x18	/*SPI_FLASH_COMMAND*/
+#define ES_SPI_CSR_07			0x1c	/*INTERRUPT_CONTROL*/
+#define ES_SPI_CSR_08			0x20	/*DMA_REQUEST_TAP*/
+#define ES_SPI_CSR_09			0x24	/*SPI_FLASH_WR_ADDRESS*/
+#define ES_SPI_CSR_10			0x28	/*PAGE_PROGRAM_TIME*/
+#define ES_SPI_CSR_11			0x2c	/*SECTOR_ERASE_TIME*/
+#define ES_SPI_CSR_12			0x30	/*SMALL_BLOCK_ERASE_TIME*/
+#define ES_SPI_CSR_13			0x34	/*LARGE_BLOCK_ERASE_TIME*/
+#define ES_SPI_CSR_14			0x38	/*CHIP_ERASE_TIME*/
+#define ES_SPI_CSR_15			0x3c	/*CHIP_DESELECT_TIME*/
+#define ES_SPI_CSR_16			0x40	/*POWER_DOWN_TIME*/
+
+#define ES_SYSCSR_SPIMODECFG			0x340
+
+#define ES_CONCSR_SPI_INTSEL			0x3c0
+
+#define SPI_COMMAND_VALID				0x01
+#define SPI_COMMAND_MOVE_VALUE			0x00
+#define SPI_COMMAND_CODE_FIELD_POSITION 0X06
+#define SPI_COMMAND_MOVE_FIELD_POSITION 0X05
+#define SPI_COMMAND_TYPE_FIELD_POSITION 0X01
+
+/* Bit fields in CTRLR0 */
+/*
+ * Only present when SSI_MAX_XFER_SIZE=16. This is the default, and the only
+ * option before version 3.23a.
+ */
+#define SPI_INTSEL_MASK			GENMASK(11, 10)
+#define INT_ROUTED_U84			0x0
+#define INT_ROUTED_LPCPU		0x1
+#define INT_ROUTED_SCPU			0x3u
+
+#define RX_TIMEOUT			5000		/* timeout in ms */
+
+#define SPI_COMMAND_INIT_VALUE       0XFFFFC000
+#define FLASH_PAGE_SIZE      0x100
+
+typedef enum {
+	SPI_FLASH_WR_BYTE  = 1,
+	SPI_FLASH_WR_2BYTE = 2,
+	SPI_FLASH_WR_WORD  = 4,
+} SPI_FLASH_WR_NUM_T;
+
+typedef enum {
+	SPI_FAST_READ_DEFAULT = 0,
+	SPI_FAST_READ_ENABLE  = 3 /*WHEN SPI QUAD0 OR DUAL MODE*/
+} SPI_FAST_READ_CTL_T;
+
+typedef enum { STANDARD_SPI = 0, DUAL_SPI, QUAD_SPI } SPI_BUS_MODE_T;
+
+typedef enum {
+	SPIC_CMD_TYPE_SPI_PROGRAM = 0,
+	SPIC_CMD_TYPE_WRITE_STATUS_REGISTER,
+	SPIC_CMD_TYPE_READ_STATUS_REGISTER,
+	SPIC_CMD_TYPE_SECTOR_ERASE,
+	SPIC_CMD_TYPE_BLOCK_ERASE_TYPE1,
+	SPIC_CMD_TYPE_BLOCK_ERASE_TYPE2,
+	SPIC_CMD_TYPE_CHIP_ERASE,
+	SPIC_CMD_TYPE_POWER_DOWN,
+	SPIC_CMD_TYPE_RELEASE_POWER_DOWM,
+	SPIC_CMD_TYPE_ENTER_OR_EXIT_32BIT_MODE,
+	SPIC_CMD_TYPE_READ_SECURITY_REG,
+	SPIC_CMD_TYPE_ERASE_SECURITY_REG,
+	SPIC_CMD_TYPE_WRITE_SECURITY_REG,
+	SPIC_CMD_TYPE_READ_DATA,
+	SPIC_CMD_TYPE_READ_MANUFACTURED_ID,
+	SPIC_CMD_TYPE_READ_JEDEC_ID
+} SPI_FLASH_COMMAND_TYPE_T;
+
+#define SPIC_CMD_CODE_POWER_DOWN              0xb9
+#define SPIC_CMD_CODE_RELEASE_POWER_DOWN       0xab
+#define SPIC_CMD_CODE_ENABLE_RESET            0x66
+#define SPIC_CMD_CODE_RESET                   0x99
+
+struct es_spi_priv {
+	struct clk *cfg_clk;
+	struct clk *clk;
+	struct reset_control *rstc;
+	struct gpio_desc *cs_gpio;	/* External chip-select gpio */
+
+	void __iomem *regs;
+	void __iomem *sys_regs;
+	void __iomem *flash_base;
+	unsigned int freq;		/* Default frequency */
+	unsigned int mode;
+
+	const void *tx;
+	u32 opcode;
+	u32 cmd_type;
+	u64 addr;
+	void *rx;
+	u32 fifo_len;			/* depth of the FIFO buffer */
+	u32 max_xfer;			/* Maximum transfer size (in bits) */
+
+	int bits_per_word;
+	int len;
+	u8 cs;				/* chip select pin */
+	u8 tmode;			/* TR/TO/RO/EEPROM */
+	u8 type;			/* SPI/SSP/MicroWire */
+	struct spi_controller *controller;
+	struct device *dev;
+	int irq;
+};
+
+static inline u32 eswin_bootspi_read(struct es_spi_priv *priv, u32 offset)
+{
+	return readl(priv->regs + offset);
+}
+
+static inline void eswin_bootspi_write(struct es_spi_priv *priv, u32 offset, u32 val)
+{
+	writel(val, priv->regs + offset);
+}
+
+static inline u32 eswin_bootspi_data_read(struct es_spi_priv *priv, u32 offset)
+{
+	return readl(priv->flash_base + offset);
+}
+
+static inline void eswin_bootspi_data_write(struct es_spi_priv *priv, u32 offset, u32 val)
+{
+	writel(val, priv->flash_base + offset);
+}
+
+static int eswin_bootspi_wait_over(struct es_spi_priv *priv)
+{
+	u32 val;
+	struct device *dev = priv->dev;
+
+	if (readl_poll_timeout(priv->regs + ES_SPI_CSR_06, val,
+		(!(val & 0x1)), 10, RX_TIMEOUT * 1000)) {
+			dev_err(dev, "eswin_bootspi_wait_over : timeout!!\n");
+			return -ETIMEDOUT;
+	}
+	return 0;
+}
+
+/**
+ * @brief spi read and write cfg
+ */
+static void eswin_bootspi_read_write_cfg(struct es_spi_priv *priv, u32 byte, u32 addr)
+{
+	eswin_bootspi_write(priv, ES_SPI_CSR_09, addr);
+	eswin_bootspi_write(priv, ES_SPI_CSR_05, byte);
+	eswin_bootspi_write(priv, ES_SPI_CSR_04, SPI_FAST_READ_DEFAULT);
+	eswin_bootspi_write(priv, ES_SPI_CSR_01, STANDARD_SPI);
+}
+
+/**
+ *  @brief write data from dest address to flash
+ */
+static void eswin_bootspi_send_data(struct es_spi_priv *priv,
+	const u8 *dest, u32 size)
+{
+	u32 offset = 0;
+	u8 *buff = (u8 *)dest;
+	u32 data = 0;
+	int i;
+	struct device *dev = priv->dev;
+
+	dev_dbg(dev,"wrtie spi data\n");
+	while (size >= SPI_FLASH_WR_WORD) {
+		data = (buff[0]) | (buff[1] << 8) |(buff[2] << 16) | (buff[3] << 24);
+		for (i = 0; i < 4; i++) {
+			dev_dbg(dev,"0x%x ", buff[i]);
+		}
+		dev_dbg(dev,"0x%x ", data);
+		eswin_bootspi_data_write(priv, offset, data);
+		offset = offset + SPI_FLASH_WR_WORD;
+		size = size - SPI_FLASH_WR_WORD;
+		buff = buff + SPI_FLASH_WR_WORD;
+	}
+	data = 0;
+	if (size != 0) {
+		for (i = 0; i < size; i++) {
+			data |=buff[i] << (8 * i);
+			dev_dbg(dev,"0x%x ", buff[i]);
+		}
+		dev_dbg(dev,"0x%x ", data);
+		eswin_bootspi_data_write(priv, offset, data);
+	}
+}
+
+/**
+ *  @brief Read data from flash to dest address
+ */
+static void eswin_bootspi_recv_data(struct es_spi_priv *priv, u8 *dest, u32 size)
+{
+	u32 offset = 0;
+	u8 *buff = NULL;
+	u32 data = 0xFFFFFFFF;
+	int i;
+	struct device *dev = priv->dev;
+
+	dev_dbg(dev,"read spi data\n");
+	while (size >= SPI_FLASH_WR_WORD) {
+		buff = (u8 *)dest;
+		data = eswin_bootspi_data_read(priv, offset);
+		dev_dbg(dev,"0x%x ", data);
+		for (i = 0; i < SPI_FLASH_WR_WORD; i++) {
+			*buff = (u8)(data >> (8 * i));
+			dev_dbg(dev,"0x%x ", *buff);
+			buff++;
+		}
+		dest = dest + SPI_FLASH_WR_WORD;
+		offset = offset + SPI_FLASH_WR_WORD;
+		size = size - SPI_FLASH_WR_WORD;
+	}
+	if (size != 0) {
+		buff = (u8 *)dest;
+		data = eswin_bootspi_data_read(priv, offset);
+		for (i = 0; i < size; i++) {
+			*buff = (u8)(data >> (8 * i));
+			dev_dbg(dev,"0x%x ", *buff);
+			buff++;
+		}
+	}
+	dev_dbg(dev,"\n");
+}
+
+
+/**
+ * @brief spi send command
+ */
+static void eswin_bootspi_cmd_cfg(struct es_spi_priv *priv, u32 code, u32 type)
+{
+	u32 command = eswin_bootspi_read(priv, ES_SPI_CSR_06);
+	struct device *dev = priv->dev;
+
+	command &= ~((0xFF << 6) | (0x1 << 5) | (0xF << 1) | 0x1);
+	command |= ((code << SPI_COMMAND_CODE_FIELD_POSITION) |
+		(SPI_COMMAND_MOVE_VALUE << SPI_COMMAND_MOVE_FIELD_POSITION) |
+		(type << SPI_COMMAND_TYPE_FIELD_POSITION) | SPI_COMMAND_VALID);
+
+	eswin_bootspi_write(priv, ES_SPI_CSR_06, command);
+	dev_dbg(dev, "[%s %d]: write command 0x%x, read back command 0x%x\n",
+		__func__,__LINE__, command, eswin_bootspi_read(priv, ES_SPI_CSR_06));
+}
+/**
+ * @brief  spi write flash
+ * @param [in]  offset: address of flash to be write
+ * @param [in]  wr_dest: Address of data to be sent
+ * @param [in]  size: size of flash to be write
+ */
+static void eswin_bootspi_writer(struct es_spi_priv *priv)
+{
+	u32 write_size = 0, offset, cmd_code;
+	u32 cmd_type = priv->cmd_type;
+	const u8 *wr_dest = priv->tx;
+	int size = priv->len;
+
+	offset = priv->addr;
+	cmd_code = priv->opcode;
+
+	if (size == 0) {
+		// if(SPIC_CMD_TYPE_SECTOR_ERASE == cmd_type)
+		{
+			eswin_bootspi_read_write_cfg(priv, write_size, offset);
+			eswin_bootspi_cmd_cfg(priv, cmd_code, cmd_type);
+			eswin_bootspi_wait_over(priv);
+		}
+	}
+	while (size > 0) {
+		write_size = size;
+		if (write_size > FLASH_PAGE_SIZE) {
+			write_size = FLASH_PAGE_SIZE;
+		}
+		eswin_bootspi_read_write_cfg(priv, write_size, offset);
+		eswin_bootspi_send_data(priv, wr_dest, write_size);
+		eswin_bootspi_cmd_cfg(priv, cmd_code, cmd_type);
+		eswin_bootspi_wait_over(priv);
+		wr_dest += write_size;
+		offset += write_size;
+		size = size - write_size;
+	}
+}
+
+static void eswin_bootspi_reader(struct es_spi_priv *priv)
+{
+	int read_size = 0;
+	u32 offset = priv->addr;
+	u32 cmd_code = priv->opcode;
+	u32 cmd_type = priv->cmd_type;
+	u8 *mem_dest = priv->rx;
+	int size = priv->len;
+
+	while (size > 0) {
+		read_size = size;
+		if (read_size > FLASH_PAGE_SIZE) {
+			read_size = FLASH_PAGE_SIZE;
+		}
+
+		eswin_bootspi_read_write_cfg(priv, read_size, offset);
+		eswin_bootspi_cmd_cfg(priv, cmd_code, cmd_type);
+		eswin_bootspi_wait_over(priv);
+		eswin_bootspi_recv_data(priv, mem_dest, read_size);
+		mem_dest += read_size;
+		offset += read_size;
+		size = size - read_size;
+	}
+}
+
+/*
+ * We define external_cs_manage function as 'weak' as some targets
+ * (like MSCC Ocelot) don't control the external CS pin using a GPIO
+ * controller. These SoCs use specific registers to control by
+ * software the SPI pins (and especially the CS).
+ */
+
+static void external_cs_manage(struct es_spi_priv *priv, bool on)
+{
+	gpiod_set_value(priv->cs_gpio, on ? 1 : 0);
+}
+
+/* The size of ctrl1 limits data transfers to 64K */
+static int eswin_bootspi_adjust_op_size(struct spi_mem *mem,
+					struct spi_mem_op *op)
+{
+	op->data.nbytes = min(op->data.nbytes, (unsigned int)SZ_64K);
+
+	return 0;
+}
+
+/*
+ * The controller only supports Standard SPI mode, Duall mode and
+ * Quad mode. Double sanitize the ops here to avoid OOB access.
+ */
+static bool eswin_bootspi_supports_op(struct spi_mem *mem,
+				      const struct spi_mem_op *op)
+{
+	return spi_mem_default_supports_op(mem, op);
+}
+
+static int eswin_bootspi_exec_op(struct spi_mem *mem,
+				 const struct spi_mem_op *op)
+{
+	bool read = op->data.dir == SPI_MEM_DATA_IN;
+	int ret = 0;
+	struct es_spi_priv *priv = spi_controller_get_devdata(mem->spi->controller);
+	struct device *dev = priv->dev;
+
+	priv->addr = op->addr.val;
+	priv->opcode = op->cmd.opcode;
+
+	dev_dbg(dev, "\n[%s %d]: addr=0x%llx opcode=0x%x\n", __func__,__LINE__,
+		priv->addr, priv->opcode);
+
+	if ( priv->opcode == SPINOR_OP_WREN
+		|| priv->opcode == SPINOR_OP_WRDI)
+		return 0;
+
+	switch(priv->opcode) {
+		case SPINOR_OP_RDID:
+		case SPINOR_OP_RDSFDP:
+			priv->cmd_type = SPIC_CMD_TYPE_READ_JEDEC_ID;
+			break;
+		case SPINOR_OP_BE_4K:
+		case SPINOR_OP_BE_4K_PMC:
+			priv->opcode = SPINOR_OP_BE_4K;
+			priv->cmd_type = SPIC_CMD_TYPE_SECTOR_ERASE;
+			break;
+		case SPINOR_OP_BE_32K:
+			priv->cmd_type = SPIC_CMD_TYPE_BLOCK_ERASE_TYPE1;
+			break;
+		case SPINOR_OP_SE:
+			priv->cmd_type = SPIC_CMD_TYPE_BLOCK_ERASE_TYPE2;
+			break;
+		case SPINOR_OP_CHIP_ERASE:
+			priv->cmd_type = SPIC_CMD_TYPE_CHIP_ERASE;
+			break;
+		case SPINOR_OP_PP:
+		case SPINOR_OP_PP_1_1_4:
+		case SPINOR_OP_PP_1_4_4:
+		case SPINOR_OP_PP_1_1_8:
+		case SPINOR_OP_PP_1_8_8:
+			priv->opcode = SPINOR_OP_PP;
+			priv->cmd_type = SPIC_CMD_TYPE_SPI_PROGRAM;
+			break;
+		case SPINOR_OP_READ:
+		case SPINOR_OP_READ_FAST:
+		case SPINOR_OP_READ_1_1_2:
+		case SPINOR_OP_READ_1_2_2:
+		case SPINOR_OP_READ_1_1_4:
+		case SPINOR_OP_READ_1_4_4:
+		case SPINOR_OP_READ_1_1_8:
+		case SPINOR_OP_READ_1_8_8:
+			priv->opcode = SPINOR_OP_READ;
+			priv->cmd_type = SPIC_CMD_TYPE_READ_DATA;
+			break;
+		case SPINOR_OP_RDSR:
+		case SPINOR_OP_RDSR2:
+			priv->cmd_type = SPIC_CMD_TYPE_READ_STATUS_REGISTER;
+			break;
+		case SPINOR_OP_WRSR:
+		case SPINOR_OP_WRSR2:
+			priv->cmd_type = SPIC_CMD_TYPE_WRITE_STATUS_REGISTER;
+			break;
+		case SPIC_CMD_CODE_POWER_DOWN:
+			priv->cmd_type = SPIC_CMD_TYPE_POWER_DOWN;
+			break;
+		case SPIC_CMD_CODE_RELEASE_POWER_DOWN:
+			priv->cmd_type = SPIC_CMD_TYPE_RELEASE_POWER_DOWM;
+			break;
+		case SPIC_CMD_CODE_ENABLE_RESET:
+		case SPIC_CMD_CODE_RESET:
+			priv->cmd_type = SPIC_CMD_TYPE_SPI_PROGRAM;
+			break;
+		default:
+			dev_warn(dev, "[%s %d]: unsupport opcode = 0x%x, return sucess directly!\n",
+				__func__,__LINE__, priv->opcode);
+			return 0;
+	}
+
+	dev_dbg(dev, "[%s %d]: data direction=%d, opcode = 0x%x, cmd_type 0x%x\n",
+		__func__,__LINE__, op->data.dir, priv->opcode, priv->cmd_type);
+	external_cs_manage(priv, false);
+
+	if (read) {
+		priv->rx = op->data.buf.in;
+		priv->len = op->data.nbytes;
+		dev_dbg(dev, "[%s %d]: read len = %u\n", __func__,__LINE__, op->data.nbytes);
+		eswin_bootspi_reader(priv);
+	} else {
+		priv->tx = op->data.buf.out;
+		priv->len = op->data.nbytes;
+		/* Fill up the write fifo before starting the transfer */
+		dev_dbg(dev, "[%s %d]: write len = 0x%x  tx_addr 0x%px\n", __func__,__LINE__,
+			op->data.nbytes, priv->tx);
+		eswin_bootspi_writer(priv);
+		if (eswin_bootspi_wait_over(priv) < 0) {
+			dev_err(dev, "eswin_bootspi_wait_over ETIMEDOUT\n");
+			ret = -ETIMEDOUT;
+		}
+	}
+	external_cs_manage(priv, true);
+	dev_dbg(dev, "%u bytes xfered\n", op->data.nbytes);
+	return ret;
+}
+
+static const struct spi_controller_mem_ops eswin_bootspi_mem_ops = {
+	.adjust_op_size = eswin_bootspi_adjust_op_size,
+	.supports_op = eswin_bootspi_supports_op,
+	.exec_op = eswin_bootspi_exec_op,
+};
+
+static int eswin_bootspi_setup(struct spi_device *spi)
+{
+	struct es_spi_priv *priv = spi_controller_get_devdata(spi->controller);
+	struct device *dev = priv->dev;
+	int vaule = 0;
+	int ret;
+
+	ret = clk_prepare_enable(priv->cfg_clk);
+	if (ret) {
+		dev_err(dev, "could not enable cfg clock: %d\n", ret);
+		goto err_cfg_clk;
+	}
+
+	ret = clk_prepare_enable(priv->clk);
+	if (ret) {
+		dev_err(dev, "could not enable clock: %d\n", ret);
+		goto err_clk;
+	}
+	/* set rate to 50M*/
+	ret = clk_set_rate(priv->clk, 50000000);
+	if (ret) {
+		dev_err(dev, "could not enable clock: %d\n", ret);
+		goto err_clk;
+	}
+
+	reset_control_deassert(priv->rstc);
+
+	/* switch bootspi to cpu mode*/
+	vaule = readl(priv->sys_regs + ES_SYSCSR_SPIMODECFG);
+	vaule |= 0x1;
+	writel(vaule, priv->sys_regs + ES_SYSCSR_SPIMODECFG);
+
+	/* Basic HW init */
+	eswin_bootspi_write(priv, ES_SPI_CSR_08, 0x0);
+	return ret;
+
+err_clk:
+	clk_disable(priv->cfg_clk);
+err_cfg_clk:
+	return ret;
+}
+
+static int eswin_bootspi_probe(struct platform_device *pdev)
+{
+	struct es_spi_priv *priv;
+	struct spi_controller *controller;
+	int ret = 0;
+	struct device *dev = &pdev->dev;
+
+	controller = devm_spi_alloc_host(&pdev->dev, sizeof(*priv));
+	if (!controller)
+		return -ENOMEM;
+
+	controller->mode_bits = SPI_CPOL | SPI_CPHA;
+	controller->flags = SPI_CONTROLLER_HALF_DUPLEX;
+	controller->setup = eswin_bootspi_setup;
+	controller->dev.of_node = pdev->dev.of_node;
+	controller->bits_per_word_mask = SPI_BPW_MASK(32) | SPI_BPW_MASK(16) |
+				     SPI_BPW_MASK(8);
+	controller->mem_ops = &eswin_bootspi_mem_ops;
+	controller->num_chipselect = 1;
+
+	priv = spi_controller_get_devdata(controller);
+	priv->controller = controller;
+	priv->dev = &pdev->dev;
+	platform_set_drvdata(pdev, priv);
+
+	priv->regs = devm_platform_ioremap_resource(pdev, 0);
+	if (IS_ERR(priv->regs)) {
+		dev_err(dev, "%s %d: failed to map registers\n", __func__,__LINE__);
+		return PTR_ERR(priv->regs);
+	}
+
+	priv->sys_regs = devm_platform_ioremap_resource(pdev, 1);
+	if (IS_ERR(priv->sys_regs)) {
+		dev_err(dev,"%s %d: failed to map sys registers\n", __func__, __LINE__);
+		return PTR_ERR(priv->sys_regs);
+	}
+
+	priv->flash_base = devm_platform_ioremap_resource(pdev, 2);
+	if (IS_ERR(priv->flash_base)) {
+		dev_err(dev,"%s %d: failed to map sys registers\n", __func__, __LINE__);
+		return PTR_ERR(priv->flash_base);
+	}
+
+	priv->cfg_clk = devm_clk_get(dev, "cfg_clk");
+	if (IS_ERR(priv->cfg_clk)) {
+		dev_err(dev, "%s %d:could not get cfg clk: %ld\n", __func__,__LINE__,
+			PTR_ERR(priv->cfg_clk));
+		return PTR_ERR(priv->cfg_clk);
+	}
+
+	priv->clk = devm_clk_get(dev, "clk");
+	if (IS_ERR(priv->clk)) {
+		dev_err(dev, "%s %d:could not get clk: %ld\n",__func__,__LINE__, PTR_ERR(priv->rstc));
+		return PTR_ERR(priv->clk);
+	}
+	priv->rstc = devm_reset_control_get_optional_exclusive(dev, "rst");
+	if (IS_ERR(priv->rstc)) {
+		dev_err(dev, "%s %d:could not get rst: %ld\n", __func__,__LINE__, PTR_ERR(priv->rstc));
+		return PTR_ERR(priv->rstc);
+	}
+
+	priv->cs_gpio = devm_gpiod_get(dev, "cs", GPIOD_OUT_LOW);
+	if (IS_ERR(priv->cs_gpio)) {
+		dev_err(dev, "%s %d: couldn't request gpio! (error %ld)\n", __func__,__LINE__,
+			PTR_ERR(priv->cs_gpio));
+		return PTR_ERR(priv->cs_gpio);
+	}
+
+	priv->max_xfer = 32;
+	dev_info(dev, "ssi_max_xfer_size=%u\n", priv->max_xfer);
+
+	/* Currently only bits_per_word == 8 supported */
+	priv->bits_per_word = 8;
+	priv->tmode = 0; /* Tx & Rx */
+
+	if (!priv->fifo_len) {
+		priv->fifo_len = 256;
+	}
+	ret = devm_spi_register_controller(dev, controller);
+	if (ret)
+		return ret;
+
+	dev_info(&pdev->dev, "fifo_len %d, %s mode.\n", priv->fifo_len, priv->irq ? "irq" : "polling");
+	return 0;
+
+}
+
+static const struct of_device_id eswin_bootspi_of_match[] = {
+	{ .compatible = "eswin,bootspi", .data = NULL},
+	{ /* end of table */}
+};
+MODULE_DEVICE_TABLE(of, eswin_bootspi_of_match);
+
+#ifdef CONFIG_ACPI
+static const struct acpi_device_id eswin_bootspi_acpi_match[] = {
+	{"eswin,bootspi", 0},
+	{}
+};
+MODULE_DEVICE_TABLE(acpi, eswin_bootspi_acpi_match);
+#endif
+
+static struct platform_driver eswin_bootspi_driver = {
+	.probe		= eswin_bootspi_probe,
+	.driver		= {
+		.name	= "eswin-bootspi",
+		.of_match_table = eswin_bootspi_of_match,
+#ifdef CONFIG_ACPI
+		.acpi_match_table = eswin_bootspi_acpi_match,
+#endif
+	},
+};
+module_platform_driver(eswin_bootspi_driver);
+
+MODULE_AUTHOR("Huangyifeng <huangyifeng@eswincomputing.com>");
+MODULE_DESCRIPTION("Eswin Boot SPI Controller Driver for EIC770X SoCs");
+MODULE_LICENSE("GPL v2");
+MODULE_SOFTDEP("pre: spi-nor");
diff --git a/drivers/usb/core/hub.c b/drivers/usb/core/hub.c
index 256fe8c86828..3651e03c5f6d 100644
--- a/drivers/usb/core/hub.c
+++ b/drivers/usb/core/hub.c
@@ -1464,6 +1464,7 @@ static int hub_configure(struct usb_hub *hub,
 	unsigned unit_load;
 	unsigned full_load;
 	unsigned maxchild;
+	int try_cnt = 0;
 
 	hub->buffer = kmalloc(sizeof(*hub->buffer), GFP_KERNEL);
 	if (!hub->buffer) {
@@ -1484,6 +1485,7 @@ static int hub_configure(struct usb_hub *hub,
 		goto fail;
 	}
 
+retry:
 	/* Request the entire hub descriptor.
 	 * hub->descriptor can handle USB_MAXCHILDREN ports,
 	 * but a (non-SS) hub can/will return fewer bytes here.
@@ -1503,9 +1505,15 @@ static int hub_configure(struct usb_hub *hub,
 		ret = -ENODEV;
 		goto fail;
 	} else if (hub->descriptor->bNbrPorts == 0) {
-		message = "hub doesn't have any ports!";
-		ret = -ENODEV;
-		goto fail;
+		try_cnt++;
+		if (try_cnt < 10) {
+			mdelay(10);
+			goto retry;
+		} else {
+			message = "hub doesn't have any ports!";
+			ret = -ENODEV;
+			goto fail;
+                }
 	}
 
 	/*
diff --git a/drivers/usb/dwc3/Kconfig b/drivers/usb/dwc3/Kconfig
index 310d182e10b5..7964147b567c 100644
--- a/drivers/usb/dwc3/Kconfig
+++ b/drivers/usb/dwc3/Kconfig
@@ -118,6 +118,15 @@ config USB_DWC3_OF_SIMPLE
 	  Currently supports Xilinx and Qualcomm DWC USB3 IP.
 	  Say 'Y' or 'M' if you have one such device.
 
+config USB_DWC3_ESWIN
+	tristate "Eswin Platforms"
+	depends on OF
+	depends on USB=y || USB=USB_DWC3
+	default USB_DWC3
+	help
+	  Support of USB2/3 functionality in Eswin platforms.
+	  say 'Y' or 'M' if you have one such device.
+
 config USB_DWC3_ST
 	tristate "STMicroelectronics Platforms"
 	depends on (ARCH_STI || COMPILE_TEST) && OF
diff --git a/drivers/usb/dwc3/Makefile b/drivers/usb/dwc3/Makefile
index 830e6c9e5fe0..eeea5a0b71cb 100644
--- a/drivers/usb/dwc3/Makefile
+++ b/drivers/usb/dwc3/Makefile
@@ -57,3 +57,4 @@ obj-$(CONFIG_USB_DWC3_IMX8MP)		+= dwc3-imx8mp.o
 obj-$(CONFIG_USB_DWC3_XILINX)		+= dwc3-xilinx.o
 obj-$(CONFIG_USB_DWC3_OCTEON)		+= dwc3-octeon.o
 obj-$(CONFIG_USB_DWC3_RTK)		+= dwc3-rtk.o
+obj-$(CONFIG_USB_DWC3_ESWIN)		+= dwc3-eswin.o
diff --git a/drivers/usb/dwc3/dwc3-eswin.c b/drivers/usb/dwc3/dwc3-eswin.c
new file mode 100644
index 000000000000..b6f27b8bf092
--- /dev/null
+++ b/drivers/usb/dwc3/dwc3-eswin.c
@@ -0,0 +1,590 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * eswin Specific Glue layer
+ *
+ * Copyright 2024, Beijing ESWIN Computing Technology Co., Ltd.. All rights reserved.
+ * SPDX-License-Identifier: GPL-2.0
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, version 2.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <https://www.gnu.org/licenses/>.
+ *
+ * Authors: Han Min <hanmin@eswincomputing.com>
+ */
+
+#include <linux/async.h>
+#include <linux/module.h>
+#include <linux/mutex.h>
+#include <linux/kernel.h>
+#include <linux/slab.h>
+#include <linux/platform_device.h>
+#include <linux/dma-mapping.h>
+#include <linux/clk.h>
+#include <linux/clk-provider.h>
+#include <linux/of.h>
+#include <linux/of_platform.h>
+#include <linux/pm_runtime.h>
+#include <linux/extcon.h>
+#include <linux/freezer.h>
+#include <linux/iopoll.h>
+#include <linux/reset.h>
+#include <linux/usb.h>
+#include <linux/pm.h>
+#include <linux/usb/hcd.h>
+#include <linux/usb/ch9.h>
+#include <linux/extcon-provider.h>
+#include <linux/mfd/syscon.h>
+#include <linux/bitfield.h>
+#include <linux/regmap.h>
+#include <linux/gpio/consumer.h>
+#include "core.h"
+#include "io.h"
+
+#define HSP_USB_VBUS_FSEL 0x2a
+#define HSP_USB_MPLL_DEFAULT 0x0
+
+#define HSP_USB_BUS_FILTER_EN (0x1 << 0)
+#define HSP_USB_BUS_CLKEN_GM (0x1 << 9)
+#define HSP_USB_BUS_CLKEN_GS (0x1 << 16)
+#define HSP_USB_BUS_SW_RST (0x1 << 24)
+#define HSP_USB_BUS_CLK_EN (0x1 << 28)
+
+#define HSP_USB_AXI_LP_XM_CSYSREQ (0x1 << 0)
+#define HSP_USB_AXI_LP_XS_CSYSREQ (0x1 << 16)
+
+struct dwc3_eswin {
+	int num_clocks;
+	bool connected;
+	bool suspended;
+	bool force_mode;
+	bool is_phy_on;
+	struct device *dev;
+	struct clk **clks;
+	struct dwc3 *dwc;
+	struct extcon_dev *edev;
+	struct usb_hcd *hcd;
+	struct notifier_block device_nb;
+	struct notifier_block host_nb;
+	struct work_struct otg_work;
+	struct mutex lock;
+	struct reset_control *vaux_rst;
+	struct device *child_dev;
+	enum usb_role new_usb_role;
+};
+
+static ssize_t dwc3_mode_show(struct device *device,
+			      struct device_attribute *attr, char *buf)
+{
+	struct dwc3_eswin *eswin = dev_get_drvdata(device);
+	struct dwc3 *dwc = eswin->dwc;
+	int ret;
+
+	switch (dwc->current_dr_role) {
+	case USB_DR_MODE_HOST:
+		ret = sprintf(buf, "host\n");
+		break;
+	case USB_DR_MODE_PERIPHERAL:
+		ret = sprintf(buf, "peripheral\n");
+		break;
+	case USB_DR_MODE_OTG:
+		ret = sprintf(buf, "otg\n");
+		break;
+	default:
+		ret = sprintf(buf, "UNKNOWN\n");
+	}
+
+	return ret;
+}
+
+static ssize_t dwc3_mode_store(struct device *device,
+			       struct device_attribute *attr,
+			       const char *buf, size_t count)
+{
+	struct dwc3_eswin *eswin = dev_get_drvdata(device);
+	struct dwc3 *dwc = eswin->dwc;
+	enum usb_role new_role;
+	struct usb_role_switch *role_sw = dwc->role_sw;
+
+	if (!strncmp(buf, "1", 1) || !strncmp(buf, "host", 4)) {
+		new_role = USB_ROLE_HOST;
+	} else if (!strncmp(buf, "0", 1) || !strncmp(buf, "peripheral", 10)) {
+		new_role = USB_ROLE_DEVICE;
+	} else {
+		dev_info(eswin->dev, "illegal dr_mode\n");
+		return count;
+	}
+	eswin->force_mode = true;
+
+	mutex_lock(&eswin->lock);
+	usb_role_switch_set_role(role_sw, new_role);
+	mutex_unlock(&eswin->lock);
+
+	return count;
+}
+
+static DEVICE_ATTR_RW(dwc3_mode);
+
+static struct attribute *dwc3_eswin_attrs[] = {
+	&dev_attr_dwc3_mode.attr,
+	NULL,
+};
+
+static struct attribute_group dwc3_eswin_attr_group = {
+	.name = NULL, /* we want them in the same directory */
+	.attrs = dwc3_eswin_attrs,
+};
+
+static int dwc3_eswin_device_notifier(struct notifier_block *nb,
+					 unsigned long event, void *ptr)
+{
+	struct dwc3_eswin *eswin =
+		container_of(nb, struct dwc3_eswin, device_nb);
+
+	mutex_lock(&eswin->lock);
+	eswin->new_usb_role = USB_ROLE_DEVICE;
+	mutex_unlock(&eswin->lock);
+	if (!eswin->suspended)
+		schedule_work(&eswin->otg_work);
+
+	return NOTIFY_DONE;
+}
+
+static int dwc3_eswin_host_notifier(struct notifier_block *nb,
+				    unsigned long event, void *ptr)
+{
+	struct dwc3_eswin *eswin = container_of(nb, struct dwc3_eswin, host_nb);
+	mutex_lock(&eswin->lock);
+	eswin->new_usb_role = USB_ROLE_HOST;
+	mutex_unlock(&eswin->lock);
+	if (!eswin->suspended)
+		schedule_work(&eswin->otg_work);
+
+	return NOTIFY_DONE;
+}
+
+static void dwc3_eswin_otg_extcon_evt_work(struct work_struct *work)
+{
+	struct dwc3_eswin *eswin =
+		container_of(work, struct dwc3_eswin, otg_work);
+	struct usb_role_switch *role_sw = eswin->dwc->role_sw;
+	if (true == eswin->force_mode) {
+		return;
+	}
+	mutex_lock(&eswin->lock);
+	usb_role_switch_set_role(role_sw, eswin->new_usb_role);
+	mutex_unlock(&eswin->lock);
+}
+
+static int dwc3_eswin_get_extcon_dev(struct dwc3_eswin *eswin)
+{
+	struct device *dev = eswin->dev;
+	struct extcon_dev *edev;
+	s32 ret = 0;
+
+	if (device_property_read_bool(dev, "extcon")) {
+		edev = extcon_get_edev_by_phandle(dev, 0);
+		if (IS_ERR(edev)) {
+			if (PTR_ERR(edev) != -EPROBE_DEFER)
+				dev_err(dev, "couldn't get extcon device\n");
+			return PTR_ERR(edev);
+		}
+		eswin->edev = edev;
+		eswin->device_nb.notifier_call = dwc3_eswin_device_notifier;
+		ret = devm_extcon_register_notifier(dev, edev, EXTCON_USB,
+						    &eswin->device_nb);
+		if (ret < 0)
+			dev_err(dev, "failed to register notifier for USB\n");
+
+		eswin->host_nb.notifier_call = dwc3_eswin_host_notifier;
+		ret = devm_extcon_register_notifier(dev, edev, EXTCON_USB_HOST,
+						    &eswin->host_nb);
+		if (ret < 0)
+			dev_err(dev, "failed to register notifier for USB-HOST\n");
+	}
+
+	return 0;
+}
+
+static int __init dwc3_eswin_deassert(struct dwc3_eswin *eswin)
+{
+	int rc;
+
+	if (eswin->vaux_rst) {
+		rc = reset_control_deassert(eswin->vaux_rst);
+		WARN_ON(0 != rc);
+	}
+
+	return 0;
+}
+
+static int dwc3_eswin_assert(struct dwc3_eswin *eswin)
+{
+	int rc = 0;
+
+	if (eswin->vaux_rst) {
+		rc = reset_control_assert(eswin->vaux_rst);
+		WARN_ON(0 != rc);
+	}
+
+	return 0;
+}
+
+static int dwc_usb_clk_init(struct device *dev)
+{
+	struct regmap *regmap;
+	u32 hsp_usb_bus;
+	u32 hsp_usb_axi_lp;
+	u32 hsp_usb_vbus_freq;
+	u32 hsp_usb_mpll;
+	int ret;
+
+	regmap = syscon_regmap_lookup_by_phandle(dev->of_node, "eswin,hsp_sp_csr");
+	if (IS_ERR(regmap)) {
+		dev_dbg(dev, "No hsp_sp_csr phandle specified\n");
+		return -1;
+	}
+	ret = of_property_read_u32_index(dev->of_node, "eswin,hsp_sp_csr", 1,
+				&hsp_usb_bus);
+	if (ret) {
+		dev_err(dev, "can't get usb sid cfg reg offset (%d)\n", ret);
+		return ret;
+	}
+	ret = of_property_read_u32_index(dev->of_node, "eswin,hsp_sp_csr", 2,
+				&hsp_usb_axi_lp);
+	if (ret) {
+		dev_err(dev, "can't get usb sid cfg reg offset (%d)\n", ret);
+		return ret;
+	}
+	ret = of_property_read_u32_index(dev->of_node, "eswin,hsp_sp_csr", 3,
+				&hsp_usb_vbus_freq);
+	if (ret) {
+		dev_err(dev, "can't get usb sid cfg reg offset (%d)\n", ret);
+		return ret;
+	}
+	ret = of_property_read_u32_index(dev->of_node, "eswin,hsp_sp_csr", 4,
+				&hsp_usb_mpll);
+	if (ret) {
+		dev_err(dev, "can't get usb sid cfg reg offset (%d)\n", ret);
+		return ret;
+	}
+
+	/*
+	 * usb1 clock init
+	 * ref clock is 24M, below need to be set to satisfy usb phy requirement(125M)
+	 */
+	regmap_write(regmap, hsp_usb_vbus_freq, HSP_USB_VBUS_FSEL);
+	regmap_write(regmap, hsp_usb_mpll, HSP_USB_MPLL_DEFAULT);
+
+	/*
+	 * reset usb core and usb phy
+	 */
+	regmap_write(regmap, hsp_usb_bus,
+		     HSP_USB_BUS_FILTER_EN | HSP_USB_BUS_CLKEN_GM |
+			     HSP_USB_BUS_CLKEN_GS | HSP_USB_BUS_SW_RST |
+			     HSP_USB_BUS_CLK_EN);
+	regmap_write(regmap, hsp_usb_axi_lp,
+		     HSP_USB_AXI_LP_XM_CSYSREQ | HSP_USB_AXI_LP_XS_CSYSREQ);
+
+	return 0;
+}
+
+static int dwc3_eswin_probe(struct platform_device *pdev)
+{
+	struct dwc3_eswin *eswin;
+	struct device *dev = &pdev->dev;
+	struct device_node *np = dev->of_node, *child;
+	struct platform_device *child_pdev;
+	unsigned int count;
+	int ret;
+	int i;
+	int err_desc = 0;
+	struct gpio_desc *hub_gpio;
+
+	hub_gpio = devm_gpiod_get(dev, "hub-rst", GPIOD_OUT_HIGH);
+	err_desc = IS_ERR(hub_gpio);
+
+	if (!err_desc) {
+		gpiod_set_raw_value(hub_gpio, 1);
+	}
+
+	eswin = devm_kzalloc(dev, sizeof(*eswin), GFP_KERNEL);
+	if (!eswin)
+		return -ENOMEM;
+
+	count = of_clk_get_parent_count(np);
+	if (!count)
+		return -ENOENT;
+
+	eswin->num_clocks = count;
+	eswin->force_mode = false;
+	eswin->clks = devm_kcalloc(dev, eswin->num_clocks, sizeof(struct clk *),
+				   GFP_KERNEL);
+	if (!eswin->clks)
+		return -ENOMEM;
+
+	platform_set_drvdata(pdev, eswin);
+
+	mutex_init(&eswin->lock);
+
+	eswin->dev = dev;
+
+	mutex_lock(&eswin->lock);
+
+	for (i = 0; i < eswin->num_clocks; i++) {
+		struct clk *clk;
+		clk = of_clk_get(np, i);
+		if (IS_ERR(clk)) {
+			ret = PTR_ERR(clk);
+			goto err0;
+		}
+		ret = clk_prepare_enable(clk);
+		if (ret < 0) {
+			clk_put(clk);
+			goto err0;
+		}
+
+		eswin->clks[i] = clk;
+	}
+
+	eswin->vaux_rst = devm_reset_control_get(dev, "vaux");
+	if (IS_ERR_OR_NULL(eswin->vaux_rst)) {
+		dev_err(dev, "Failed to asic0_rst handle\n");
+		return -EFAULT;
+	}
+
+	dwc3_eswin_deassert(eswin);
+	dwc_usb_clk_init(dev);
+
+	pm_runtime_set_active(dev);
+	pm_runtime_enable(dev);
+	ret = pm_runtime_get_sync(dev);
+	if (ret < 0) {
+		dev_err(dev, "get_sync failed with err %d\n", ret);
+		goto err1;
+	}
+
+	child = of_get_child_by_name(np, "dwc3");
+	if (!child) {
+		dev_err(dev, "failed to find dwc3 core node\n");
+		ret = -ENODEV;
+		goto err1;
+	}
+
+	/* Allocate and initialize the core */
+	ret = of_platform_populate(np, NULL, NULL, dev);
+	if (ret) {
+		dev_err(dev, "failed to create dwc3 core\n");
+		goto err1;
+	}
+
+	INIT_WORK(&eswin->otg_work, dwc3_eswin_otg_extcon_evt_work);
+
+	child_pdev = of_find_device_by_node(child);
+	if (!child_pdev) {
+		dev_err(dev, "failed to find dwc3 core device\n");
+		ret = -ENODEV;
+		goto err2;
+	}
+
+	eswin->dwc = platform_get_drvdata(child_pdev);
+	if (!eswin->dwc) {
+		dev_err(dev, "failed to get drvdata dwc3\n");
+		ret = -EPROBE_DEFER;
+		goto err2;
+	}
+	eswin->child_dev = &child_pdev->dev;
+
+	ret = dwc3_eswin_get_extcon_dev(eswin);
+	if (ret < 0)
+		goto err2;
+
+	mutex_unlock(&eswin->lock);
+	ret = sysfs_create_group(&dev->kobj, &dwc3_eswin_attr_group);
+	if (ret)
+		dev_err(dev, "failed to create sysfs group: %d\n", ret);
+
+	return ret;
+
+err2:
+	cancel_work_sync(&eswin->otg_work);
+	of_platform_depopulate(dev);
+
+err1:
+	pm_runtime_put_sync(dev);
+	pm_runtime_disable(dev);
+	dwc3_eswin_assert(eswin);
+
+err0:
+	for (i = 0; i < eswin->num_clocks && eswin->clks[i]; i++) {
+		if (!pm_runtime_status_suspended(dev))
+			clk_disable(eswin->clks[i]);
+		clk_unprepare(eswin->clks[i]);
+		clk_put(eswin->clks[i]);
+	}
+
+	mutex_unlock(&eswin->lock);
+
+	return ret;
+}
+
+static void dwc3_eswin_remove(struct platform_device *pdev)
+{
+	struct dwc3_eswin *eswin = platform_get_drvdata(pdev);
+	struct device *dev = &pdev->dev;
+	int i = 0;
+	cancel_work_sync(&eswin->otg_work);
+
+	sysfs_remove_group(&dev->kobj, &dwc3_eswin_attr_group);
+
+	/* Restore hcd state before unregistering xhci */
+	if (eswin->edev && !eswin->connected) {
+		struct usb_hcd *hcd = dev_get_drvdata(&eswin->dwc->xhci->dev);
+
+		pm_runtime_get_sync(dev);
+
+		/*
+		 * The xhci code does not expect that HCDs have been removed.
+		 * It will unconditionally call usb_remove_hcd() when the xhci
+		 * driver is unloaded in of_platform_depopulate(). This results
+		 * in a crash if the HCDs were already removed. To avoid this
+		 * crash, add the HCDs here as dummy operation.
+		 * This code should be removed after pm runtime support
+		 * has been added to xhci.
+		 */
+		if (hcd->state == HC_STATE_HALT) {
+			usb_add_hcd(hcd, hcd->irq, IRQF_SHARED);
+			usb_add_hcd(hcd->shared_hcd, hcd->irq, IRQF_SHARED);
+		}
+	}
+
+	of_platform_depopulate(dev);
+
+	pm_runtime_put_sync(dev);
+	pm_runtime_disable(dev);
+
+	dwc3_eswin_assert(eswin);
+	for (i = 0; i < eswin->num_clocks; i++) {
+		if (!pm_runtime_status_suspended(dev))
+			clk_disable(eswin->clks[i]);
+		clk_unprepare(eswin->clks[i]);
+		clk_put(eswin->clks[i]);
+	}
+}
+
+#ifdef CONFIG_PM
+static int dwc3_eswin_runtime_suspend(struct device *dev)
+{
+	struct dwc3_eswin *eswin = dev_get_drvdata(dev);
+	int i;
+
+	for (i = 0; i < eswin->num_clocks; i++)
+		clk_disable(eswin->clks[i]);
+
+	device_init_wakeup(dev, false);
+
+	return 0;
+}
+
+static int dwc3_eswin_runtime_resume(struct device *dev)
+{
+	struct dwc3_eswin *eswin = dev_get_drvdata(dev);
+	int i;
+
+	for (i = 0; i < eswin->num_clocks; i++)
+		clk_enable(eswin->clks[i]);
+
+	device_init_wakeup(dev, true);
+
+	return 0;
+}
+
+static int __maybe_unused dwc3_eswin_suspend(struct device *dev)
+{
+	struct dwc3_eswin *eswin = dev_get_drvdata(dev);
+	struct dwc3 *dwc = eswin->dwc;
+
+	eswin->suspended = true;
+	cancel_work_sync(&eswin->otg_work);
+
+	/*
+	 * The flag of is_phy_on is only true if
+	 * the DWC3 is in Host mode.
+	 */
+	if (eswin->is_phy_on) {
+		phy_power_off(dwc->usb2_generic_phy[0]);
+
+		/*
+		 * If link state is Rx.Detect, it means that
+		 * no usb device is connecting with the DWC3
+		 * Host, and need to power off the USB3 PHY.
+		 */
+		dwc->link_state = dwc3_gadget_get_link_state(dwc);
+		if (dwc->link_state == DWC3_LINK_STATE_RX_DET)
+			phy_power_off(dwc->usb3_generic_phy[0]);
+	}
+
+	return 0;
+}
+
+static int __maybe_unused dwc3_eswin_resume(struct device *dev)
+{
+	struct dwc3_eswin *eswin = dev_get_drvdata(dev);
+	struct dwc3 *dwc = eswin->dwc;
+
+	eswin->suspended = false;
+
+	if (eswin->is_phy_on) {
+		phy_power_on(dwc->usb2_generic_phy[0]);
+
+		if (dwc->link_state == DWC3_LINK_STATE_RX_DET)
+			phy_power_on(dwc->usb3_generic_phy[0]);
+	}
+
+	if (eswin->edev)
+		schedule_work(&eswin->otg_work);
+
+	return 0;
+}
+
+static const struct dev_pm_ops dwc3_eswin_dev_pm_ops = {
+	SET_SYSTEM_SLEEP_PM_OPS(dwc3_eswin_suspend, dwc3_eswin_resume)
+	SET_RUNTIME_PM_OPS(dwc3_eswin_runtime_suspend,
+			   dwc3_eswin_runtime_resume, NULL)
+};
+
+#define DEV_PM_OPS      (&dwc3_eswin_dev_pm_ops)
+#else
+#define DEV_PM_OPS	NULL
+#endif /* CONFIG_PM */
+
+static const struct of_device_id eswin_dwc3_match[] = {
+	{ .compatible = "eswin,eic7700-dwc3" },
+	{ /* Sentinel */ }
+};
+
+MODULE_DEVICE_TABLE(of, eswin_dwc3_match);
+
+static struct platform_driver dwc3_eswin_driver = {
+	.probe		= dwc3_eswin_probe,
+	.remove		= dwc3_eswin_remove,
+	.driver		= {
+		.name	= "eswin-dwc3",
+		.pm	= DEV_PM_OPS,
+		.of_match_table = eswin_dwc3_match,
+	},
+};
+
+module_platform_driver(dwc3_eswin_driver);
+
+MODULE_ALIAS("platform:eswin-dwc3");
+MODULE_AUTHOR("Han Min <hanmin@eswin.com>");
+MODULE_LICENSE("GPL v2");
+MODULE_DESCRIPTION("DesignWare USB3 ESWIN Glue Layer");
diff --git a/drivers/usb/typec/tcpm/Kconfig b/drivers/usb/typec/tcpm/Kconfig
index 8cdd84ca5d6f..5d6d1722b682 100644
--- a/drivers/usb/typec/tcpm/Kconfig
+++ b/drivers/usb/typec/tcpm/Kconfig
@@ -63,6 +63,15 @@ config TYPEC_FUSB302
 	  Type-C Port Controller Manager to provide USB PD and USB
 	  Type-C functionalities.
 
+config TYPEC_FUSB303B
+	tristate "Onsemi FUSB303B Type-C chip driver"
+	depends on I2C
+	depends on EXTCON || !EXTCON
+	help
+	  The Onsemi FUSB303B Type-C chip driver that works with
+	  Type-C Port Controller Manager to provide USB
+	  Type-C functionalities.
+
 config TYPEC_WCOVE
 	tristate "Intel WhiskeyCove PMIC USB Type-C PHY driver"
 	depends on ACPI
diff --git a/drivers/usb/typec/tcpm/Makefile b/drivers/usb/typec/tcpm/Makefile
index 7a8cad0c0bdb..d2b501e32012 100644
--- a/drivers/usb/typec/tcpm/Makefile
+++ b/drivers/usb/typec/tcpm/Makefile
@@ -1,6 +1,7 @@
 # SPDX-License-Identifier: GPL-2.0
 obj-$(CONFIG_TYPEC_TCPM)		+= tcpm.o
 obj-$(CONFIG_TYPEC_FUSB302)		+= fusb302.o
+obj-$(CONFIG_TYPEC_FUSB303B)		+= fusb303b.o
 obj-$(CONFIG_TYPEC_WCOVE)		+= typec_wcove.o
 typec_wcove-y				:= wcove.o
 obj-$(CONFIG_TYPEC_TCPCI)		+= tcpci.o
diff --git a/drivers/usb/typec/tcpm/fusb303b.c b/drivers/usb/typec/tcpm/fusb303b.c
new file mode 100644
index 000000000000..c7d8215173b1
--- /dev/null
+++ b/drivers/usb/typec/tcpm/fusb303b.c
@@ -0,0 +1,643 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Onsemi FUSB303B Type-C Chip Driver
+ *
+ * Copyright 2024, Beijing ESWIN Computing Technology Co., Ltd.. All rights reserved.
+ * SPDX-License-Identifier: GPL-2.0
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, version 2.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <https://www.gnu.org/licenses/>.
+ *
+ * Authors: Yang Wei <yangwei1@eswincomputing.com>
+ */
+#include <linux/debugfs.h>
+#include <linux/delay.h>
+#include <linux/errno.h>
+#include <linux/gpio/consumer.h>
+#include <linux/i2c.h>
+#include <linux/interrupt.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/mutex.h>
+#include <linux/of_device.h>
+#include <linux/pinctrl/consumer.h>
+#include <linux/proc_fs.h>
+#include <linux/regulator/consumer.h>
+#include <linux/sched/clock.h>
+#include <linux/seq_file.h>
+#include <linux/slab.h>
+#include <linux/spinlock.h>
+#include <linux/string.h>
+#include <linux/types.h>
+#include <linux/usb.h>
+#include <linux/usb/typec.h>
+#include <linux/usb/tcpm.h>
+#include <linux/usb/pd.h>
+#include <linux/workqueue.h>
+
+#include <linux/of.h>
+#include <linux/of_platform.h>
+#include <linux/mfd/syscon.h>
+#include <linux/regmap.h>
+#include <linux/usb/role.h>
+
+#define FUSB303B_REG_DEVICE_ID 0X1
+#define FUSB303B_REG_DEVICE_TYPE 0X2
+#define FUSB303B_REG_PORTROLE 0X3
+#define FUSB303B_REG_CONTROL 0X4
+#define FUSB303B_REG_CONTROL1 0X5
+#define FUSB303B_REG_RESET 0XA
+#define FUSB303B_REG_MASK 0XE
+#define FUSB303B_REG_MASK1 0XF
+#define FUSB303B_REG_STATUS 0X11
+#define FUSB303B_REG_TYPE 0X13
+#define FUSB303B_REG_INTERRUPT 0X14
+#define FUSB303B_REG_INTERRUPT1 0X15
+
+#define FUSB303B_PORTROLE_DRP BIT(2)
+#define FUSB303B_PORTROLE_SINK BIT(1)
+#define FUSB303B_PORTROLE_SOURCE BIT(0)
+
+#define FUSB303B_CONTROL_DCABLE_EN BIT(3)
+#define FUSB303B_CONTROL_INT_MASK BIT(0)
+
+#define FUSB303B_CONTROL1_REMEDY_EN BIT(7)
+#define FUSB303B_CONTROL1_ENABLE BIT(3)
+
+#define FUSB303B_STATUS_VBUSOK BIT(3)
+#define FUSB303B_STATUS_ATTACH BIT(0)
+
+#define FUSB303B_INT_I_VBUS_CHG BIT(4)
+#define FUSB303B_INT_I_DETACH BIT(1)
+#define FUSB303B_INT_I_ATTACH BIT(0)
+
+#define FUSB303B_TYPE_SINK BIT(4)
+#define FUSB303B_TYPE_SOURCE BIT(3)
+
+#define FUSB_REG_MASK_M_VBUS_CHG BIT(4)
+#define FUSB_REG_MASK_M_DETACH BIT(1)
+#define FUSB_REG_MASK_M_ATTACH BIT(0)
+
+#define LOG_BUFFER_ENTRIES 1024
+#define LOG_BUFFER_ENTRY_SIZE 128
+
+struct fusb303b_chip
+{
+	struct device *dev;
+	struct i2c_client *i2c_client;
+	struct fwnode_handle *fwnode;
+	spinlock_t irq_lock;
+	struct work_struct irq_work;
+	struct gpio_desc *gpio_int_n;
+	int gpio_int_n_irq;
+	struct usb_role_switch *role_sw;
+	/* lock for sharing chip states */
+	struct mutex lock;
+	bool vbus_ok;
+	bool attch_ok;
+#ifdef CONFIG_DEBUG_FS
+	struct dentry *dentry;
+	/* lock for log buffer access */
+	struct mutex logbuffer_lock;
+	int logbuffer_head;
+	int logbuffer_tail;
+	u8 *logbuffer[LOG_BUFFER_ENTRIES];
+#endif
+};
+
+#ifdef CONFIG_DEBUG_FS
+static bool fusb303b_log_full(struct fusb303b_chip *chip)
+{
+	return chip->logbuffer_tail ==
+	       (chip->logbuffer_head + 1) % LOG_BUFFER_ENTRIES;
+}
+
+__printf(2, 0) static void _fusb303b_log(struct fusb303b_chip *chip,
+					 const char *fmt, va_list args)
+{
+	char tmpbuffer[LOG_BUFFER_ENTRY_SIZE];
+	u64 ts_nsec = local_clock();
+	unsigned long rem_nsec;
+
+	if (!chip->logbuffer[chip->logbuffer_head]) {
+		chip->logbuffer[chip->logbuffer_head] =
+			kzalloc(LOG_BUFFER_ENTRY_SIZE, GFP_KERNEL);
+		if (!chip->logbuffer[chip->logbuffer_head])
+			return;
+	}
+
+	vsnprintf(tmpbuffer, sizeof(tmpbuffer), fmt, args);
+
+	mutex_lock(&chip->logbuffer_lock);
+
+	if (fusb303b_log_full(chip)) {
+		chip->logbuffer_head = max(chip->logbuffer_head - 1, 0);
+		strscpy(tmpbuffer, "overflow", sizeof(tmpbuffer));
+	}
+
+	if (chip->logbuffer_head < 0 ||
+	    chip->logbuffer_head >= LOG_BUFFER_ENTRIES) {
+		dev_warn(chip->dev, "Bad log buffer index %d\n",
+			 chip->logbuffer_head);
+		goto abort;
+	}
+
+	if (!chip->logbuffer[chip->logbuffer_head]) {
+		dev_warn(chip->dev, "Log buffer index %d is NULL\n",
+			 chip->logbuffer_head);
+		goto abort;
+	}
+
+	rem_nsec = do_div(ts_nsec, 1000000000);
+	scnprintf(chip->logbuffer[chip->logbuffer_head], LOG_BUFFER_ENTRY_SIZE,
+		  "[%5lu.%06lu] %s", (unsigned long)ts_nsec, rem_nsec / 1000,
+		  tmpbuffer);
+	chip->logbuffer_head = (chip->logbuffer_head + 1) % LOG_BUFFER_ENTRIES;
+
+abort:
+	mutex_unlock(&chip->logbuffer_lock);
+}
+
+__printf(2, 3) static void fusb303b_log(struct fusb303b_chip *chip,
+					const char *fmt, ...)
+{
+	va_list args;
+
+	va_start(args, fmt);
+	_fusb303b_log(chip, fmt, args);
+	va_end(args);
+}
+
+static int fusb303b_debug_show(struct seq_file *s, void *v)
+{
+	struct fusb303b_chip *chip = (struct fusb303b_chip *)s->private;
+	int tail;
+
+	mutex_lock(&chip->logbuffer_lock);
+	tail = chip->logbuffer_tail;
+	while (tail != chip->logbuffer_head) {
+		seq_printf(s, "%s\n", chip->logbuffer[tail]);
+		tail = (tail + 1) % LOG_BUFFER_ENTRIES;
+	}
+	if (!seq_has_overflowed(s))
+		chip->logbuffer_tail = tail;
+	mutex_unlock(&chip->logbuffer_lock);
+
+	return 0;
+}
+DEFINE_SHOW_ATTRIBUTE(fusb303b_debug);
+
+static void fusb303b_debugfs_init(struct fusb303b_chip *chip)
+{
+	char name[NAME_MAX];
+
+	mutex_init(&chip->logbuffer_lock);
+	snprintf(name, NAME_MAX, "fusb303b-%s", dev_name(chip->dev));
+	chip->dentry = debugfs_create_dir(name, usb_debug_root);
+	debugfs_create_file("log", S_IFREG | 0444, chip->dentry, chip,
+			    &fusb303b_debug_fops);
+}
+
+static void fusb303b_debugfs_exit(struct fusb303b_chip *chip)
+{
+	debugfs_remove(chip->dentry);
+}
+
+#else
+
+static void fusb303b_log(const struct fusb303b_chip *chip, const char *fmt, ...)
+{
+}
+static void fusb303b_debugfs_init(const struct fusb303b_chip *chip)
+{
+}
+static void fusb303b_debugfs_exit(const struct fusb303b_chip *chip)
+{
+}
+
+#endif
+
+static int fusb303b_i2c_write(struct fusb303b_chip *chip, u8 address, u8 data)
+{
+	int ret = 0;
+
+	ret = i2c_smbus_write_byte_data(chip->i2c_client, address, data);
+	if (ret < 0)
+		fusb303b_log(chip, "cannot write 0x%02x to 0x%02x, ret=%d",
+			     data, address, ret);
+
+	return ret;
+}
+
+static int fusb303b_i2c_read(struct fusb303b_chip *chip, u8 address, u8 *data)
+{
+	int ret = 0;
+
+	ret = i2c_smbus_read_byte_data(chip->i2c_client, address);
+	*data = (u8)ret;
+	if (ret < 0)
+		fusb303b_log(chip, "cannot read %02x, ret=%d", address, ret);
+
+	return ret;
+}
+
+static int fusb303b_i2c_mask_write(struct fusb303b_chip *chip, u8 address,
+				   u8 mask, u8 value)
+{
+	int ret = 0;
+	u8 data;
+
+	ret = fusb303b_i2c_read(chip, address, &data);
+	if (ret < 0)
+		return ret;
+	data &= ~mask;
+	data |= value;
+	ret = fusb303b_i2c_write(chip, address, data);
+	if (ret < 0)
+		return ret;
+
+	return ret;
+}
+
+static int fusb303b_i2c_clear_bits(struct fusb303b_chip *chip, u8 address,
+				   u8 clear_bits)
+{
+	return fusb303b_i2c_mask_write(chip, address, clear_bits, 0x00);
+}
+
+static int fusb303b_sw_reset(struct fusb303b_chip *chip)
+{
+	int ret = 0;
+
+	ret = fusb303b_i2c_write(chip, FUSB303B_REG_RESET, 1);
+	if (ret < 0)
+		fusb303b_log(chip, "cannot sw reset the chip, ret=%d", ret);
+	else
+		fusb303b_log(chip, "sw reset");
+
+	return ret;
+}
+
+/*
+ * initialize interrupt on the chip
+ * - unmasked interrupt: VBUS_OK
+ */
+static int fusb303b_init_interrupt(struct fusb303b_chip *chip)
+{
+	int ret = 0;
+	u8 int_unmask = FUSB_REG_MASK_M_VBUS_CHG |
+                        FUSB_REG_MASK_M_DETACH | FUSB_REG_MASK_M_ATTACH;
+	ret = fusb303b_i2c_write(chip, FUSB303B_REG_MASK,
+                                0xFF & ~(int_unmask));
+	if (ret < 0)
+		return ret;
+	ret = fusb303b_i2c_write(chip, FUSB303B_REG_MASK1, 0xFF);
+	if (ret < 0)
+		return ret;
+
+	ret = fusb303b_i2c_clear_bits(chip, FUSB303B_REG_CONTROL,
+                                    FUSB303B_CONTROL_INT_MASK);
+	if (ret < 0)
+		return ret;
+
+	return ret;
+}
+
+static int fusb303b_init(struct fusb303b_chip *chip)
+{
+	int ret = 0;
+	u8 data;
+
+	ret = fusb303b_sw_reset(chip);
+	if (ret < 0)
+		return ret;
+	fusb303b_i2c_read(chip, FUSB303B_REG_STATUS, &data);
+	fusb303b_i2c_mask_write(chip, FUSB303B_REG_CONTROL,
+                                FUSB303B_CONTROL_DCABLE_EN,
+                                FUSB303B_CONTROL_DCABLE_EN);
+	fusb303b_i2c_mask_write(chip, FUSB303B_REG_CONTROL1,
+                                FUSB303B_CONTROL1_ENABLE | FUSB303B_CONTROL1_REMEDY_EN,
+                                FUSB303B_CONTROL1_ENABLE | FUSB303B_CONTROL1_REMEDY_EN);
+	ret = fusb303b_init_interrupt(chip);
+	if (ret < 0)
+		return ret;
+
+	ret = fusb303b_i2c_read(chip, FUSB303B_REG_STATUS, &data);
+	if (ret < 0)
+		return ret;
+	chip->vbus_ok = !!(data & FUSB303B_STATUS_VBUSOK);
+	chip->attch_ok = !!(data & FUSB303B_STATUS_ATTACH);
+	ret = fusb303b_i2c_read(chip, FUSB303B_REG_DEVICE_ID, &data);
+	if (ret < 0)
+		return ret;
+	fusb303b_log(chip, "fusb303b device ID: 0x%02x", data);
+
+	ret = fusb303b_i2c_read(chip, FUSB303B_REG_DEVICE_TYPE, &data);
+	if (ret < 0)
+		return ret;
+	fusb303b_log(chip, "fusb303b type:0x%02x", data);
+
+	return ret;
+}
+
+static s32 fusb303b_set_port_check(struct fusb303b_chip *chip,
+                                    enum typec_port_type port_type)
+{
+	s32 ret = 0;
+
+	fusb303b_log(chip, "%s.%d port_type:%d",
+                    __FUNCTION__, __LINE__, port_type);
+	switch (port_type)
+	{
+            case TYPEC_PORT_DRP:
+                ret = fusb303b_i2c_write(chip, FUSB303B_REG_PORTROLE,
+                                        FUSB303B_PORTROLE_DRP);
+                break;
+            case TYPEC_PORT_SRC:
+                ret = fusb303b_i2c_write(chip, FUSB303B_REG_PORTROLE,
+                                        FUSB303B_PORTROLE_SOURCE);
+                break;
+            default:
+                ret = fusb303b_i2c_write(chip, FUSB303B_REG_PORTROLE,
+                                        FUSB303B_PORTROLE_SINK);
+                break;
+	}
+
+	return ret;
+}
+
+static int fusb303b_set_usb_role(struct fusb303b_chip *chip)
+{
+	u8 type = 0;
+	int ret = 0;
+
+	if ((true == chip->attch_ok) && (true == chip->vbus_ok))
+	{
+		ret = fusb303b_i2c_read(chip, FUSB303B_REG_TYPE, &type);
+		if (ret < 0)
+		{
+			fusb303b_log(chip, "read type error:%d", ret);
+			return ret;
+		}
+		fusb303b_log(chip, "%s type: 0x%02x", __func__, type);
+		if (FUSB303B_TYPE_SOURCE == (FUSB303B_TYPE_SOURCE & type))
+		{
+			usb_role_switch_set_role(chip->role_sw, USB_ROLE_HOST);
+			fusb303b_log(chip, "set usb to host");
+		}
+		else
+		{
+			usb_role_switch_set_role(chip->role_sw, USB_ROLE_DEVICE);
+			fusb303b_log(chip, "set usb to device");
+			if (FUSB303B_TYPE_SINK != (FUSB303B_TYPE_SINK & type))
+			{
+				fusb303b_log(chip, "illegel type:0x%02x,set usb to device", type);
+			}
+		}
+	}
+
+	return 0;
+}
+
+static irqreturn_t fusb303b_irq_intn(int irq, void *dev_id)
+{
+	struct fusb303b_chip *chip = dev_id;
+	int ret = 0;
+	u8 interrupt = 0, interrupt1 = 0, status = 0;
+
+	mutex_lock(&chip->lock);
+	ret = fusb303b_i2c_read(chip, FUSB303B_REG_INTERRUPT, &interrupt);
+	if (ret < 0)
+		goto done;
+	ret = fusb303b_i2c_read(chip, FUSB303B_REG_INTERRUPT1, &interrupt1);
+	if (ret < 0)
+		goto done;
+	ret = fusb303b_i2c_read(chip, FUSB303B_REG_STATUS, &status);
+	if (ret < 0)
+		goto done;
+
+	fusb303b_log(chip, "IRQ: 0x%02x,0x%02x status: 0x%02x",
+				 interrupt, interrupt1, status);
+
+	if (interrupt & FUSB303B_INT_I_VBUS_CHG)
+	{
+		chip->vbus_ok = !!(status & FUSB303B_STATUS_VBUSOK);
+		fusb303b_log(chip, "IRQ: VBUS_OK, vbus=%s",
+                    chip->vbus_ok ? "On" : "Off");
+	}
+	if (interrupt & (FUSB303B_INT_I_ATTACH | FUSB303B_INT_I_DETACH))
+	{
+		chip->attch_ok = !!(status & FUSB303B_STATUS_ATTACH);
+		fusb303b_log(chip, "IRQ: attach OK, attach=%s",
+                        chip->attch_ok ? "On" : "Off");
+	}
+	fusb303b_set_usb_role(chip);
+	if (0 != interrupt)
+		fusb303b_i2c_write(chip, FUSB303B_REG_INTERRUPT, interrupt);
+	if (0 != interrupt1)
+		fusb303b_i2c_write(chip, FUSB303B_REG_INTERRUPT1, interrupt1);
+
+done:
+	mutex_unlock(&chip->lock);
+	return IRQ_HANDLED;
+}
+
+static int init_gpio(struct fusb303b_chip *chip)
+{
+	struct device *dev = chip->dev;
+	int ret = 0;
+
+	chip->gpio_int_n = devm_gpiod_get(dev, "int", GPIOD_IN);
+	if (IS_ERR(chip->gpio_int_n))
+	{
+		fusb303b_log(chip, "failed to request gpio_int_n\n");
+		return PTR_ERR(chip->gpio_int_n);
+	}
+	ret = gpiod_to_irq(chip->gpio_int_n);
+	if (ret < 0)
+	{
+		fusb303b_log(chip, "cannot request IRQ for GPIO Int_N, ret=%d", ret);
+		return ret;
+	}
+	chip->gpio_int_n_irq = ret;
+
+	return 0;
+}
+
+static const struct property_entry port_props[] = {
+	PROPERTY_ENTRY_STRING("data-role", "dual"),
+	PROPERTY_ENTRY_STRING("power-role", "dual"),
+	PROPERTY_ENTRY_STRING("try-power-role", "sink"),
+	{}};
+
+static struct fwnode_handle *fusb303b_fwnode_get(struct device *dev)
+{
+	struct fwnode_handle *fwnode;
+	fwnode = device_get_named_child_node(dev, "connector");
+	if (!fwnode)
+		fwnode = fwnode_create_software_node(port_props, NULL);
+
+	return fwnode;
+}
+
+static int fusb303b_probe(struct i2c_client *client)
+{
+	struct fusb303b_chip *chip;
+	struct device *dev = &client->dev;
+	int ret = 0;
+	struct regmap *regmap;
+	int irq_sel_reg;
+	int irq_sel_bit;
+	const char *cap_str;
+	int usb_data_role = 0;
+	regmap = syscon_regmap_lookup_by_phandle(dev->of_node, "eswin,syscfg");
+	if (!IS_ERR(regmap)) {
+		ret = of_property_read_u32_index(dev->of_node, "eswin,syscfg",
+						 1, &irq_sel_reg);
+		if (ret) {
+			dev_err(dev,
+				"can't get irq cfg reg offset in sys_con(errno:%d)\n",
+				ret);
+			return ret;
+		}
+		ret = of_property_read_u32_index(dev->of_node, "eswin,syscfg",
+						 2, &irq_sel_bit);
+		if (ret) {
+			dev_err(dev,
+				"can't get irq cfg bit offset in sys_con(errno:%d)\n",
+				ret);
+			return ret;
+		}
+		regmap_clear_bits(regmap, irq_sel_reg, BIT_ULL(irq_sel_bit));
+	}
+
+	chip = devm_kzalloc(&client->dev, sizeof(*chip), GFP_KERNEL);
+	if (!chip)
+		return -ENOMEM;
+	chip->i2c_client = client;
+	chip->dev = &client->dev;
+	mutex_init(&chip->lock);
+	spin_lock_init(&chip->irq_lock);
+	fusb303b_init(chip);
+	fusb303b_debugfs_init(chip);
+	if (client->irq)
+	{
+		chip->gpio_int_n_irq = client->irq;
+	}
+	else
+	{
+		ret = init_gpio(chip);
+		if (ret < 0)
+			goto destroy_workqueue;
+	}
+	chip->fwnode = fusb303b_fwnode_get(dev);
+	if (IS_ERR(chip->fwnode))
+	{
+		ret = PTR_ERR(chip->fwnode);
+		goto destroy_workqueue;
+	}
+	/*
+	 * This fwnode has a "compatible" property, but is never populated as a
+	 * struct device. Instead we simply parse it to read the properties.
+	 * This it breaks fw_devlink=on. To maintain backward compatibility
+	 * with existing DT files, we work around this by deleting any
+	 * fwnode_links to/from this fwnode.
+	 */
+	fw_devlink_purge_absent_suppliers(chip->fwnode);
+
+	/* USB data support is optional */
+	ret = fwnode_property_read_string(chip->fwnode, "data-role", &cap_str);
+	if (ret == 0)
+	{
+		ret = typec_find_port_data_role(cap_str);
+		if (ret < 0)
+		{
+			fusb303b_log(chip, "%s is not leage data-role\n", cap_str);
+			goto put_fwnode;
+		}
+		usb_data_role = ret;
+	}
+	else
+	{
+		fusb303b_log(chip, "cannot find data-role in dts\n");
+	}
+	chip->role_sw = usb_role_switch_get(chip->dev);
+	if (IS_ERR(chip->role_sw))
+	{
+		ret = PTR_ERR(chip->role_sw);
+		fusb303b_log(chip, "get role_sw error");
+		goto put_fwnode;
+	}
+
+	ret = devm_request_threaded_irq(dev, chip->gpio_int_n_irq, NULL,
+									fusb303b_irq_intn,
+									IRQF_ONESHOT | IRQF_TRIGGER_LOW,
+									"fusb303b_interrupt_int_n", chip);
+	if (ret < 0)
+	{
+		fusb303b_log(chip, "cannot request IRQ for GPIO Int_N, ret=%d", ret);
+		goto err_put_role;
+	}
+
+	enable_irq_wake(chip->gpio_int_n_irq);
+	fusb303b_set_port_check(chip, usb_data_role);
+
+	i2c_set_clientdata(client, chip);
+	fusb303b_log(chip, "Kernel thread created successfully");
+	return ret;
+err_put_role:
+	usb_role_switch_put(chip->role_sw);
+put_fwnode:
+	fwnode_handle_put(chip->fwnode);
+destroy_workqueue:
+	fusb303b_debugfs_exit(chip);
+
+	return ret;
+}
+
+static void fusb303b_remove(struct i2c_client *client)
+{
+	struct fusb303b_chip *chip = i2c_get_clientdata(client);
+
+	disable_irq_wake(chip->gpio_int_n_irq);
+	free_irq(chip->gpio_int_n_irq, chip);
+	usb_role_switch_put(chip->role_sw);
+	fwnode_handle_put(chip->fwnode);
+	fusb303b_debugfs_exit(chip);
+}
+
+static const struct of_device_id fusb303b_dt_match[] = {
+	{.compatible = "fcs,fusb303b"},
+	{},
+};
+MODULE_DEVICE_TABLE(of, fusb303b_dt_match);
+
+static const struct i2c_device_id fusb303b_i2c_device_id[] = {
+	{"typec_fusb303b", 0},
+	{},
+};
+MODULE_DEVICE_TABLE(i2c, fusb303b_i2c_device_id);
+
+static struct i2c_driver fusb303b_driver = {
+	.driver = {
+		.name = "typec_fusb303b",
+		.of_match_table = of_match_ptr(fusb303b_dt_match),
+	},
+	.probe = fusb303b_probe,
+	.remove = fusb303b_remove,
+	.id_table = fusb303b_i2c_device_id,
+};
+module_i2c_driver(fusb303b_driver);
+
+MODULE_AUTHOR("Yang Wei <yangwei1@eswincomputing.com>");
+MODULE_DESCRIPTION("Onsemi FUSB303B Type-C Chip Driver");
+MODULE_LICENSE("GPL");
diff --git a/include/dt-bindings/clock/eic7700-clock.h b/include/dt-bindings/clock/eic7700-clock.h
new file mode 100644
index 000000000000..866507498876
--- /dev/null
+++ b/include/dt-bindings/clock/eic7700-clock.h
@@ -0,0 +1,623 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * ESWIN Clk Provider Driver
+ *
+ * Copyright 2024, Beijing ESWIN Computing Technology Co., Ltd.. All rights reserved.
+ * SPDX-License-Identifier: GPL-2.0
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, version 2.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <https://www.gnu.org/licenses/>.
+ *
+ * Authors: HuangYiFeng<huangyifeng@eswincomputing.com>
+ */
+
+#ifndef __DTS_EIC7700_CLOCK_H
+#define __DTS_EIC7700_CLOCK_H
+
+#define EIC7700_NONE_CLOCK	0
+
+/* fixed rate */
+#define EIC7700_XTAL_24M                        1
+#define EIC7700_XTAL_32K                        2
+#define EIC7700_PLL_CPU                         3	/*for cpu clk*/
+#define EIC7700_SPLL0_FOUT1                     4
+#define EIC7700_SPLL0_FOUT2                     5
+#define EIC7700_SPLL0_FOUT3                     6
+#define EIC7700_SPLL1_FOUT1                     7
+#define EIC7700_SPLL1_FOUT2                     8
+#define EIC7700_SPLL1_FOUT3                     9
+#define EIC7700_SPLL2_FOUT1                     10
+#define EIC7700_SPLL2_FOUT2                     11
+#define EIC7700_SPLL2_FOUT3                     12
+#define EIC7700_VPLL_FOUT1                      13
+#define EIC7700_VPLL_FOUT2                      14
+#define EIC7700_VPLL_FOUT3                      15
+#define EIC7700_APLL_FOUT1                      16
+#define EIC7700_APLL_FOUT2                      17
+#define EIC7700_APLL_FOUT3                      18
+#define EIC7700_EXT_MCLK                        19
+#define EIC7700_PLL_DDR                         20
+#define EIC7700_LPDDR_REF_BAK                   21
+
+
+/* mux clocks */
+#define  EIC7700_MUX_U_CPU_ROOT_3MUX1_GFREE                         30	/*for cpu clk*/
+#define  EIC7700_MUX_U_CPU_ACLK_2MUX1_GFREE                         31	/*for cpu clk*/
+#define  EIC7700_MUX_U_DSP_ACLK_ROOT_2MUX1_GFREE                    32
+#define  EIC7700_MUX_U_D2D_ACLK_ROOT_2MUX1_GFREE                    33
+#define  EIC7700_MUX_U_MSHCORE_ROOT_3MUX1_0                         34
+#define  EIC7700_MUX_U_MSHCORE_ROOT_3MUX1_1                         35
+#define  EIC7700_MUX_U_MSHCORE_ROOT_3MUX1_2                         36
+#define  EIC7700_MUX_U_NPU_LLCLK_3MUX1_GFREE                        37
+#define  EIC7700_MUX_U_NPU_CORE_3MUX1_GFREE                         38
+#define  EIC7700_MUX_U_VI_ACLK_ROOT_2MUX1_GFREE                     39
+#define  EIC7700_MUX_U_VI_DVP_ROOT_2MUX1_GFREE                      40
+#define  EIC7700_MUX_U_VI_DIG_ISP_ROOT_2MUX1_GFREE                  41
+#define  EIC7700_MUX_U_VO_ACLK_ROOT_2MUX1_GFREE                     42
+#define  EIC7700_MUX_U_VO_PIXEL_ROOT_2MUX1                          43
+#define  EIC7700_MUX_U_VO_CEC_2MUX1                                 44
+#define  EIC7700_MUX_U_VCDEC_ROOT_2MUX1_GFREE                       45
+#define  EIC7700_MUX_U_VCACLK_ROOT_2MUX1_GFREE                      46
+#define  EIC7700_MUX_U_RTC_2MUX1                                    47
+#define  EIC7700_MUX_U_SYSCFG_CLK_ROOT_2MUX1_GFREE                  48
+#define  EIC7700_MUX_U_NOCNSP_XTAL_2MUX1                            49
+#define  EIC7700_MUX_U_BOOTSPI_CLK_2MUX1_GFREE                      50
+#define  EIC7700_MUX_U_SCPU_CORE_CLK_2MUX1_GFREE                    51
+#define  EIC7700_MUX_U_LPCPU_CORE_CLK_2MUX1_GFREE                   52
+#define  EIC7700_MUX_GPU_ACLK_XTAL_2MUX1                            53
+#define  EIC7700_MUX_U_DSP_ACLK_XTAL_2MUX1                          54
+#define  EIC7700_MUX_U_D2D_ACLK_XTAL_2MUX1                          55
+#define  EIC7700_MUX_U_HSP_ACLK_XTAL_2MUX1                          56
+#define  EIC7700_MUX_U_PCIE_ACLK_XTAL_2MUX1                         57
+#define  EIC7700_MUX_U_NPU_ACLK_XTAL_2MUX1                          58
+#define  EIC7700_MUX_U_NPU_LLC_XTAL_2MUX1                           59
+#define  EIC7700_MUX_U_NPU_CORE_XTAL_2MUX1                          60
+#define  EIC7700_MUX_U_VI_ACLK_XTAL_2MUX1                           61
+#define  EIC7700_MUX_U_VI_DVP_XTAL_2MUX1                            62
+#define  EIC7700_MUX_U_VI_DIG_ISP_XTAL_2MUX1                        63
+#define  EIC7700_MUX_U_VI_SHUTTER_XTAL_2MUX1_0                      64
+#define  EIC7700_MUX_U_VI_SHUTTER_XTAL_2MUX1_1                      65
+#define  EIC7700_MUX_U_VI_SHUTTER_XTAL_2MUX1_2                      66
+#define  EIC7700_MUX_U_VI_SHUTTER_XTAL_2MUX1_3                      67
+#define  EIC7700_MUX_U_VI_SHUTTER_XTAL_2MUX1_4                      68
+#define  EIC7700_MUX_U_VI_SHUTTER_XTAL_2MUX1_5                      69
+#define  EIC7700_MUX_U_VO_ACLK_XTAL_2MUX1                           70
+#define  EIC7700_MUX_U_IESMCLK_XTAL_2MUX1                           71
+#define  EIC7700_MUX_U_VO_PIXEL_XTAL_2MUX1                          72
+#define  EIC7700_MUX_U_VO_MCLK_2MUX_EXT_MCLK                        73
+#define  EIC7700_MUX_U_VC_ACLK_XTAL_2MUX1                           74
+#define  EIC7700_MUX_U_JD_XTAL_2MUX1                                75
+#define  EIC7700_MUX_U_JE_XTAL_2MUX1                                76
+#define  EIC7700_MUX_U_VE_XTAL_2MUX1                                77
+#define  EIC7700_MUX_U_VD_XTAL_2MUX1                                78
+#define  EIC7700_MUX_U_SATA_PHY_2MUX1                               79
+#define  EIC7700_MUX_U_AONDMA_AXI2MUX1_GFREE                        80
+#define  EIC7700_MUX_U_CRYPTO_XTAL_2MUX1                            81
+#define  EIC7700_MUX_U_RMII_REF_2MUX                                82
+#define  EIC7700_MUX_U_ETH_CORE_2MUX1                               83
+#define  EIC7700_MUX_U_VI_DW_ROOT_2MUX1                             84
+#define  EIC7700_MUX_U_VI_DW_XTAL_2MUX1                             85
+#define  EIC7700_MUX_U_NPU_E31_3MUX1_GFREE                          86
+#define  EIC7700_MUX_U_DDR_ACLK_ROOT_2MUX1_GFREE                    87
+
+/* divider clocks */
+#define EIC7700_DIVDER_U_SYS_CFG_DIV_DYNM                           100
+#define EIC7700_DIVDER_U_NOC_NSP_DIV_DYNM                           101
+#define EIC7700_DIVDER_U_BOOTSPI_DIV_DYNM                           102
+#define EIC7700_DIVDER_U_SCPU_CORE_DIV_DYNM                         103
+#define EIC7700_DIVDER_U_LPCPU_CORE_DIV_DYNM                        104
+#define EIC7700_DIVDER_U_GPU_ACLK_DIV_DYNM                          105
+#define EIC7700_DIVDER_U_DSP_ACLK_DIV_DYNM                          106
+#define EIC7700_DIVDER_U_D2D_ACLK_DIV_DYNM                          107
+#define EIC7700_DIVDER_U_HSP_ACLK_DIV_DYNM                          108
+#define EIC7700_DIVDER_U_ETH_TXCLK_DIV_DYNM_0                       109
+#define EIC7700_DIVDER_U_ETH_TXCLK_DIV_DYNM_1                       110
+#define EIC7700_DIVDER_U_MSHC_CORE_DIV_DYNM_0                       111
+#define EIC7700_DIVDER_U_MSHC_CORE_DIV_DYNM_1                       112
+#define EIC7700_DIVDER_U_MSHC_CORE_DIV_DYNM_2                       113
+#define EIC7700_DIVDER_U_PCIE_ACLK_DIV_DYNM                         114
+#define EIC7700_DIVDER_U_NPU_ACLK_DIV_DYNM                          115
+#define EIC7700_DIVDER_U_NPU_LLC_SRC0_DIV_DYNM                      116
+#define EIC7700_DIVDER_U_NPU_LLC_SRC1_DIV_DYNM                      117
+#define EIC7700_DIVDER_U_NPU_CORECLK_DIV_DYNM                       118
+#define EIC7700_DIVDER_U_VI_ACLK_DIV_DYNM                           119
+#define EIC7700_DIVDER_U_VI_DVP_DIV_DYNM                            120
+#define EIC7700_DIVDER_U_VI_DIG_ISP_DIV_DYNM                        121
+#define EIC7700_DIVDER_U_VI_SHUTTER_DIV_DYNM_0                      122
+#define EIC7700_DIVDER_U_VI_SHUTTER_DIV_DYNM_1                      123
+#define EIC7700_DIVDER_U_VI_SHUTTER_DIV_DYNM_2                      124
+#define EIC7700_DIVDER_U_VI_SHUTTER_DIV_DYNM_3                      125
+#define EIC7700_DIVDER_U_VI_SHUTTER_DIV_DYNM_4                      126
+#define EIC7700_DIVDER_U_VI_SHUTTER_DIV_DYNM_5                      127
+#define EIC7700_DIVDER_U_VO_ACLK_DIV_DYNM                           128
+#define EIC7700_DIVDER_U_IESMCLK_DIV_DYNM                           129
+#define EIC7700_DIVDER_U_VO_PIXEL_DIV_DYNM                          130
+#define EIC7700_DIVDER_U_VO_MCLK_DIV_DYNM                           131
+#define EIC7700_DIVDER_U_VC_ACLK_DIV_DYNM                           132
+#define EIC7700_DIVDER_U_JD_DIV_DYNM                                133
+#define EIC7700_DIVDER_U_JE_DIV_DYNM                                134
+#define EIC7700_DIVDER_U_VE_DIV_DYNM                                135
+#define EIC7700_DIVDER_U_VD_DIV_DYNM                                136
+#define EIC7700_DIVDER_U_G2D_DIV_DYNM                               137
+#define EIC7700_DIVDER_U_AONDMA_AXI_DIV_DYNM                        138
+#define EIC7700_DIVDER_U_CRYPTO_DIV_DYNM                            139
+#define EIC7700_DIVDER_U_VI_DW_DIV_DYNM                             140
+#define EIC7700_DIVDER_U_NPU_E31_DIV_DYNM                           141
+#define EIC7700_DIVDER_U_SATA_PHY_REF_DIV_DYNM                      142
+#define EIC7700_DIVDER_U_DSP_0_ACLK_DIV_DYNM                        143
+#define EIC7700_DIVDER_U_DSP_1_ACLK_DIV_DYNM                        144
+#define EIC7700_DIVDER_U_DSP_2_ACLK_DIV_DYNM                        145
+#define EIC7700_DIVDER_U_DSP_3_ACLK_DIV_DYNM                        146
+#define EIC7700_DIVDER_U_DDR_ACLK_DIV_DYNM                          147
+#define EIC7700_DIVDER_U_AON_RTC_DIV_DYNM                           148
+#define EIC7700_DIVDER_U_U84_RTC_TOGGLE_DIV_DYNM                    149
+#define EIC7700_DIVDER_U_VO_CEC_DIV_DYNM                            150
+
+/* gate clocks */
+#define EIC7700_GATE_CLK_CPU_EXT_SRC_CORE_CLK_0                 200
+#define EIC7700_GATE_CLK_CPU_EXT_SRC_CORE_CLK_1                 201
+#define EIC7700_GATE_CLK_CPU_EXT_SRC_CORE_CLK_2                 202
+#define EIC7700_GATE_CLK_CPU_EXT_SRC_CORE_CLK_3                 203
+#define EIC7700_GATE_CLK_CPU_TRACE_CLK_0                        204
+#define EIC7700_GATE_CLK_CPU_TRACE_CLK_1                        205
+#define EIC7700_GATE_CLK_CPU_TRACE_CLK_2                        206
+#define EIC7700_GATE_CLK_CPU_TRACE_CLK_3                        207
+#define EIC7700_GATE_CLK_CPU_DEBUG_CLK                          208
+#define EIC7700_GATE_CLK_CPU_TRACE_COM_CLK                      209
+#define EIC7700_GATE_CLK_CPU_CLK                                210
+#define EIC7700_GATE_CLK_SPLL0_FOUT2                            211
+#define EIC7700_GATE_CLK_VPLL_FOUT2                             212
+#define EIC7700_GATE_CLK_VPLL_FOUT3                             213
+#define EIC7700_GATE_CLK_APLL_FOUT1                             214
+#define EIC7700_GATE_CLK_APLL_FOUT2                             215
+#define EIC7700_GATE_CLK_APLL_FOUT3                             216
+#define EIC7700_GATE_EXT_MCLK                                   217
+#define EIC7700_GATE_CLK_1M                                     218
+#define EIC7700_GATE_CLK_SYS_CFG                                219
+#define EIC7700_GATE_CLK_MIPI_TXESC                             220
+#define EIC7700_GATE_NOC_CFG_CLK                                221
+#define EIC7700_GATE_NOC_NSP_CLK                                222
+#define EIC7700_GATE_CLK_BOOTSPI                                223
+#define EIC7700_GATE_CLK_BOOTSPI_CFG                            224
+#define EIC7700_GATE_CLK_U84_CORE_LP                            225
+#define EIC7700_GATE_CLK_SCPU_CORE                              226
+#define EIC7700_GATE_CLK_SCPU_BUS                               227
+#define EIC7700_GATE_CLK_LPCPU_CORE                             228
+#define EIC7700_GATE_CLK_LPCPU_BUS                              229
+#define EIC7700_GATE_GPU_ACLK                                   230
+#define EIC7700_GATE_GPU_GRAY_CLK                               231
+#define EIC7700_GATE_GPU_CFG_CLK                                232
+#define EIC7700_GATE_CLK_DSP_ROOT                               233
+#define EIC7700_GATE_DSPT_ACLK                                  234
+#define EIC7700_GATE_DSPT_CFG_CLK                               235
+#define EIC7700_GATE_CLK_D2DDR_ACLK                             236
+#define EIC7700_GATE_D2D_ACLK                                   237
+#define EIC7700_GATE_D2D_CFG_CLK                                238
+#define EIC7700_GATE_CLK_HSP_ACLK                               239
+#define EIC7700_GATE_CLK_HSP_CFGCLK                             240
+#define EIC7700_GATE_TCU_ACLK                                   241
+#define EIC7700_GATE_TCU_CFG_CLK                                242
+#define EIC7700_GATE_DDRT_CFG_CLK                               243
+#define EIC7700_GATE_DDRT1_CFG_CLK                              244
+#define EIC7700_GATE_DDRT0_P0_ACLK                              245
+#define EIC7700_GATE_DDRT0_P1_ACLK                              246
+#define EIC7700_GATE_DDRT0_P2_ACLK                              247
+#define EIC7700_GATE_DDRT0_P3_ACLK                              248
+#define EIC7700_GATE_DDRT0_P4_ACLK                              249
+#define EIC7700_GATE_DDRT1_P0_ACLK                              250
+#define EIC7700_GATE_DDRT1_P1_ACLK                              251
+#define EIC7700_GATE_DDRT1_P2_ACLK                              252
+#define EIC7700_GATE_DDRT1_P3_ACLK                              253
+#define EIC7700_GATE_DDRT1_P4_ACLK                              254
+#define EIC7700_GATE_HSP_ACLK                                   255
+#define EIC7700_GATE_HSP_CFG_CLK                                256
+#define EIC7700_GATE_HSP_SATA_RBC_CLK                           257
+#define EIC7700_GATE_HSP_SATA_OOB_CLK                           258
+#define EIC7700_GATE_HSP_SATA_PMALIVE_CLK                       259
+#define EIC7700_GATE_HSP_ETH_APP_CLK                            260
+#define EIC7700_GATE_HSP_ETH_CSR_CLK                            261
+#define EIC7700_GATE_HSP_ETH0_CORE_CLK                          262
+#define EIC7700_GATE_HSP_ETH1_CORE_CLK                          263
+#define EIC7700_GATE_HSP_MSHC0_CORE_CLK                         264
+#define EIC7700_GATE_HSP_MSHC1_CORE_CLK                         265
+#define EIC7700_GATE_HSP_MSHC2_CORE_CLK                         266
+#define EIC7700_GATE_HSP_MSHC0_TMR_CLK                          267
+#define EIC7700_GATE_HSP_MSHC1_TMR_CLK                          268
+#define EIC7700_GATE_HSP_MSHC2_TMR_CLK                          269
+#define EIC7700_GATE_HSP_USB0_SUSPEND_CLK                       270
+#define EIC7700_GATE_HSP_USB1_SUSPEND_CLK                       271
+#define EIC7700_GATE_PCIET_ACLK                                 272
+#define EIC7700_GATE_PCIET_CFG_CLK                              273
+#define EIC7700_GATE_PCIET_CR_CLK                               274
+#define EIC7700_GATE_PCIET_AUX_CLK                              275
+#define EIC7700_GATE_NPU_ACLK                                   276
+#define EIC7700_GATE_NPU_CFG_CLK                                277
+#define EIC7700_GATE_CLK_NPU_LLC_SRC0                           278
+#define EIC7700_GATE_CLK_NPU_LLC_SRC1                           279
+#define EIC7700_GATE_NPU_LLC_ACLK                               280
+#define EIC7700_GATE_CLK_NPU_CORE_ST1                           281
+#define EIC7700_GATE_NPU_CLK                                    282
+#define EIC7700_GATE_NPU_E31_CLK                                283
+#define EIC7700_GATE_CLK_VI_ACLK_ST1                            284
+#define EIC7700_GATE_VI_ACLK                                    285
+#define EIC7700_GATE_VI_DVP_CLK                                 286
+#define EIC7700_GATE_VI_CFG_CLK                                 287
+#define EIC7700_GATE_VI_DIG_DW_CLK                              288
+#define EIC7700_GATE_VI_DIG_ISP_CLK                             289
+#define EIC7700_GATE_VI_SHUTTER_0                               290
+#define EIC7700_GATE_VI_SHUTTER_1                               291
+#define EIC7700_GATE_VI_SHUTTER_2                               292
+#define EIC7700_GATE_VI_SHUTTER_3                               293
+#define EIC7700_GATE_VI_SHUTTER_4                               294
+#define EIC7700_GATE_VI_SHUTTER_5                               295
+#define EIC7700_GATE_VI_PHY_TXCLKESC                            296
+#define EIC7700_GATE_VI_PHY_CFG                                 297
+#define EIC7700_GATE_VO_ACLK                                    298
+#define EIC7700_GATE_VO_CFG_CLK                                 299
+#define EIC7700_GATE_VO_HDMI_IESMCLK                            300
+#define EIC7700_GATE_VO_PIXEL_CLK                               301
+#define EIC7700_GATE_VO_I2S_MCLK                                302
+#define EIC7700_GATE_VO_CR_CLK                                  303
+#define EIC7700_GATE_VO_CEC_CLK                                 304
+#define EIC7700_GATE_CLK_VC_ROOT                                305
+#define EIC7700_GATE_VC_ACLK                                    306
+#define EIC7700_GATE_VC_CFG_CLK                                 307
+#define EIC7700_GATE_VC_JE_CLK                                  308
+#define EIC7700_GATE_VC_JD_CLK                                  309
+#define EIC7700_GATE_VC_VE_CLK                                  310
+#define EIC7700_GATE_VC_VD_CLK                                  311
+#define EIC7700_GATE_G2D_CFG_CLK                                312
+#define EIC7700_GATE_CLK_G2D_ST2                                313
+#define EIC7700_GATE_G2D_CLK                                    314
+#define EIC7700_GATE_G2D_ACLK                                   315
+#define EIC7700_GATE_CLK_PVT_INNER                              316
+#define EIC7700_GATE_PVT_CLK_0                                  317
+#define EIC7700_GATE_PVT_CLK_1                                  318
+#define EIC7700_GATE_PVT_CLK_2                                  319
+#define EIC7700_GATE_PVT_CLK_3                                  320
+#define EIC7700_GATE_PVT_CLK_4                                  321
+#define EIC7700_GATE_CLK_AONDMA_CFG                             322
+#define EIC7700_GATE_CLK_AONDMA_AXI_ST3                         323
+#define EIC7700_GATE_AONDMA_ACLK                                324
+#define EIC7700_GATE_AON_ACLK                                   325
+#define EIC7700_GATE_TIMER_CLK_0                                326
+#define EIC7700_GATE_TIMER_CLK_1                                327
+#define EIC7700_GATE_TIMER_CLK_2                                328
+#define EIC7700_GATE_TIMER_CLK_3                                329
+#define EIC7700_GATE_TIMER_PCLK_0                               330
+#define EIC7700_GATE_TIMER_PCLK_1                               331
+#define EIC7700_GATE_TIMER_PCLK_2                               332
+#define EIC7700_GATE_TIMER_PCLK_3                               333
+#define EIC7700_GATE_TIMER3_CLK8                                334
+#define EIC7700_GATE_CLK_RTC_CFG                                335
+#define EIC7700_GATE_CLK_RTC                                    336
+#define EIC7700_GATE_HSP_RMII_REF_0                             337
+#define EIC7700_GATE_HSP_RMII_REF_1                             338
+#define EIC7700_GATE_CLK_PKA_CFG                                339
+#define EIC7700_GATE_CLK_SPACC_CFG                              340
+#define EIC7700_GATE_CLK_CRYPTO                                 341
+#define EIC7700_GATE_CLK_TRNG_CFG                               342
+#define EIC7700_GATE_CLK_OTP_CFG                                343
+#define EIC7700_GATE_CLMM_CFG_CLK                               344
+#define EIC7700_GATE_CLMM_DEB_CLK                               345
+#define EIC7700_GATE_CLK_MAILBOX_0                              346
+#define EIC7700_GATE_CLK_MAILBOX_1                              347
+#define EIC7700_GATE_CLK_MAILBOX_2                              348
+#define EIC7700_GATE_CLK_MAILBOX_3                              349
+#define EIC7700_GATE_CLK_MAILBOX_4                              350
+#define EIC7700_GATE_CLK_MAILBOX_5                              351
+#define EIC7700_GATE_CLK_MAILBOX_6                              352
+#define EIC7700_GATE_CLK_MAILBOX_7                              353
+#define EIC7700_GATE_CLK_MAILBOX_8                              354
+#define EIC7700_GATE_CLK_MAILBOX_9                              355
+#define EIC7700_GATE_CLK_MAILBOX_10                             356
+#define EIC7700_GATE_CLK_MAILBOX_11                             357
+#define EIC7700_GATE_CLK_MAILBOX_12                             358
+#define EIC7700_GATE_CLK_MAILBOX_13                             359
+#define EIC7700_GATE_CLK_MAILBOX_14                             360
+#define EIC7700_GATE_CLK_MAILBOX_15                             361
+#define EIC7700_GATE_CLK_APLL_TEST_OUT                          362
+#define EIC7700_GATE_CLK_CPLL_TEST_OUT                          363
+#define EIC7700_GATE_CLK_HSP_DFT150M                            364
+#define EIC7700_GATE_CLK_HSP_DFT300M                            365
+#define EIC7700_GATE_CLK_HSP_DFT600M                            366
+#define EIC7700_GATE_CLK_VI_DFT400M                             367
+#define EIC7700_GATE_CLK_VI_DFT500M                             368
+#define EIC7700_GATE_CLK_VO_DFT300M                             369
+#define EIC7700_GATE_CLK_VO_DFT600M                             370
+#define EIC7700_GATE_CLK_D2D_DFT300M                            371
+#define EIC7700_GATE_CLK_D2D_DFT600M                            372
+#define EIC7700_GATE_CLK_PCIE_DFT125M                           373
+#define EIC7700_GATE_CLK_PCIE_DFT200M                           374
+#define EIC7700_GATE_CLK_DDR_PLL_BYP_CLK                        375
+#define EIC7700_GATE_CLK_DDR_RX_TEST_CLK                        376
+#define EIC7700_GATE_LSP_I2C0_PCLK                              377
+#define EIC7700_GATE_LSP_I2C1_PCLK                              378
+#define EIC7700_GATE_LSP_I2C2_PCLK                              379
+#define EIC7700_GATE_LSP_I2C3_PCLK                              380
+#define EIC7700_GATE_LSP_I2C4_PCLK                              381
+#define EIC7700_GATE_LSP_I2C5_PCLK                              382
+#define EIC7700_GATE_LSP_I2C6_PCLK                              383
+#define EIC7700_GATE_LSP_I2C7_PCLK                              384
+#define EIC7700_GATE_LSP_I2C8_PCLK                              385
+#define EIC7700_GATE_LSP_I2C9_PCLK                              386
+#define EIC7700_GATE_LSP_WDT0_PCLK                              387
+#define EIC7700_GATE_LSP_WDT1_PCLK                              388
+#define EIC7700_GATE_LSP_WDT2_PCLK                              389
+#define EIC7700_GATE_LSP_WDT3_PCLK                              390
+#define EIC7700_GATE_LSP_SSI0_PCLK                              391
+#define EIC7700_GATE_LSP_SSI1_PCLK                              392
+#define EIC7700_GATE_LSP_PVT_PCLK                               393
+#define EIC7700_GATE_AON_I2C0_PCLK                              394
+#define EIC7700_GATE_AON_I2C1_PCLK                              395
+#define EIC7700_GATE_LSP_UART0_PCLK                             396
+#define EIC7700_GATE_LSP_UART1_PCLK                             397
+#define EIC7700_GATE_LSP_UART2_PCLK                             398
+#define EIC7700_GATE_LSP_UART3_PCLK                             399
+#define EIC7700_GATE_LSP_UART4_PCLK                             400
+#define EIC7700_GATE_LSP_TIMER_PCLK                             401
+#define EIC7700_GATE_LSP_FAN_PCLK                               402
+#define EIC7700_GATE_LSP_PVT0_CLK                               403
+#define EIC7700_GATE_LSP_PVT1_CLK                               404
+#define EIC7700_GATE_RESERVED_1                                 405
+#define EIC7700_GATE_RESERVED_2                                 406
+#define EIC7700_GATE_RESERVED_3                                 407
+#define EIC7700_GATE_VC_JE_PCLK                                 408
+#define EIC7700_GATE_VC_JD_PCLK                                 409
+#define EIC7700_GATE_VC_VE_PCLK                                 410
+#define EIC7700_GATE_VC_VD_PCLK                                 411
+#define EIC7700_GATE_VC_MON_PCLK                                412
+#define EIC7700_GATE_HSP_DMA0_CLK                               413
+
+/*fixed factor clocks*/
+#define EIC7700_FIXED_FACTOR_U_CPU_DIV2                         450
+#define EIC7700_FIXED_FACTOR_U_CLK_1M_DIV24                     451
+#define EIC7700_FIXED_FACTOR_U_MIPI_TXESC_DIV10                 452
+#define EIC7700_FIXED_FACTOR_U_U84_CORE_LP_DIV2                 453
+#define EIC7700_FIXED_FACTOR_U_SCPU_BUS_DIV2                    454
+#define EIC7700_FIXED_FACTOR_U_LPCPU_BUS_DIV2                   455
+#define EIC7700_FIXED_FACTOR_U_PCIE_CR_DIV2                     456
+#define EIC7700_FIXED_FACTOR_U_PCIE_AUX_DIV4                    457
+#define EIC7700_FIXED_FACTOR_U_PVT_DIV20                        458
+#define EIC7700_FIXED_FACTOR_U_DFT100M_DIV4                     459
+#define EIC7700_FIXED_FACTOR_U_DFT125M_DIV2                     460
+#define EIC7700_FIXED_FACTOR_U_DFT150M_DIV2                     461
+#define EIC7700_FIXED_FACTOR_U_DFT100M_DIV2                     462
+#define EIC7700_FIXED_FACTOR_U_DFT500M_DIV3                     463
+#define EIC7700_FIXED_FACTOR_U_DFT500M_DIV2                     464
+#define EIC7700_FIXED_FACTOR_SPLL0_TEST_DIV8                    465
+#define EIC7700_FIXED_FACTOR_SPLL1_TEST_DIV6                    466
+#define EIC7700_FIXED_FACTOR_SPLL2_TEST_DIV4                    467
+#define EIC7700_FIXED_FACTOR_U_HSP_RMII_REF_DIV6                468
+#define EIC7700_FIXED_FACTOR_U_DRR_DIV8                         469
+
+
+/*clocks list for consumer*/
+#define EIC7700_CLK_CPU_EXT_SRC_CORE_CLK_0                      500
+#define EIC7700_CLK_CPU_EXT_SRC_CORE_CLK_1                      501
+#define EIC7700_CLK_CPU_EXT_SRC_CORE_CLK_2                      502
+#define EIC7700_CLK_CPU_EXT_SRC_CORE_CLK_3                      503
+#define EIC7700_CLK_CPU_TRACE_CLK_0                             504
+#define EIC7700_CLK_CPU_TRACE_CLK_1                             505
+#define EIC7700_CLK_CPU_TRACE_CLK_2                             506
+#define EIC7700_CLK_CPU_TRACE_CLK_3                             507
+#define EIC7700_CLK_CPU_DEBUG_CLK                               508
+#define EIC7700_CLK_CPU_TRACE_COM_CLK                           509
+#define EIC7700_CLK_CPU_CLK                                     510
+#define EIC7700_CLK_CLK_1M                                      511
+#define EIC7700_CLK_CLK_SYS_CFG                                 512
+#define EIC7700_CLK_CLK_MIPI_TXESC                              513
+#define EIC7700_CLK_NOC_CFG_CLK                                 514
+#define EIC7700_CLK_NOC_NSP_CLK                                 515
+#define EIC7700_CLK_CLK_BOOTSPI                                 516
+#define EIC7700_CLK_CLK_BOOTSPI_CFG                             517
+#define EIC7700_CLK_CLK_U84_CORE_LP                             518
+#define EIC7700_CLK_CLK_SCPU_CORE                               519
+#define EIC7700_CLK_CLK_SCPU_BUS                                520
+#define EIC7700_CLK_CLK_LPCPU_CORE                              521
+#define EIC7700_CLK_CLK_LPCPU_BUS                               522
+#define EIC7700_CLK_GPU_ACLK                                    523
+#define EIC7700_CLK_GPU_GRAY_CLK                                524
+#define EIC7700_CLK_GPU_CFG_CLK                                 525
+#define EIC7700_CLK_CLK_DSP_ROOT                                526
+#define EIC7700_CLK_DSPT_ACLK                                   527
+#define EIC7700_CLK_DSPT_CFG_CLK                                528
+#define EIC7700_CLK_CLK_D2DDR_ACLK                              529
+#define EIC7700_CLK_D2D_ACLK                                    530
+#define EIC7700_CLK_D2D_CFG_CLK                                 531
+#define EIC7700_CLK_TCU_ACLK                                    532
+#define EIC7700_CLK_TCU_CFG_CLK                                 533
+#define EIC7700_CLK_DDRT_CFG_CLK                                534
+#define EIC7700_CLK_DDRT0_P0_ACLK                               535
+#define EIC7700_CLK_DDRT0_P1_ACLK                               536
+#define EIC7700_CLK_DDRT0_P2_ACLK                               537
+#define EIC7700_CLK_DDRT0_P3_ACLK                               538
+#define EIC7700_CLK_DDRT0_P4_ACLK                               539
+#define EIC7700_CLK_DDRT1_P0_ACLK                               540
+#define EIC7700_CLK_DDRT1_P1_ACLK                               541
+#define EIC7700_CLK_DDRT1_P2_ACLK                               542
+#define EIC7700_CLK_DDRT1_P3_ACLK                               543
+#define EIC7700_CLK_DDRT1_P4_ACLK                               544
+#define EIC7700_CLK_HSP_ACLK                                    545
+#define EIC7700_CLK_HSP_CFG_CLK                                 546
+#define EIC7700_CLK_HSP_SATA_RBC_CLK                            547
+#define EIC7700_CLK_HSP_SATA_OOB_CLK                            548
+#define EIC7700_CLK_HSP_SATA_PMALIVE_CLK                        549
+#define EIC7700_CLK_HSP_ETH_APP_CLK                             550
+#define EIC7700_CLK_HSP_ETH_CSR_CLK                             551
+#define EIC7700_CLK_HSP_ETH0_CORE_CLK                           552
+#define EIC7700_CLK_HSP_ETH1_CORE_CLK                           553
+#define EIC7700_CLK_HSP_MSHC0_CORE_CLK                          554
+#define EIC7700_CLK_HSP_MSHC1_CORE_CLK                          555
+#define EIC7700_CLK_HSP_MSHC2_CORE_CLK                          556
+#define EIC7700_CLK_HSP_MSHC0_TMR_CLK                           557
+#define EIC7700_CLK_HSP_MSHC1_TMR_CLK                           558
+#define EIC7700_CLK_HSP_MSHC2_TMR_CLK                           559
+#define EIC7700_CLK_HSP_USB0_SUSPEND_CLK                        560
+#define EIC7700_CLK_HSP_USB1_SUSPEND_CLK                        561
+#define EIC7700_CLK_PCIET_ACLK                                  562
+#define EIC7700_CLK_PCIET_CFG_CLK                               563
+#define EIC7700_CLK_PCIET_CR_CLK                                564
+#define EIC7700_CLK_PCIET_AUX_CLK                               565
+#define EIC7700_CLK_NPU_ACLK                                    566
+#define EIC7700_CLK_NPU_CFG_CLK                                 567
+#define EIC7700_CLK_CLK_NPU_LLC_SRC0                            568
+#define EIC7700_CLK_CLK_NPU_LLC_SRC1                            569
+#define EIC7700_CLK_NPU_LLC_ACLK                                570
+#define EIC7700_CLK_CLK_NPU_CORE_ST1                            571
+#define EIC7700_CLK_NPU_CLK                                     572
+#define EIC7700_CLK_NPU_E31_CLK                                 573
+#define EIC7700_CLK_CLK_VI_ACLK_ST1                             574
+#define EIC7700_CLK_VI_ACLK                                     575
+#define EIC7700_CLK_VI_DVP_CLK                                  576
+#define EIC7700_CLK_VI_CFG_CLK                                  577
+#define EIC7700_CLK_VI_DIG_DW_CLK                               578
+#define EIC7700_CLK_VI_DIG_ISP_CLK                              579
+#define EIC7700_CLK_VI_SHUTTER_0                                580
+#define EIC7700_CLK_VI_SHUTTER_1                                581
+#define EIC7700_CLK_VI_SHUTTER_2                                582
+#define EIC7700_CLK_VI_SHUTTER_3                                583
+#define EIC7700_CLK_VI_SHUTTER_4                                584
+#define EIC7700_CLK_VI_SHUTTER_5                                585
+#define EIC7700_CLK_VI_PHY_TXCLKESC                             586
+#define EIC7700_CLK_VI_PHY_CFG                                  587
+#define EIC7700_CLK_VO_ACLK                                     588
+#define EIC7700_CLK_VO_CFG_CLK                                  589
+#define EIC7700_CLK_VO_HDMI_IESMCLK                             590
+#define EIC7700_CLK_VO_PIXEL_CLK                                591
+#define EIC7700_CLK_VO_I2S_MCLK                                 592
+#define EIC7700_CLK_VO_CR_CLK                                   593
+#define EIC7700_CLK_VO_CEC_CLK                                  594
+#define EIC7700_CLK_CLK_VC_ROOT                                 595
+#define EIC7700_CLK_VC_ACLK                                     596
+#define EIC7700_CLK_VC_CFG_CLK                                  597
+#define EIC7700_CLK_VC_JE_CLK                                   598
+#define EIC7700_CLK_VC_JD_CLK                                   599
+#define EIC7700_CLK_VC_VE_CLK                                   600
+#define EIC7700_CLK_VC_VD_CLK                                   601
+#define EIC7700_CLK_G2D_CFG_CLK                                 602
+#define EIC7700_CLK_CLK_G2D_ST2                                 603
+#define EIC7700_CLK_G2D_CLK                                     604
+#define EIC7700_CLK_G2D_ACLK                                    605
+#define EIC7700_CLK_CLK_RESERVED                                606
+#define EIC7700_CLK_PVT_CLK_0                                   607
+#define EIC7700_CLK_PVT_CLK_1                                   608
+#define EIC7700_CLK_HSP_RMII_REF_0                              609
+#define EIC7700_CLK_HSP_RMII_REF_1                              610
+#define EIC7700_CLK_HSP_SATA_PHY_REF                            611
+#define EIC7700_CLK_AONDMA_CFG                                  612
+#define EIC7700_CLK_CLK_AONDMA_AXI_ST3                          613
+#define EIC7700_CLK_AONDMA_ACLK                                 614
+#define EIC7700_CLK_AON_ACLK                                    615
+#define EIC7700_CLK_TIMER_CLK_0                                 616      //AON timer
+#define EIC7700_CLK_TIMER_CLK_1                                 617
+#define EIC7700_CLK_TIMER_CLK_2                                 618
+#define EIC7700_CLK_TIMER_CLK_3                                 619
+#define EIC7700_CLK_TIMER_PCLK_0                                620
+#define EIC7700_CLK_TIMER_PCLK_1                                621
+#define EIC7700_CLK_TIMER_PCLK_2                                622
+#define EIC7700_CLK_TIMER_PCLK_3                                623
+#define EIC7700_CLK_TIMER3_CLK8                                 624
+#define EIC7700_CLK_CLK_RTC_CFG                                 625  // AON rtc
+#define EIC7700_CLK_CLK_RTC                                     626  // AON rtc
+#define EIC7700_CLK_CLK_U84_RTC_TOGGLE                          627
+#define EIC7700_CLK_UNUSED_1                                    628
+#define EIC7700_CLK_CLK_PKA_CFG                                 629
+#define EIC7700_CLK_CLK_SPACC_CFG                               630
+#define EIC7700_CLK_CLK_CRYPTO                                  631
+#define EIC7700_CLK_CLK_TRNG_CFG                                632
+#define EIC7700_CLK_CLK_OTP_CFG                                 633
+#define EIC7700_CLK_CLMM_CFG_CLK                                634
+#define EIC7700_CLK_CLMM_DEB_CLK                                635
+#define EIC7700_CLK_DDR_PLL_BYP_CLK                             636
+#define EIC7700_CLK_DDR_PLL_REF_AND_DFI_CLK                     637
+#define EIC7700_CLK_DDR_RX_TEST_CLK                             638
+#define EIC7700_CLK_MAILBOX_0                                   638
+#define EIC7700_CLK_MAILBOX_1                                   639
+#define EIC7700_CLK_MAILBOX_2                                   640
+#define EIC7700_CLK_MAILBOX_3                                   641
+#define EIC7700_CLK_MAILBOX_4                                   642
+#define EIC7700_CLK_MAILBOX_5                                   643
+#define EIC7700_CLK_MAILBOX_6                                   644
+#define EIC7700_CLK_MAILBOX_7                                   645
+#define EIC7700_CLK_MAILBOX_8                                   646
+#define EIC7700_CLK_MAILBOX_9                                   647
+#define EIC7700_CLK_MAILBOX_10                                  648
+#define EIC7700_CLK_MAILBOX_11                                  649
+#define EIC7700_CLK_MAILBOX_12                                  650
+#define EIC7700_CLK_MAILBOX_13                                  651
+#define EIC7700_CLK_MAILBOX_14                                  652
+#define EIC7700_CLK_MAILBOX_15                                  653
+#define EIC7700_CLK_LSP_I2C0_PCLK                               654
+#define EIC7700_CLK_LSP_I2C1_PCLK                               655
+#define EIC7700_CLK_LSP_I2C2_PCLK                               656
+#define EIC7700_CLK_LSP_I2C3_PCLK                               657
+#define EIC7700_CLK_LSP_I2C4_PCLK                               658
+#define EIC7700_CLK_LSP_I2C5_PCLK                               659
+#define EIC7700_CLK_LSP_I2C6_PCLK                               660
+#define EIC7700_CLK_LSP_I2C7_PCLK                               661
+#define EIC7700_CLK_LSP_I2C8_PCLK                               662
+#define EIC7700_CLK_LSP_I2C9_PCLK                               663
+#define EIC7700_CLK_LSP_WDT0_PCLK                               664
+#define EIC7700_CLK_LSP_WDT1_PCLK                               665
+#define EIC7700_CLK_LSP_WDT2_PCLK                               666
+#define EIC7700_CLK_LSP_WDT3_PCLK                               667
+#define EIC7700_CLK_LSP_SSI0_PCLK                               668
+#define EIC7700_CLK_LSP_SSI1_PCLK                               669
+#define EIC7700_CLK_LSP_PVT_PCLK                                670
+#define EIC7700_CLK_AON_I2C0_PCLK                               671
+#define EIC7700_CLK_AON_I2C1_PCLK                               672
+#define EIC7700_CLK_LSP_UART0_PCLK                              673
+#define EIC7700_CLK_LSP_UART1_PCLK                              674
+#define EIC7700_CLK_LSP_UART2_PCLK                              675
+#define EIC7700_CLK_LSP_UART3_PCLK                              676
+#define EIC7700_CLK_LSP_UART4_PCLK                              677
+#define EIC7700_CLK_LSP_TIMER_PCLK                              678         //LSP timer
+#define EIC7700_CLK_LSP_FAN_PCLK                                679
+#define EIC7700_CLK_DSP_ACLK_0                                  680
+#define EIC7700_CLK_DSP_ACLK_1                                  681
+#define EIC7700_CLK_DSP_ACLK_2                                  682
+#define EIC7700_CLK_DSP_ACLK_3                                  683
+
+#define EIC7700_CLK_VC_JE_PCLK                                  685
+#define EIC7700_CLK_VC_JD_PCLK                                  686
+#define EIC7700_CLK_VC_VE_PCLK                                  687
+#define EIC7700_CLK_VC_VD_PCLK                                  688
+#define EIC7700_CLK_VC_MON_PCLK                                 689
+
+#define EIC7700_CLK_HSP_DMA0_CLK                                690
+
+#define EIC7700_NR_CLKS                                         700
+
+/* run frquency */
+#define CLK_FREQ_1800M					1800000000
+#define CLK_FREQ_1700M					1700000000
+#define CLK_FREQ_1600M					1600000000
+#define CLK_FREQ_1500M					1500000000
+#define CLK_FREQ_1400M					1400000000
+#define CLK_FREQ_1300M					1300000000
+#define CLK_FREQ_1200M					1200000000
+#define CLK_FREQ_1000M					1000000000
+#define CLK_FREQ_900M					900000000
+#define CLK_FREQ_800M					800000000
+#define CLK_FREQ_700M					700000000
+#define CLK_FREQ_600M					600000000
+#define CLK_FREQ_500M					500000000
+#define CLK_FREQ_400M					400000000
+#define CLK_FREQ_200M					200000000
+#define CLK_FREQ_100M					100000000
+#define CLK_FREQ_24M					24000000
+
+#define APLL_HIGH_FREQ					983040000
+#define APLL_LOW_FREQ 					225792000
+
+#endif /*endif __DTS_EIC7700_CLOCK_H*/
diff --git a/include/dt-bindings/interconnect/eic7700.h b/include/dt-bindings/interconnect/eic7700.h
new file mode 100644
index 000000000000..984b7cc0840f
--- /dev/null
+++ b/include/dt-bindings/interconnect/eic7700.h
@@ -0,0 +1,141 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Interconnect driver for Eswin EIC7700 SoC
+ *
+ * Copyright (C) 2022  Beiging Eswin Co. Ltd
+ * Author: Huangyifeng <huangyifeng@eswincomputing.com>
+ */
+
+#ifndef _DT_BINDINGS_INTERCONNECT_EIC7700_H_
+#define _DT_BINDINGS_INTERCONNECT_EIC7700_H_
+
+#define OFFSET0                              (0)
+#define OFFSET1                              (1)
+#define OFFSET2                              (2)
+#define OFFSET3                              (3)
+#define OFFSET4                              (4)
+#define OFFSET5                              (5)
+#define OFFSET6                              (6)
+#define OFFSET7                              (7)
+#define OFFSET8                              (8)
+#define OFFSET9                              (9)
+#define OFFSET10                             (10)
+#define OFFSET11                             (11)
+#define OFFSET12                             (12)
+#define OFFSET13                             (13)
+#define OFFSET14                             (14)
+#define OFFSET15                             (15)
+#define OFFSET16                             (16)
+#define OFFSET17                             (17)
+#define OFFSET18                             (18)
+#define OFFSET19                             (19)
+#define OFFSET20                             (20)
+#define OFFSET21                             (21)
+#define OFFSET22                             (22)
+#define OFFSET23                             (23)
+
+#define OFFSET31                             (31)
+
+/*sideband manager module id defination*/
+/*sys noc*/
+#define SBM_AON_SNOC_SP0	0
+#define SBM_DSPT_SNOC		1
+#define SBM_JTAG_SNOC		2
+#define SBM_MCPUT_SNOC_D2D	3
+#define SBM_MCPUT_SNOC_MP	4
+#define SBM_MCPUT_SNOC_SP0	5
+#define SBM_MCPUT_SNOC_SP1	6
+#define SBM_NPU_SNOC_SP0	7
+#define SBM_NPU_SNOC_SP1	8
+#define SBM_PCIET_SNOC_P	9
+#define SBM_SPISLV_PCIET_SNOC	10
+#define SBM_TBU4_SNOC		11
+#define SBM_TCU_SNOC		12
+#define SBM_SNOC_AON		13
+#define SBM_SNOC_DDR0_P1	14
+#define SBM_SNOC_DDR0_P2	15
+#define SBM_SNOC_DDR1_P1	16
+#define SBM_SNOC_DDR1_P2	17
+#define SBM_SNOC_DSPT		18
+#define SBM_SNOC_MCPUT_D2D	19
+#define SBM_SNOC_NPU		20
+#define SBM_SNOC_PCIET		21
+
+/*cfg noc*/
+#define SBM_CLMM		30
+#define SBM_CNOC_AON		31
+#define SBM_CNOC_DDRT0_CTRL	32
+#define SBM_CNOC_DDRT0_PHY	33
+#define SBM_CNOC_DDRT1_CTRL	34
+#define SBM_CNOC_DDRT1_PHY	35
+#define SBM_CNOC_DSPT		36
+#define SBM_CNOC_GPU		37
+#define SBM_CNOC_HSP		38
+#define SBM_CNOC_LSP_APB2	39
+#define SBM_CNOC_LSP_APB3	40
+#define SBM_CNOC_LSP_APB4	41
+#define SBM_CNOC_LSP_APB6	42
+#define SBM_CNOC_MCPUT_D2D	43
+#define SBM_CNOC_NPU		44
+#define SBM_CNOC_PCIET_P	45
+#define SBM_CNOC_PCIET_X	46
+#define SBM_CNOC_TCU		47
+#define SBM_CNOC_VC		48
+#define SBM_CNOC_VI		49
+#define SBM_CNOC_VO		50
+
+/*llc noc*/
+#define SBM_LNOC_NPU_LLC0		60
+#define SBM_LNOC_NPU_LLC1		61
+#define SBM_LNOC_DDRT0_P0		62
+#define SBM_LNOC_DDRT1_P0		63
+
+/*media noc*/
+#define SBM_MNOC_GPU			70
+#define SBM_MNOC_TBU2			71
+#define SBM_MNOC_VC			72
+#define SBM_MNOC_DDRT0_P3		73
+#define SBM_MNOC_DDRT1_P3		74
+
+/*realtime noc*/
+#define SBM_RNOC_TBU0			80
+#define SBM_RNOC_VO			81
+#define SBM_RNOC_DDRT0_P4		82
+#define SBM_RNOC_DDRT1_P4		83
+
+/*RouteID defination*/
+#define        aon_snoc_sp0_I_O        0x0
+#define        dspt_snoc_I_O           0x1
+#define        jtag_snoc_I_O           0x2
+#define        mcput_snoc_d2d_I_O      0x3
+#define        mcput_snoc_mp_I_O       0x4
+#define        mcput_snoc_sp0_I_O      0x5
+#define        mcput_snoc_sp1_I_O      0x6
+#define        mnoc_snoc_I_O           0x7
+#define        npu_snoc_sp0_I_O        0x8
+#define        npu_snoc_sp1_I_O        0x9
+#define        pciet_snoc_p_I_O        0xA
+#define        rnoc_snoc_I_O           0xB
+#define        spislv_tbu3_snoc_I_O    0xC
+#define        tbu4_snoc_I_O           0xD
+#define        tcu_snoc_I_O            0xE
+#define        RESERVED0               0xF
+
+#define        snoc_aon_T_O            0x0
+#define        snoc_cnoc_T_O           0x1
+#define        snoc_ddrt0_p1_T_O       0x2
+#define        snoc_ddrt0_p2_T_O       0x3
+#define        snoc_ddrt1_p1_T_O       0x4
+#define        snoc_ddrt1_p2_T_O       0x5
+#define        snoc_dspt_T_O           0x6
+#define        snoc_lnoc_T_O           0x7
+#define        snoc_mcput_d2d_T_O      0x8
+#define        snoc_mnoc_T_O           0x9
+#define        snoc_npu_T_O            0xA
+#define        snoc_pciet_T_O          0xB
+#define        snoc_rnoc_T_O           0xC
+#define        snoc_service_T_O        0xD
+#define        RESERVED1               0xE
+#define        RESERVED2               0xF
+
+#endif /* _DT_BINDINGS_INTERCONNECT_EIC7700_H_ */
diff --git a/include/dt-bindings/mailbox/eswin-mailbox.h b/include/dt-bindings/mailbox/eswin-mailbox.h
new file mode 100644
index 000000000000..1c82418dbadc
--- /dev/null
+++ b/include/dt-bindings/mailbox/eswin-mailbox.h
@@ -0,0 +1,88 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * ESWIN Mailbox Driver
+ *
+ * Copyright 2024, Beijing ESWIN Computing Technology Co., Ltd.. All rights reserved.
+ * SPDX-License-Identifier: GPL-2.0
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, version 2.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <https://www.gnu.org/licenses/>.
+ *
+ * Authors: HuangYiFeng<huangyifeng@eswincomputing.com>
+ */
+
+#ifndef _DTS_ESWIN_MAILBOX_H_
+#define _DTS_ESWIN_MAILBOX_H_
+
+#define ESWIN_MAILBOX_U84_TO_SCPU_REG_BASE   0x50a00000 /*maibox 0*/
+#define ESWIN_MAILBOX_SCPU_TO_U84_REG_BASE   0x50a10000 /*maibox 1*/
+
+#define ESWIN_MAILBOX_U84_TO_LPCPU_REG_BASE  0x50a20000 /*maibox 2*/
+#define ESWIN_MAILBOX_LPCPU_TO_U84_REG_BASE  0x50a30000 /*maibox 3*/
+
+#define ESWIN_MAILBOX_U84_TO_NPU_0_REG_BASE  0x50a40000 /*maibox 4*/
+#define ESWIN_MAILBOX_NPU_0_TO_U84_REG_BASE  0x50a50000 /*maibox 5*/
+
+#define ESWIN_MAILBOX_U84_TO_NPU_1_REG_BASE  0x50a60000 /*maibox 6*/
+#define ESWIN_MAILBOX_NP1_0_TO_U84_REG_BASE  0x50a70000 /*maibox 7*/
+
+#define ESWIN_MAILBOX_U84_TO_DSP_0_REG_BASE  0x50a80000 /*maibox 8*/
+#define ESWIN_MAILBOX_DSP_0_TO_U84_REG_BASE  0x50a90000 /*maibox 9*/
+
+#define ESWIN_MAILBOX_U84_TO_DSP_1_REG_BASE  0x50aa0000 /*maibox 10*/
+#define ESWIN_MAILBOX_DSP_1_TO_U84_REG_BASE  0x50ab0000 /*maibox 11*/
+
+#define ESWIN_MAILBOX_U84_TO_DSP_2_REG_BASE  0x50ac0000 /*maibox 12*/
+#define ESWIN_MAILBOX_DSP_2_TO_U84_REG_BASE  0x50ad0000 /*maibox 13*/
+
+#define ESWIN_MAILBOX_U84_TO_DSP_3_REG_BASE  0x50ae0000 /*maibox 14*/
+#define ESWIN_MAILBOX_DSP_3_TO_U84_REG_BASE  0x50af0000 /*maibox 15*/
+
+#define BIT0                              (1 << 0)
+#define BIT1                              (1 << 1)
+#define BIT2                              (1 << 2)
+#define BIT3                              (1 << 3)
+#define BIT4                              (1 << 4)
+#define BIT5                              (1 << 5)
+#define BIT6                              (1 << 6)
+#define BIT7                              (1 << 7)
+#define BIT8                              (1 << 8)
+#define BIT9                              (1 << 9)
+#define BIT10                             (1 << 10)
+#define BIT11                             (1 << 11)
+#define BIT12                             (1 << 12)
+#define BIT13                             (1 << 13)
+#define BIT14                             (1 << 14)
+#define BIT31                             (1 << 31)
+
+#define ESWIN_MAILBOX_WR_LOCK_BIT_U84      BIT0
+#define ESWIN_MAILBOX_WR_LOCK_BIT_SCPU     BIT1
+#define ESWIN_MAILBOX_WR_LOCK_BIT_LPCPU    BIT2
+#define ESWIN_MAILBOX_WR_LOCK_BIT_NPU_0    BIT3
+#define ESWIN_MAILBOX_WR_LOCK_BIT_NPU_1    BIT4
+#define ESWIN_MAILBOX_WR_LOCK_BIT_DSP_0    BIT5
+#define ESWIN_MAILBOX_WR_LOCK_BIT_DSP_1    BIT6
+#define ESWIN_MAILBOX_WR_LOCK_BIT_DSP_2    BIT7
+#define ESWIN_MAILBOX_WR_LOCK_BIT_DSP_3    BIT8
+
+
+#define ESWIN_MAIBOX_U84_IRQ_BIT           BIT0
+#define ESWIN_MAIBOX_SCPU_IRQ_BIT          BIT1
+#define ESWIN_MAIBOX_LPCPU_IRQ_BIT         BIT2
+#define ESWIN_MAIBOX_NPU_0_IRQ_BIT         BIT3
+#define ESWIN_MAIBOX_NPU_1_IRQ_BIT         BIT4
+#define ESWIN_MAIBOX_DSP_0_IRQ_BIT         BIT5
+#define ESWIN_MAIBOX_DSP_1_IRQ_BIT         BIT6
+#define ESWIN_MAIBOX_DSP_2_IRQ_BIT         BIT7
+#define ESWIN_MAIBOX_DSP_3_IRQ_BIT         BIT8
+
+#endif /* _DTS_ESWIN_MAILBOX_H_ */
diff --git a/include/dt-bindings/memory/eic7700-sid.h b/include/dt-bindings/memory/eic7700-sid.h
new file mode 100644
index 000000000000..0fa589ec93b1
--- /dev/null
+++ b/include/dt-bindings/memory/eic7700-sid.h
@@ -0,0 +1,138 @@
+#ifndef DT_BINDINGS_MEMORY_EIC7700_SID_H
+#define DT_BINDINGS_MEMORY_EIC7700_SID_H
+
+#define EIC7700_SID_DMA0	1
+
+#define EIC7700_SID_JDEC	2
+
+#define EIC7700_SID_JENC	3
+
+/* NPU DMA*/
+#define EIC7700_SID_NPU_DMA	4
+
+/* NPU-E31 */
+#define EIC7700_SID_NPU_E31	5
+
+/* Video In */
+#define EIC7700_SID_ISP0	6
+
+//#define EIC7700_SID_ISP1	EIC7700_SID_ISP0
+
+#define EIC7700_SID_DW		8
+
+#define EIC7700_SID_DVP		9
+
+/* High Speed */
+#define EIC7700_SID_USB0	10
+
+#define EIC7700_SID_USB1	11
+
+#define EIC7700_SID_ETH0	12
+
+#define EIC7700_SID_ETH1	13
+
+#define EIC7700_SID_SATA	14
+
+#define EIC7700_SID_EMMC0	15
+
+#define EIC7700_SID_SD0		16
+
+#define EIC7700_SID_SD1		17
+
+
+/* DSP */
+#define EIC7700_SID_DSP_0	18
+#define EIC7700_SID_DSP_1	19
+#define EIC7700_SID_DSP_2	20
+#define EIC7700_SID_DSP_3	21
+
+/* CODEC */
+//#define EIC7700_SID_VDEC	EIC7700_SID_JDEC
+
+//#define EIC7700_SID_VENC	EIC7700_SID_JENC
+
+/*** AON subsystem ***/
+/* Secure CPU */
+#define EIC7700_SID_SCPU	24
+#define SCPU_SID_REG_OFFSET	0x1004
+
+/* Low power CPU */
+#define EIC7700_SID_LCPU	25
+#define LCPU_SID_REG_OFFSET	0x2004
+
+/* Always on, DMA1 */
+#define EIC7700_SID_DMA1	26
+#define DMA1_SID_REG_OFFSET	0x3004
+
+/* crypt */
+//#define EIC7700_SID_CRYPT	EIC7700_SID_SCPU
+#define CRYPT_SID_REG_OFFSET	0x4004
+
+///*** for iova mapping test ***/
+//#define EIC7700_SID_DEV_FOO_A        28
+//#define EIC7700_SID_DEV_FOO_B        29
+//#define EIC7700_SID_DEV_FOO_FOR_DIE1	30
+
+
+/*** tbu id ***/
+/* tbu_id: bit[3:0] is for major, bit[7:4] is for minor;
+	For example, tbu of dsp3 is tbu7_3, the bu 0x73. It measn tbu7_3
+*/
+#define	EIC7700_TBUID_0x0	0x0
+
+#define	EIC7700_TBUID_0x10	0x10
+#define	EIC7700_TBUID_0x11	0x11
+#define	EIC7700_TBUID_0x12	0x12
+#define	EIC7700_TBUID_0x13	0x13
+
+#define	EIC7700_TBUID_0x2	0x2
+
+#define	EIC7700_TBUID_0x3	0x3
+
+#define	EIC7700_TBUID_0x4	0x4
+
+#define	EIC7700_TBUID_0x5	0x5
+
+#define	EIC7700_TBUID_0x70	0x70
+#define	EIC7700_TBUID_0x71	0x71
+#define	EIC7700_TBUID_0x72	0x72
+#define	EIC7700_TBUID_0x73	0x73
+
+#define	EIC7700_TBUID_0xF00	0xF00	// simulation for EIC7700_SID_DEV_FOO_A/B, No real tbu attached infact
+
+
+/* For better use by devices in dts, create tbu alias for devices*/
+#define EIC7700_TBUID_ISP	EIC7700_TBUID_0x0
+#define EIC7700_TBUID_DW	EIC7700_TBUID_ISP
+
+#define EIC7700_TBUID_VDEC	EIC7700_TBUID_0x10
+#define EIC7700_TBUID_VENC	EIC7700_TBUID_0x11
+#define EIC7700_TBUID_JENC	EIC7700_TBUID_0x12
+#define EIC7700_TBUID_JDEC	EIC7700_TBUID_0x13
+
+//high speed modules share the same tbu2
+#define EIC7700_TBUID_DMA0	EIC7700_TBUID_0x2
+#define EIC7700_TBUID_USB	EIC7700_TBUID_DMA0
+#define EIC7700_TBUID_ETH	EIC7700_TBUID_DMA0
+#define EIC7700_TBUID_SATA	EIC7700_TBUID_DMA0
+#define EIC7700_TBUID_EMMC	EIC7700_TBUID_DMA0
+#define EIC7700_TBUID_SD	EIC7700_TBUID_DMA0
+
+#define EIC7700_TBUID_PCIE	EIC7700_TBUID_0x3
+
+//scpu, crypto, lpcpu, dma1 share the same tbu4
+#define EIC7700_TBUID_SCPU	EIC7700_TBUID_0x4
+#define EIC7700_TBUID_CRYPT	EIC7700_TBUID_SCPU
+#define EIC7700_TBUID_DMA1	EIC7700_TBUID_SCPU
+#define EIC7700_TBUID_LPCPU	EIC7700_TBUID_SCPU
+
+//npu
+#define EIC7700_TBUID_NPU	EIC7700_TBUID_0x5
+
+//dsp
+#define EIC7700_TBUID_DSP0	EIC7700_TBUID_0x70
+#define EIC7700_TBUID_DSP1	EIC7700_TBUID_0x71
+#define EIC7700_TBUID_DSP2	EIC7700_TBUID_0x72
+#define EIC7700_TBUID_DSP3	EIC7700_TBUID_0x73
+
+#endif
diff --git a/include/dt-bindings/reset/eic7700-syscrg.h b/include/dt-bindings/reset/eic7700-syscrg.h
new file mode 100644
index 000000000000..ea1ff1874a85
--- /dev/null
+++ b/include/dt-bindings/reset/eic7700-syscrg.h
@@ -0,0 +1,693 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * ESWIN SysCrg Definition
+ *
+ * Copyright 2024, Beijing ESWIN Computing Technology Co., Ltd.. All rights reserved.
+ * SPDX-License-Identifier: GPL-2.0
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, version 2.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <https://www.gnu.org/licenses/>.
+ *
+ * Authors: HuangYiFeng<huangyifeng@eswincomputing.com>
+ */
+
+#ifndef __DT_ESWIN_EIC7700_SYSCRG_H__
+#define __DT_ESWIN_EIC7700_SYSCRG_H__
+
+/*REG OFFSET OF SYS-CRG*/
+
+#define EIC7700_REG_OFFSET_SPLL0_CFG_0                          0X0000
+#define EIC7700_REG_OFFSET_SPLL0_CFG_1                          0X0004
+#define EIC7700_REG_OFFSET_SPLL0_CFG_2                          0X0008
+#define EIC7700_REG_OFFSET_SPLL0_DSKEWCAL                       0X000C
+#define EIC7700_REG_OFFSET_SPLL0_SSC                            0X0010
+#define EIC7700_REG_OFFSET_SPLL1_CFG_0                          0X0014
+#define EIC7700_REG_OFFSET_SPLL1_CFG_1                          0X0018
+#define EIC7700_REG_OFFSET_SPLL1_CFG_2                          0X001C
+#define EIC7700_REG_OFFSET_SPLL1_DSKEWCAL                       0X0020
+#define EIC7700_REG_OFFSET_SPLL1_SSC                            0X0024
+#define EIC7700_REG_OFFSET_SPLL2_CFG_0                          0X0028
+#define EIC7700_REG_OFFSET_SPLL2_CFG_1                          0X002C
+#define EIC7700_REG_OFFSET_SPLL2_CFG_2                          0X0030
+#define EIC7700_REG_OFFSET_SPLL2_DSKEWCAL                       0X0034
+#define EIC7700_REG_OFFSET_SPLL2_SSC                            0X0038
+#define EIC7700_REG_OFFSET_VPLL_CFG_0                           0X003C
+#define EIC7700_REG_OFFSET_VPLL_CFG_1                           0X0040
+#define EIC7700_REG_OFFSET_VPLL_CFG_2                           0X0044
+#define EIC7700_REG_OFFSET_VPLL_DSKEWCAL                        0X0048
+#define EIC7700_REG_OFFSET_VPLL_SSC                             0X004C
+#define EIC7700_REG_OFFSET_APLL_CFG_0                           0X0050
+#define EIC7700_REG_OFFSET_APLL_CFG_1                           0X0054
+#define EIC7700_REG_OFFSET_APLL_CFG_2                           0X0058
+#define EIC7700_REG_OFFSET_APLL_DSKEWCAL                        0X005C
+#define EIC7700_REG_OFFSET_APLL_SSC                             0X0060
+#define EIC7700_REG_OFFSET_MCPUT_PLL_CFG_0                      0X0064
+#define EIC7700_REG_OFFSET_MCPUT_PLL_CFG_1                      0X0068
+#define EIC7700_REG_OFFSET_MCPUT_PLL_CFG_2                      0X006C
+#define EIC7700_REG_OFFSET_MCPUT_PLL_DSKEWCAL                   0X0070
+#define EIC7700_REG_OFFSET_MCPUT_PLL_SSC                        0X0074
+#define EIC7700_REG_OFFSET_DDRT_PLL_CFG_0                       0X0078
+#define EIC7700_REG_OFFSET_DDRT_PLL_CFG_1                       0X007C
+#define EIC7700_REG_OFFSET_DDRT_PLL_CFG_2                       0X0080
+#define EIC7700_REG_OFFSET_DDRT_PLL_DSKEWCAL                    0X0084
+#define EIC7700_REG_OFFSET_DDRT_PLL_SSC                         0X0088
+#define EIC7700_REG_OFFSET_PLL_STATUS                           0X00A4
+#define EIC7700_REG_OFFSET_NOC_CLK_CTRL                         0X100
+#define EIC7700_REG_OFFSET_BOOTSPI_CLK_CTRL                     0X104
+#define EIC7700_REG_OFFSET_BOOTSPI_CFGCLK_CTRL                  0X108
+#define EIC7700_REG_OFFSET_SCPU_CORECLK_CTRL                    0X10C
+#define EIC7700_REG_OFFSET_SCPU_BUSCLK_CTRL                     0X110
+#define EIC7700_REG_OFFSET_LPCPU_CORECLK_CTRL                   0X114
+#define EIC7700_REG_OFFSET_LPCPU_BUSCLK_CTRL                    0X118
+#define EIC7700_REG_OFFSET_TCU_ACLK_CTRL                        0X11C
+#define EIC7700_REG_OFFSET_TCU_CFG_CTRL                         0X120
+#define EIC7700_REG_OFFSET_DDR_CLK_CTRL                         0X124
+#define EIC7700_REG_OFFSET_DDR1_CLK_CTRL                        0X128
+#define EIC7700_REG_OFFSET_GPU_ACLK_CTRL                        0X12C
+#define EIC7700_REG_OFFSET_GPU_CFG_CTRL                         0X130
+#define EIC7700_REG_OFFSET_GPU_GRAY_CTRL                        0X134
+#define EIC7700_REG_OFFSET_DSP_ACLK_CTRL                        0X138
+#define EIC7700_REG_OFFSET_DSP_CFG_CTRL                         0X13C
+#define EIC7700_REG_OFFSET_D2D_ACLK_CTRL                        0X140
+#define EIC7700_REG_OFFSET_D2D_CFG_CTRL                         0X144
+#define EIC7700_REG_OFFSET_HSP_ACLK_CTRL                        0X148
+#define EIC7700_REG_OFFSET_HSP_CFG_CTRL                         0X14C
+#define EIC7700_REG_OFFSET_SATA_RBC_CTRL                        0X150
+#define EIC7700_REG_OFFSET_SATA_OOB_CTRL                        0X154
+#define EIC7700_REG_OFFSET_ETH0_CTRL                            0X158
+#define EIC7700_REG_OFFSET_ETH1_CTRL                            0X15C
+#define EIC7700_REG_OFFSET_MSHC0_CORECLK_CTRL                   0X160
+#define EIC7700_REG_OFFSET_MSHC1_CORECLK_CTRL                   0X164
+#define EIC7700_REG_OFFSET_MSHC2_CORECLK_CTRL                   0X168
+#define EIC7700_REG_OFFSET_MSHC_USB_SLWCLK                      0X16C
+#define EIC7700_REG_OFFSET_PCIE_ACLK_CTRL                       0X170
+#define EIC7700_REG_OFFSET_PCIE_CFG_CTRL                        0X174
+#define EIC7700_REG_OFFSET_NPU_ACLK_CTRL                        0X178
+#define EIC7700_REG_OFFSET_NPU_LLC_CTRL                         0X17C
+#define EIC7700_REG_OFFSET_NPU_CORE_CTRL                        0X180
+#define EIC7700_REG_OFFSET_VI_DWCLK_CTRL                        0X184
+#define EIC7700_REG_OFFSET_VI_ACLK_CTRL                         0X188
+#define EIC7700_REG_OFFSET_VI_DIG_ISP_CLK_CTRL                  0X18C
+#define EIC7700_REG_OFFSET_VI_DVP_CLK_CTRL                      0X190
+#define EIC7700_REG_OFFSET_VI_SHUTTER0                          0X194
+#define EIC7700_REG_OFFSET_VI_SHUTTER1                          0X198
+#define EIC7700_REG_OFFSET_VI_SHUTTER2                          0X19C
+#define EIC7700_REG_OFFSET_VI_SHUTTER3                          0X1A0
+#define EIC7700_REG_OFFSET_VI_SHUTTER4                          0X1A4
+#define EIC7700_REG_OFFSET_VI_SHUTTER5                          0X1A8
+#define EIC7700_REG_OFFSET_VI_PHY_CLKCTRL                       0X1AC
+#define EIC7700_REG_OFFSET_VO_ACLK_CTRL                         0X1B0
+#define EIC7700_REG_OFFSET_VO_IESMCLK_CTRL                      0X1B4
+#define EIC7700_REG_OFFSET_VO_PIXEL_CTRL                        0X1B8
+#define EIC7700_REG_OFFSET_VO_MCLK_CTRL                         0X1BC
+#define EIC7700_REG_OFFSET_VO_PHY_CLKCTRL                       0X1C0
+#define EIC7700_REG_OFFSET_VC_ACLK_CTRL                         0X1C4
+#define EIC7700_REG_OFFSET_VCDEC_ROOTCLK_CTRL                   0X1C8
+#define EIC7700_REG_OFFSET_G2D_CTRL                             0X1CC
+#define EIC7700_REG_OFFSET_VC_CLKEN_CTRL                        0X1D0
+#define EIC7700_REG_OFFSET_JE_CLK_CTRL                          0X1D4
+#define EIC7700_REG_OFFSET_JD_CLK_CTRL                          0X1D8
+#define EIC7700_REG_OFFSET_VD_CLK_CTRL                          0X1DC
+#define EIC7700_REG_OFFSET_VE_CLK_CTRL                          0X1E0
+#define EIC7700_REG_OFFSET_AON_DMA_CLK_CTRL                     0X1E4
+#define EIC7700_REG_OFFSET_TIMER_CLK_CTRL                       0X1E8
+#define EIC7700_REG_OFFSET_RTC_CLK_CTRL                         0X1EC
+#define EIC7700_REG_OFFSET_PKA_CLK_CTRL                         0X1F0
+#define EIC7700_REG_OFFSET_SPACC_CLK_CTRL                       0X1F4
+#define EIC7700_REG_OFFSET_TRNG_CLK_CTRL                        0X1F8
+#define EIC7700_REG_OFFSET_OTP_CLK_CTRL                         0X1FC
+#define EIC7700_REG_OFFSET_LSP_CLK_EN0                          0X200
+#define EIC7700_REG_OFFSET_LSP_CLK_EN1                          0X204
+#define EIC7700_REG_OFFSET_U84_CLK_CTRL                         0X208
+#define EIC7700_REG_OFFSET_SYSCFG_CLK_CTRL                      0X20C
+#define EIC7700_REG_OFFSET_I2C0_CLK_CTRL                        0X210
+#define EIC7700_REG_OFFSET_I2C1_CLK_CTRL                        0X214
+#define EIC7700_REG_OFFSET_DFT_CLK_CTRL                         0X280
+#define EIC7700_REG_OFFSET_SYS_SWRST_VALUE                      0X300
+#define EIC7700_REG_OFFSET_CLR_RST_STATUS                       0X304
+#define EIC7700_REG_OFFSET_DIE_STATUS                           0X308
+#define EIC7700_REG_OFFSET_CLR_BOOT_INFO                        0X30C
+#define EIC7700_REG_OFFSET_SCPU_BOOT_ADDRESS                    0X310
+#define EIC7700_REG_OFFSET_LPCPU_BOOT_ADDRESS                   0X314
+#define EIC7700_REG_OFFSET_NPUE31_BOOT_ADDRESS                  0X318
+#define EIC7700_REG_OFFSET_U84_BOOT_ADDRESS0_HI                 0X31C
+#define EIC7700_REG_OFFSET_U84_BOOT_ADDRESS0_LOW                0X320
+#define EIC7700_REG_OFFSET_U84_BOOT_ADDRESS1_HI                 0X324
+#define EIC7700_REG_OFFSET_U84_BOOT_ADDRESS1_LOW                0X328
+#define EIC7700_REG_OFFSET_U84_BOOT_ADDRESS2_HI                 0X32C
+#define EIC7700_REG_OFFSET_U84_BOOT_ADDRESS2_LOW                0X330
+#define EIC7700_REG_OFFSET_U84_BOOT_ADDRESS3_HI                 0X334
+#define EIC7700_REG_OFFSET_U84_BOOT_ADDRESS3_LOW                0X338
+#define EIC7700_REG_OFFSET_BOOT_SEL_STAT                        0X33C
+#define EIC7700_REG_OFFSET_BOOT_SPI_CFG                         0X340
+#define EIC7700_REG_OFFSET_SNOC_RST_CTRL                        0X400
+#define EIC7700_REG_OFFSET_GPU_RST_CTRL                         0X404
+#define EIC7700_REG_OFFSET_DSP_RST_CTRL                         0X408
+#define EIC7700_REG_OFFSET_D2D_RST_CTRL                         0X40C
+#define EIC7700_REG_OFFSET_DDR_RST_CTRL                         0X410
+#define EIC7700_REG_OFFSET_TCU_RST_CTRL                         0X414
+#define EIC7700_REG_OFFSET_NPU_RST_CTRL                         0X418
+#define EIC7700_REG_OFFSET_HSPDMA_RST_CTRL                      0X41C
+#define EIC7700_REG_OFFSET_PCIE_RST_CTRL                        0X420
+#define EIC7700_REG_OFFSET_I2C_RST_CTRL                         0X424
+#define EIC7700_REG_OFFSET_FAN_RST_CTRL                         0X428
+#define EIC7700_REG_OFFSET_PVT_RST_CTRL                         0X42C
+#define EIC7700_REG_OFFSET_MBOX_RST_CTRL                        0X430
+#define EIC7700_REG_OFFSET_UART_RST_CTRL                        0X434
+#define EIC7700_REG_OFFSET_GPIO_RST_CTRL                        0X438
+#define EIC7700_REG_OFFSET_TIMER_RST_CTRL                       0X43C
+#define EIC7700_REG_OFFSET_SSI_RST_CTRL                         0X440
+#define EIC7700_REG_OFFSET_WDT_RST_CTRL                         0X444
+#define EIC7700_REG_OFFSET_LSP_CFGRST_CTRL                      0X448
+#define EIC7700_REG_OFFSET_U84_RST_CTRL                         0X44C
+#define EIC7700_REG_OFFSET_SCPU_RST_CTRL                        0X450
+#define EIC7700_REG_OFFSET_LPCPU_RST_CTRL                       0X454
+#define EIC7700_REG_OFFSET_VC_RST_CTRL                          0X458
+#define EIC7700_REG_OFFSET_JD_RST_CTRL                          0X45C
+#define EIC7700_REG_OFFSET_JE_RST_CTRL                          0X460
+#define EIC7700_REG_OFFSET_VD_RST_CTRL                          0X464
+#define EIC7700_REG_OFFSET_VE_RST_CTRL                          0X468
+#define EIC7700_REG_OFFSET_G2D_RST_CTRL                         0X46C
+#define EIC7700_REG_OFFSET_VI_RST_CTRL                          0X470
+#define EIC7700_REG_OFFSET_DVP_RST_CTRL                         0X474
+#define EIC7700_REG_OFFSET_ISP0_RST_CTRL                        0X478
+#define EIC7700_REG_OFFSET_ISP1_RST_CTRL                        0X47C
+#define EIC7700_REG_OFFSET_SHUTTER_RST_CTRL                     0X480
+#define EIC7700_REG_OFFSET_VO_PHYRST_CTRL                       0X484
+#define EIC7700_REG_OFFSET_VO_I2SRST_CTRL                       0X488
+#define EIC7700_REG_OFFSET_VO_RST_CTRL                          0X48C
+#define EIC7700_REG_OFFSET_BOOTSPI_RST_CTRL                     0X490
+#define EIC7700_REG_OFFSET_I2C1_RST_CTRL                        0X494
+#define EIC7700_REG_OFFSET_I2C0_RST_CTRL                        0X498
+#define EIC7700_REG_OFFSET_DMA1_RST_CTRL                        0X49C
+#define EIC7700_REG_OFFSET_FPRT_RST_CTRL                        0X4A0
+#define EIC7700_REG_OFFSET_HBLOCK_RST_CTRL                      0X4A4
+#define EIC7700_REG_OFFSET_SECSR_RST_CTRL                       0X4A8
+#define EIC7700_REG_OFFSET_OTP_RST_CTRL                         0X4AC
+#define EIC7700_REG_OFFSET_PKA_RST_CTRL                         0X4B0
+#define EIC7700_REG_OFFSET_SPACC_RST_CTRL                       0X4B4
+#define EIC7700_REG_OFFSET_TRNG_RST_CTRL                        0X4B8
+#define EIC7700_REG_OFFSET_TIMER0_RST_CTRL                      0X4C0
+#define EIC7700_REG_OFFSET_TIMER1_RST_CTRL                      0X4C4
+#define EIC7700_REG_OFFSET_TIMER2_RST_CTRL                      0X4C8
+#define EIC7700_REG_OFFSET_TIMER3_RST_CTRL                      0X4CC
+#define EIC7700_REG_OFFSET_RTC_RST_CTRL                         0X4D0
+#define EIC7700_REG_OFFSET_MNOC_RST_CTRL                        0X4D4
+#define EIC7700_REG_OFFSET_RNOC_RST_CTRL                        0X4D8
+#define EIC7700_REG_OFFSET_CNOC_RST_CTRL                        0X4DC
+#define EIC7700_REG_OFFSET_LNOC_RST_CTRL                        0X4E0
+
+/*
+ * RESET DEV ID  FOR EACH RESET CONSUMER
+ *
+ */
+#define		SNOC_RST_CTRL					0X00
+#define		GPU_RST_CTRL					0X01
+#define		DSP_RST_CTRL					0X02
+#define		D2D_RST_CTRL					0X03
+#define		DDR_RST_CTRL					0X04
+#define		TCU_RST_CTRL					0X05
+#define		NPU_RST_CTRL					0X06
+#define		HSPDMA_RST_CTRL					0X07
+#define		PCIE_RST_CTRL					0X08
+#define		I2C_RST_CTRL					0X09
+#define		FAN_RST_CTRL					0X0A
+#define		PVT_RST_CTRL					0X0B
+#define		MBOX_RST_CTRL					0X0C
+#define		UART_RST_CTRL					0X0D
+#define		GPIO_RST_CTRL					0X0E
+#define		TIMER_RST_CTRL					0X0F
+#define		SSI_RST_CTRL					0X10
+#define		WDT_RST_CTRL					0X11
+#define		LSP_CFGRST_CTRL					0X12
+#define		U84_RST_CTRL					0X13
+#define		SCPU_RST_CTRL					0X14
+#define		LPCPU_RST_CTRL					0X15
+#define		VC_RST_CTRL					0X16
+#define		JD_RST_CTRL					0X17
+#define		JE_RST_CTRL					0X18
+#define		VD_RST_CTRL					0X19
+#define		VE_RST_CTRL					0X1A
+#define		G2D_RST_CTRL					0X1B
+#define		VI_RST_CTRL					0X1C
+#define		DVP_RST_CTRL					0X1D
+#define		ISP0_RST_CTRL					0X1E
+#define		ISP1_RST_CTRL					0X1F
+#define		SHUTTER_RST_CTRL				0X20
+#define		VO_PHYRST_CTRL					0X21
+#define		VO_I2SRST_CTRL					0X22
+#define		VO_RST_CTRL					0X23
+#define		BOOTSPI_RST_CTRL				0X24
+#define		I2C1_RST_CTRL					0X25
+#define		I2C0_RST_CTRL					0X26
+#define		DMA1_RST_CTRL					0X27
+#define		FPRT_RST_CTRL					0X28
+#define		HBLOCK_RST_CTRL					0X29
+#define		SECSR_RST_CTRL					0X2A
+#define		OTP_RST_CTRL					0X2B
+#define		PKA_RST_CTRL					0X2C
+#define		SPACC_RST_CTRL					0X2D
+#define		TRNG_RST_CTRL					0X2E
+#define		RESERVED					0X2F
+#define		TIMER0_RST_CTRL					0X30
+#define		TIMER1_RST_CTRL					0X31
+#define		TIMER2_RST_CTRL					0X32
+#define		TIMER3_RST_CTRL					0X33
+#define		RTC_RST_CTRL					0X34
+#define		MNOC_RST_CTRL					0X35
+#define		RNOC_RST_CTRL					0X36
+#define		CNOC_RST_CTRL					0X37
+#define		LNOC_RST_CTRL					0X38
+
+#define BIT0                              (1 << 0)
+#define BIT1                              (1 << 1)
+#define BIT2                              (1 << 2)
+#define BIT3                              (1 << 3)
+#define BIT4                              (1 << 4)
+#define BIT5                              (1 << 5)
+#define BIT6                              (1 << 6)
+#define BIT7                              (1 << 7)
+#define BIT8                              (1 << 8)
+#define BIT9                              (1 << 9)
+#define BIT10                             (1 << 10)
+#define BIT11                             (1 << 11)
+#define BIT12                             (1 << 12)
+#define BIT13                             (1 << 13)
+#define BIT14                             (1 << 14)
+#define BIT15                             (1 << 15)
+#define BIT16                             (1 << 16)
+#define BIT17                             (1 << 17)
+#define BIT18                             (1 << 18)
+#define BIT19                             (1 << 19)
+#define BIT20                             (1 << 20)
+#define BIT21                             (1 << 21)
+#define BIT22                             (1 << 22)
+#define BIT23                             (1 << 23)
+#define BIT24                             (1 << 24)
+#define BIT25                             (1 << 25)
+#define BIT26                             (1 << 26)
+#define BIT27                             (1 << 27)
+#define BIT28                             (1 << 28)
+#define BIT29                             (1 << 29)
+#define BIT30                             (1 << 30)
+#define BIT31                             (1 << 31)
+
+/*
+	CONSUMER RESET CONTROL BIT
+*/
+/*SNOC*/
+#define		SW_NOC_NSP_RSTN						BIT0
+#define		SW_NOC_CFG_RSTN						BIT1
+#define		SW_RNOC_NSP_RSTN					BIT2
+#define		SW_SNOC_TCU_ARSTN					BIT3
+#define		SW_SNOC_U84_ARSTN					BIT4
+#define		SW_SNOC_PCIET_XSRSTN					BIT5
+#define		SW_SNOC_PCIET_XMRSTN					BIT6
+#define		SW_SNOC_PCIET_PRSTN					BIT7
+#define		SW_SNOC_NPU_ARSTN					BIT8
+#define		SW_SNOC_JTAG_ARSTN					BIT9
+#define		SW_SNOC_DSPT_ARSTN					BIT10
+#define		SW_SNOC_DDRC1_P2_ARSTN					BIT11
+#define		SW_SNOC_DDRC1_P1_ARSTN					BIT12
+#define		SW_SNOC_DDRC0_P2_ARSTN					BIT13
+#define		SW_SNOC_DDRC0_P1_ARSTN					BIT14
+#define		SW_SNOC_D2D_ARSTN					BIT15
+#define		SW_SNOC_AON_ARSTN					BIT16
+
+/*GPU*/
+#define		SW_GPU_AXI_RSTN						BIT0
+#define		SW_GPU_CFG_RSTN						BIT1
+#define		SW_GPU_GRAY_RSTN					BIT2
+#define		SW_GPU_JONES_RSTN					BIT3
+#define		SW_GPU_SPU_RSTN						BIT4
+
+/*DSP*/
+#define		SW_DSP_AXI_RSTN						BIT0
+#define		SW_DSP_CFG_RSTN						BIT1
+#define		SW_DSP_DIV4_RSTN					BIT2
+#define		SW_DSP_DIV_RSTN_0					BIT4
+#define		SW_DSP_DIV_RSTN_1					BIT5
+#define		SW_DSP_DIV_RSTN_2					BIT6
+#define		SW_DSP_DIV_RSTN_3					BIT7
+
+/*D2D*/
+#define		SW_D2D_AXI_RSTN						BIT0
+#define		SW_D2D_CFG_RSTN						BIT1
+#define		SW_D2D_PRST_N						BIT2
+#define		SW_D2D_RAW_PCS_RST_N					BIT4
+#define		SW_D2D_RX_RST_N						BIT5
+#define		SW_D2D_TX_RST_N						BIT6
+#define		SW_D2D_CORE_RST_N					BIT7
+
+/*TCU*/
+#define		SW_TCU_AXI_RSTN						BIT0
+#define		SW_TCU_CFG_RSTN						BIT1
+#define		TBU_RSTN_0						BIT4
+#define		TBU_RSTN_1						BIT5
+#define		TBU_RSTN_2						BIT6
+#define		TBU_RSTN_3						BIT7
+#define		TBU_RSTN_4						BIT8
+#define		TBU_RSTN_5						BIT9
+#define		TBU_RSTN_6						BIT10
+#define		TBU_RSTN_7						BIT11
+#define		TBU_RSTN_8						BIT12
+#define		TBU_RSTN_9						BIT13
+#define		TBU_RSTN_10						BIT14
+#define		TBU_RSTN_11						BIT15
+#define		TBU_RSTN_12						BIT16
+#define		TBU_RSTN_13						BIT17
+#define		TBU_RSTN_14						BIT18
+#define		TBU_RSTN_15						BIT19
+#define		TBU_RSTN_16						BIT20
+
+/*NPU*/
+#define		SW_NPU_AXI_RSTN						BIT0
+#define		SW_NPU_CFG_RSTN						BIT1
+#define		SW_NPU_CORE_RSTN					BIT2
+#define		SW_NPU_E31CORE_RSTN					BIT3
+#define		SW_NPU_E31BUS_RSTN					BIT4
+#define		SW_NPU_E31DBG_RSTN					BIT5
+#define		SW_NPU_LLC_RSTN						BIT6
+
+/*HSP DMA*/
+#define		SW_HSP_AXI_RSTN						BIT0
+#define		SW_HSP_CFG_RSTN						BIT1
+#define		SW_HSP_POR_RSTN						BIT2
+#define		SW_MSHC0_PHY_RSTN					BIT3
+#define		SW_MSHC1_PHY_RSTN					BIT4
+#define		SW_MSHC2_PHY_RSTN					BIT5
+#define		SW_MSHC0_TXRX_RSTN					BIT6
+#define		SW_MSHC1_TXRX_RSTN					BIT7
+#define		SW_MSHC2_TXRX_RSTN					BIT8
+#define		SW_SATA_ASIC0_RSTN					BIT9
+#define		SW_SATA_OOB_RSTN					BIT10
+#define		SW_SATA_PMALIVE_RSTN					BIT11
+#define		SW_SATA_RBC_RSTN					BIT12
+#define		SW_DMA0_RST_N						BIT13
+#define		SW_HSP_DMA0_RSTN					BIT14
+#define		SW_USB0_VAUX_RSTN					BIT15
+#define		SW_USB1_VAUX_RSTN					BIT16
+#define		SW_HSP_SD1_PRSTN					BIT17
+#define		SW_HSP_SD0_PRSTN					BIT18
+#define		SW_HSP_EMMC_PRSTN					BIT19
+#define		SW_HSP_DMA_PRSTN					BIT20
+#define		SW_HSP_SD1_ARSTN					BIT21
+#define		SW_HSP_SD0_ARSTN					BIT22
+#define		SW_HSP_EMMC_ARSTN					BIT23
+#define		SW_HSP_DMA_ARSTN					BIT24
+#define		SW_HSP_ETH1_ARSTN					BIT25
+#define		SW_HSP_ETH0_ARSTN					BIT26
+#define		SW_HSP_SATA_ARSTN					BIT27
+
+/*PCIE*/
+#define		SW_PCIE_CFG_RSTN					BIT0
+#define		SW_PCIE_POWERUP_RSTN					BIT1
+#define		SW_PCIE_PERST_N						BIT2
+
+/*I2C*/
+#define		SW_I2C_RST_N_0						BIT0
+#define		SW_I2C_RST_N_1						BIT1
+#define		SW_I2C_RST_N_2						BIT2
+#define		SW_I2C_RST_N_3						BIT3
+#define		SW_I2C_RST_N_4						BIT4
+#define		SW_I2C_RST_N_5						BIT5
+#define		SW_I2C_RST_N_6						BIT6
+#define		SW_I2C_RST_N_7						BIT7
+#define		SW_I2C_RST_N_8						BIT8
+#define		SW_I2C_RST_N_9						BIT9
+
+/*FAN*/
+#define		SW_FAN_RST_N						BIT0
+
+/*PVT*/
+#define		SW_PVT_RST_N_0						BIT0
+#define		SW_PVT_RST_N_1						BIT1
+
+/*MBOX*/
+#define		SW_MBOX_RST_N_0					BIT0
+#define		SW_MBOX_RST_N_1					BIT1
+#define		SW_MBOX_RST_N_2					BIT2
+#define		SW_MBOX_RST_N_3					BIT3
+#define		SW_MBOX_RST_N_4					BIT4
+#define		SW_MBOX_RST_N_5					BIT5
+#define		SW_MBOX_RST_N_6					BIT6
+#define		SW_MBOX_RST_N_7					BIT7
+#define		SW_MBOX_RST_N_8					BIT8
+#define		SW_MBOX_RST_N_9					BIT9
+#define		SW_MBOX_RST_N_10				BIT10
+#define		SW_MBOX_RST_N_11				BIT11
+#define		SW_MBOX_RST_N_12				BIT12
+#define		SW_MBOX_RST_N_13				BIT13
+#define		SW_MBOX_RST_N_14				BIT14
+#define		SW_MBOX_RST_N_15				BIT15
+
+/*UART*/
+#define		SW_UART_RST_N_0					BIT0
+#define		SW_UART_RST_N_1					BIT1
+#define		SW_UART_RST_N_2					BIT2
+#define		SW_UART_RST_N_3					BIT3
+#define		SW_UART_RST_N_4					BIT4
+
+/*GPIO*/
+/*
+#define		SW_GPIO_RST_N_0					BIT0
+#define		SW_GPIO_RST_N_1					BIT1
+*/
+
+/*TIMER*/
+#define		SW_TIMER_RST_N					BIT0
+
+/*SSI*/
+#define		SW_SSI_RST_N_0					BIT0
+#define		SW_SSI_RST_N_1					BIT1
+
+/*WDT*/
+#define		SW_WDT_RST_N_0					BIT0
+#define		SW_WDT_RST_N_1					BIT1
+#define		SW_WDT_RST_N_2					BIT2
+#define		SW_WDT_RST_N_3					BIT3
+
+/*LSP CFG*/
+#define		SW_LSP_CFG_RSTN					BIT0
+
+/*U84 CFG*/
+#define		SW_U84_CORE_RSTN_0				BIT0
+#define		SW_U84_CORE_RSTN_1				BIT1
+#define		SW_U84_CORE_RSTN_2				BIT2
+#define		SW_U84_CORE_RSTN_3				BIT3
+#define		SW_U84_BUS_RSTN					BIT4
+#define		SW_U84_DBG_RSTN					BIT5
+#define		SW_U84_TRACECOM_RSTN				BIT6
+#define		SW_U84_TRACE_RSTN_0				BIT8
+#define		SW_U84_TRACE_RSTN_1				BIT9
+#define		SW_U84_TRACE_RSTN_2				BIT10
+#define		SW_U84_TRACE_RSTN_3				BIT11
+
+/*SCPU*/
+#define		SW_SCPU_CORE_RSTN				BIT0
+#define		SW_SCPU_BUS_RSTN				BIT1
+#define		SW_SCPU_DBG_RSTN				BIT2
+
+/*LPCPU*/
+#define		SW_LPCPU_CORE_RSTN				BIT0
+#define		SW_LPCPU_BUS_RSTN				BIT1
+#define		SW_LPCPU_DBG_RSTN				BIT2
+
+/*VC*/
+#define		SW_VC_CFG_RSTN					BIT0
+#define		SW_VC_AXI_RSTN					BIT1
+#define		SW_VC_MONCFG_RSTN				BIT2
+
+/*JD*/
+#define		SW_JD_CFG_RSTN					BIT0
+#define		SW_JD_AXI_RSTN					BIT1
+
+/*JE*/
+#define		SW_JE_CFG_RSTN					BIT0
+#define		SW_JE_AXI_RSTN					BIT1
+
+/*VD*/
+#define		SW_VD_CFG_RSTN					BIT0
+#define		SW_VD_AXI_RSTN					BIT1
+
+/*VE*/
+#define		SW_VE_AXI_RSTN					BIT0
+#define		SW_VE_CFG_RSTN					BIT1
+
+/*G2D*/
+#define		SW_G2D_CORE_RSTN				BIT0
+#define		SW_G2D_CFG_RSTN					BIT1
+#define		SW_G2D_AXI_RSTN					BIT2
+
+/*VI*/
+#define		SW_VI_AXI_RSTN					BIT0
+#define		SW_VI_CFG_RSTN					BIT1
+#define		SW_VI_DWE_RSTN					BIT2
+
+/*DVP*/
+#define		SW_VI_DVP_RSTN					BIT0
+
+/*ISP0*/
+#define		SW_VI_ISP0_RSTN					BIT0
+
+/*ISP1*/
+#define		SW_VI_ISP1_RSTN					BIT0
+
+/*SHUTTR*/
+#define		SW_VI_SHUTTER_RSTN_0				BIT0
+#define		SW_VI_SHUTTER_RSTN_1				BIT1
+#define		SW_VI_SHUTTER_RSTN_2				BIT2
+#define		SW_VI_SHUTTER_RSTN_3				BIT3
+#define		SW_VI_SHUTTER_RSTN_4				BIT4
+#define		SW_VI_SHUTTER_RSTN_5				BIT5
+
+/*VO PHY*/
+#define		SW_VO_MIPI_PRSTN				BIT0
+#define		SW_VO_PRSTN					BIT1
+#define		SW_VO_HDMI_PRSTN				BIT3
+#define		SW_HDMI_PHYCTRL_RSTN				BIT4
+#define		SW_VO_HDMI_RSTN					BIT5
+
+/*VO I2S*/
+#define		SW_VO_I2S_RSTN					BIT0
+#define		SW_VO_I2S_PRSTN					BIT1
+
+/*VO*/
+#define		SW_VO_AXI_RSTN					BIT0
+#define		SW_VO_CFG_RSTN					BIT1
+#define		SW_VO_DC_RSTN					BIT2
+#define		SW_VO_DC_PRSTN					BIT3
+
+/*BOOTSPI*/
+#define		SW_BOOTSPI_HRSTN				BIT0
+#define		SW_BOOTSPI_RSTN					BIT1
+
+/*I2C1*/
+#define		SW_I2C1_PRSTN					BIT0
+
+/*I2C0*/
+#define		SW_I2C0_PRSTN					BIT0
+
+/*DMA1*/
+#define		SW_DMA1_ARSTN					BIT0
+#define		SW_DMA1_HRSTN					BIT1
+
+/*FPRT*/
+#define		SW_FP_PRT_HRSTN					BIT0
+
+/*HBLOCK*/
+#define		SW_HBLOCK_HRSTN					BIT0
+
+/*SECSR*/
+#define		SW_SECSR_HRSTN					BIT0
+
+/*OTP*/
+#define		SW_OTP_PRSTN					BIT0
+
+/*PKA*/
+#define		SW_PKA_HRSTN					BIT0
+
+/*SPACC*/
+#define		SW_SPACC_RSTN					BIT0
+
+/*TRNG*/
+#define		SW_TRNG_HRSTN					BIT0
+
+/*TIMER0*/
+#define		SW_TIMER0_RSTN_0				BIT0
+#define		SW_TIMER0_RSTN_1				BIT1
+#define		SW_TIMER0_RSTN_2				BIT2
+#define		SW_TIMER0_RSTN_3				BIT3
+#define		SW_TIMER0_RSTN_4				BIT4
+#define		SW_TIMER0_RSTN_5				BIT5
+#define		SW_TIMER0_RSTN_6				BIT6
+#define		SW_TIMER0_RSTN_7				BIT7
+#define		SW_TIMER0_PRSTN					BIT8
+
+/*TIMER1*/
+#define		SW_TIMER1_RSTN_0				BIT0
+#define		SW_TIMER1_RSTN_1				BIT1
+#define		SW_TIMER1_RSTN_2				BIT2
+#define		SW_TIMER1_RSTN_3				BIT3
+#define		SW_TIMER1_RSTN_4				BIT4
+#define		SW_TIMER1_RSTN_5				BIT5
+#define		SW_TIMER1_RSTN_6				BIT6
+#define		SW_TIMER1_RSTN_7				BIT7
+#define		SW_TIMER1_PRSTN					BIT8
+
+/*TIMER2*/
+#define		SW_TIMER2_RSTN_0				BIT0
+#define		SW_TIMER2_RSTN_1				BIT1
+#define		SW_TIMER2_RSTN_2				BIT2
+#define		SW_TIMER2_RSTN_3				BIT3
+#define		SW_TIMER2_RSTN_4				BIT4
+#define		SW_TIMER2_RSTN_5				BIT5
+#define		SW_TIMER2_RSTN_6				BIT6
+#define		SW_TIMER2_RSTN_7				BIT7
+#define		SW_TIMER2_PRSTN					BIT8
+
+/*TIMER3*/
+#define		SW_TIMER3_RSTN_0				BIT0
+#define		SW_TIMER3_RSTN_1				BIT1
+#define		SW_TIMER3_RSTN_2				BIT2
+#define		SW_TIMER3_RSTN_3				BIT3
+#define		SW_TIMER3_RSTN_4				BIT4
+#define		SW_TIMER3_RSTN_5				BIT5
+#define		SW_TIMER3_RSTN_6				BIT6
+#define		SW_TIMER3_RSTN_7				BIT7
+#define		SW_TIMER3_PRSTN					BIT8
+
+/*RTC*/
+#define		SW_RTC_RSTN					BIT0
+
+/*MNOC*/
+#define		SW_MNOC_SNOC_NSP_RSTN				BIT0
+#define		SW_MNOC_VC_ARSTN				BIT1
+#define		SW_MNOC_CFG_RSTN				BIT2
+#define		SW_MNOC_HSP_ARSTN				BIT3
+#define		SW_MNOC_GPU_ARSTN				BIT4
+#define		SW_MNOC_DDRC1_P3_ARSTN				BIT5
+#define		SW_MNOC_DDRC0_P3_ARSTN				BIT6
+
+/*RNOC*/
+#define		SW_RNOC_VO_ARSTN				BIT0
+#define		SW_RNOC_VI_ARSTN				BIT1
+#define		SW_RNOC_SNOC_NSP_RSTN				BIT2
+#define		SW_RNOC_CFG_RSTN				BIT3
+#define		SW_MNOC_DDRC1_P4_ARSTN				BIT4
+#define		SW_MNOC_DDRC0_P4_ARSTN				BIT5
+
+/*CNOC*/
+#define		SW_CNOC_VO_CFG_RSTN				BIT0
+#define		SW_CNOC_VI_CFG_RSTN				BIT1
+#define		SW_CNOC_VC_CFG_RSTN				BIT2
+#define		SW_CNOC_TCU_CFG_RSTN				BIT3
+#define		SW_CNOC_PCIET_CFG_RSTN				BIT4
+#define		SW_CNOC_NPU_CFG_RSTN				BIT5
+#define		SW_CNOC_LSP_CFG_RSTN				BIT6
+#define		SW_CNOC_HSP_CFG_RSTN				BIT7
+#define		SW_CNOC_GPU_CFG_RSTN				BIT8
+#define		SW_CNOC_DSPT_CFG_RSTN				BIT9
+#define		SW_CNOC_DDRT1_CFG_RSTN				BIT10
+#define		SW_CNOC_DDRT0_CFG_RSTN				BIT11
+#define		SW_CNOC_D2D_CFG_RSTN				BIT12
+#define		SW_CNOC_CFG_RSTN				BIT13
+#define		SW_CNOC_CLMM_CFG_RSTN				BIT14
+#define		SW_CNOC_AON_CFG_RSTN				BIT15
+
+/*LNOC*/
+#define		SW_LNOC_CFG_RSTN				BIT0
+#define		SW_LNOC_NPU_LLC_ARSTN				BIT1
+#define		SW_LNOC_DDRC1_P0_ARSTN				BIT2
+#define		SW_LNOC_DDRC0_P0_ARSTN				BIT3
+
+#endif /*endif __DT_ESWIN_EIC7700_SYSCRG_H__*/
diff --git a/include/dt-bindings/riscv/physical-memory.h b/include/dt-bindings/riscv/physical-memory.h
new file mode 100644
index 000000000000..7cb2e58fa8c1
--- /dev/null
+++ b/include/dt-bindings/riscv/physical-memory.h
@@ -0,0 +1,44 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+
+#ifndef _DT_BINDINGS_RISCV_PHYSICAL_MEMORY_H
+#define _DT_BINDINGS_RISCV_PHYSICAL_MEMORY_H
+
+#define PMA_READ			(1 << 0)
+#define PMA_WRITE			(1 << 1)
+#define PMA_EXECUTE			(1 << 2)
+#define PMA_AMO_MASK			(3 << 4)
+#define PMA_AMO_NONE			(0 << 4)
+#define PMA_AMO_SWAP			(1 << 4)
+#define PMA_AMO_LOGICAL			(2 << 4)
+#define PMA_AMO_ARITHMETIC		(3 << 4)
+#define PMA_RSRV_MASK			(3 << 6)
+#define PMA_RSRV_NONE			(0 << 6)
+#define PMA_RSRV_NON_EVENTUAL		(1 << 6)
+#define PMA_RSRV_EVENTUAL		(2 << 6)
+
+#define PMA_RW				(PMA_READ | PMA_WRITE)
+#define PMA_RWA				(PMA_RW | PMA_AMO_ARITHMETIC | PMA_RSRV_EVENTUAL)
+#define PMA_RWX				(PMA_RW | PMA_EXECUTE)
+#define PMA_RWXA			(PMA_RWA | PMA_EXECUTE)
+
+#define PMA_ORDER_MASK			(3 << 8)
+#define PMA_ORDER_IO_RELAXED		(0 << 8)
+#define PMA_ORDER_IO_STRONG		(1 << 8)
+#define PMA_ORDER_MEMORY		(2 << 8)
+#define PMA_READ_IDEMPOTENT		(1 << 10)
+#define PMA_WRITE_IDEMPOTENT		(1 << 11)
+#define PMA_CACHEABLE			(1 << 12)
+#define PMA_COHERENT			(1 << 13)
+
+#define PMA_UNSAFE			(1 << 15)
+
+#define PMA_IO				(PMA_ORDER_IO_RELAXED)
+#define PMA_NONCACHEABLE_MEMORY		(PMA_ORDER_MEMORY | PMA_READ_IDEMPOTENT | \
+						PMA_WRITE_IDEMPOTENT)
+#define PMA_NONCOHERENT_MEMORY		(PMA_NONCACHEABLE_MEMORY | PMA_CACHEABLE)
+#define PMA_NORMAL_MEMORY		(PMA_NONCOHERENT_MEMORY | PMA_COHERENT)
+
+#define PMR_ALIAS_MASK			(0xff << 24)
+#define PMR_ALIAS(n)			((n) << 24)
+
+#endif /* _DT_BINDINGS_RISCV_PHYSICAL_MEMORY_H */
